xref: /llvm-project/llvm/test/CodeGen/RISCV/rv32e.ll (revision 3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a)
1*3ac9fe69SWang Pengcheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2*3ac9fe69SWang Pengcheng; RUN: llc -mtriple=riscv32 -mattr=+e -verify-machineinstrs < %s \
3*3ac9fe69SWang Pengcheng; RUN:   | FileCheck %s
4*3ac9fe69SWang Pengcheng
5*3ac9fe69SWang Pengcheng; TODO: Add more tests.
6*3ac9fe69SWang Pengcheng
7*3ac9fe69SWang Pengchengdefine i32 @exhausted(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
8*3ac9fe69SWang Pengcheng; CHECK-LABEL: exhausted:
9*3ac9fe69SWang Pengcheng; CHECK:       # %bb.0:
10*3ac9fe69SWang Pengcheng; CHECK-NEXT:    lw t0, 0(sp)
11*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a0, a0, a1
12*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a2, a3, a2
13*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a0, a2, a0
14*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a4, a5, a4
15*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a0, a4, a0
16*3ac9fe69SWang Pengcheng; CHECK-NEXT:    add a0, t0, a0
17*3ac9fe69SWang Pengcheng; CHECK-NEXT:    ret
18*3ac9fe69SWang Pengcheng  %1 = add i32 %a, %b
19*3ac9fe69SWang Pengcheng  %2 = add i32 %c, %1
20*3ac9fe69SWang Pengcheng  %3 = add i32 %d, %2
21*3ac9fe69SWang Pengcheng  %4 = add i32 %e, %3
22*3ac9fe69SWang Pengcheng  %5 = add i32 %f, %4
23*3ac9fe69SWang Pengcheng  %6 = add i32 %g, %5
24*3ac9fe69SWang Pengcheng  ret i32 %6
25*3ac9fe69SWang Pengcheng}
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