1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs | FileCheck %s -check-prefixes=RV32 3; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs | FileCheck %s -check-prefixes=RV64 4 5; Test case: 6; - `A[row]` is loop invariant and should be hoisted up to preheader 7; FIXME: RV32 is working as expected, but RV64 doesn't 8 9; The following LLVM IR simulates: 10; int A[16][16]; 11; void test(int row, int N) { 12; for (int i=0; i<N; ++I) { 13; A[row][i+1] = 4; 14; A[row][i+2] = 5; 15; } 16; } 17 18; After LSR: 19; int A[16][16]; 20; void test(int row, int N) { 21; for (int *ptr = A[row][2]; N>0; N--) { 22; *(ptr-1) = 4; 23; *(ptr) = 5; 24; ++ptr; 25; } 26; } 27 28@A = internal global [16 x [16 x i32]] zeroinitializer, align 32 ; <ptr> [#uses=2] 29 30define void @test(i32 signext %row, i32 signext %N.in) nounwind { 31; RV32-LABEL: test: 32; RV32: # %bb.0: # %entry 33; RV32-NEXT: blez a1, .LBB0_3 34; RV32-NEXT: # %bb.1: # %cond_true.preheader 35; RV32-NEXT: slli a0, a0, 6 36; RV32-NEXT: lui a2, %hi(A) 37; RV32-NEXT: addi a2, a2, %lo(A) 38; RV32-NEXT: add a0, a0, a2 39; RV32-NEXT: addi a0, a0, 8 40; RV32-NEXT: li a2, 4 41; RV32-NEXT: li a3, 5 42; RV32-NEXT: .LBB0_2: # %cond_true 43; RV32-NEXT: # =>This Inner Loop Header: Depth=1 44; RV32-NEXT: sw a2, -4(a0) 45; RV32-NEXT: sw a3, 0(a0) 46; RV32-NEXT: addi a1, a1, -1 47; RV32-NEXT: addi a0, a0, 4 48; RV32-NEXT: bnez a1, .LBB0_2 49; RV32-NEXT: .LBB0_3: # %return 50; RV32-NEXT: ret 51; 52; RV64-LABEL: test: 53; RV64: # %bb.0: # %entry 54; RV64-NEXT: blez a1, .LBB0_3 55; RV64-NEXT: # %bb.1: # %cond_true.preheader 56; RV64-NEXT: negw a1, a1 57; RV64-NEXT: slli a0, a0, 6 58; RV64-NEXT: lui a2, %hi(A) 59; RV64-NEXT: addi a2, a2, %lo(A) 60; RV64-NEXT: add a0, a0, a2 61; RV64-NEXT: addi a2, a0, 4 62; RV64-NEXT: li a3, 2 63; RV64-NEXT: li a4, 4 64; RV64-NEXT: li a5, 5 65; RV64-NEXT: li a6, 2 66; RV64-NEXT: .LBB0_2: # %cond_true 67; RV64-NEXT: # =>This Inner Loop Header: Depth=1 68; RV64-NEXT: sw a4, 0(a2) 69; RV64-NEXT: slli a7, a6, 2 70; RV64-NEXT: add a7, a0, a7 71; RV64-NEXT: sw a5, 0(a7) 72; RV64-NEXT: addiw a6, a6, 1 73; RV64-NEXT: addw a7, a1, a6 74; RV64-NEXT: addi a2, a2, 4 75; RV64-NEXT: bne a7, a3, .LBB0_2 76; RV64-NEXT: .LBB0_3: # %return 77; RV64-NEXT: ret 78entry: 79 %N = bitcast i32 %N.in to i32 80 %tmp5 = icmp sgt i32 %N.in, 0 81 br i1 %tmp5, label %cond_true, label %return 82 83cond_true: 84 %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] 85 %tmp2 = add i32 %indvar, 1 86 %tmp = getelementptr [16 x [16 x i32]], ptr @A, i32 0, i32 %row, i32 %tmp2 87 store i32 4, ptr %tmp 88 %tmp5.upgrd.1 = add i32 %indvar, 2 89 %tmp7 = getelementptr [16 x [16 x i32]], ptr @A, i32 0, i32 %row, i32 %tmp5.upgrd.1 90 store i32 5, ptr %tmp7 91 %indvar.next = add i32 %indvar, 1 92 %exitcond = icmp eq i32 %indvar.next, %N 93 br i1 %exitcond, label %return, label %cond_true 94 95return: 96 ret void 97} 98