1dba54fb0SJim Lin; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2dba54fb0SJim Lin; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ 3dba54fb0SJim Lin; RUN: | FileCheck -check-prefix=RV32I %s 4dba54fb0SJim Lin; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ 5dba54fb0SJim Lin; RUN: | FileCheck -check-prefix=RV64I %s 6dba54fb0SJim Lin 7dba54fb0SJim Lindefine <vscale x 1 x i8> @constraint_vr(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind { 8dba54fb0SJim Lin; RV32I-LABEL: constraint_vr: 9dba54fb0SJim Lin; RV32I: # %bb.0: 10dba54fb0SJim Lin; RV32I-NEXT: #APP 11dba54fb0SJim Lin; RV32I-NEXT: vadd.vv v8, v8, v9 12dba54fb0SJim Lin; RV32I-NEXT: #NO_APP 13dba54fb0SJim Lin; RV32I-NEXT: ret 14dba54fb0SJim Lin; 15dba54fb0SJim Lin; RV64I-LABEL: constraint_vr: 16dba54fb0SJim Lin; RV64I: # %bb.0: 17dba54fb0SJim Lin; RV64I-NEXT: #APP 18dba54fb0SJim Lin; RV64I-NEXT: vadd.vv v8, v8, v9 19dba54fb0SJim Lin; RV64I-NEXT: #NO_APP 20dba54fb0SJim Lin; RV64I-NEXT: ret 21dba54fb0SJim Lin %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"( 22dba54fb0SJim Lin <vscale x 1 x i8> %0, <vscale x 1 x i8> %1) 23dba54fb0SJim Lin ret <vscale x 1 x i8> %a 24dba54fb0SJim Lin} 25dba54fb0SJim Lin 26dba54fb0SJim Lindefine <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind { 27dba54fb0SJim Lin; RV32I-LABEL: constraint_vd: 28dba54fb0SJim Lin; RV32I: # %bb.0: 29dba54fb0SJim Lin; RV32I-NEXT: #APP 30dba54fb0SJim Lin; RV32I-NEXT: vadd.vv v8, v8, v9 31dba54fb0SJim Lin; RV32I-NEXT: #NO_APP 32dba54fb0SJim Lin; RV32I-NEXT: ret 33dba54fb0SJim Lin; 34dba54fb0SJim Lin; RV64I-LABEL: constraint_vd: 35dba54fb0SJim Lin; RV64I: # %bb.0: 36dba54fb0SJim Lin; RV64I-NEXT: #APP 37dba54fb0SJim Lin; RV64I-NEXT: vadd.vv v8, v8, v9 38dba54fb0SJim Lin; RV64I-NEXT: #NO_APP 39dba54fb0SJim Lin; RV64I-NEXT: ret 40dba54fb0SJim Lin %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"( 41dba54fb0SJim Lin <vscale x 1 x i8> %0, <vscale x 1 x i8> %1) 42dba54fb0SJim Lin ret <vscale x 1 x i8> %a 43dba54fb0SJim Lin} 44dba54fb0SJim Lin 45dba54fb0SJim Lindefine <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind { 46dba54fb0SJim Lin; RV32I-LABEL: constraint_vm: 47dba54fb0SJim Lin; RV32I: # %bb.0: 48*b6c0f1bfSLuke Lau; RV32I-NEXT: vsetivli zero, 1, e8, m1, ta, ma 49dba54fb0SJim Lin; RV32I-NEXT: vmv1r.v v9, v0 50dba54fb0SJim Lin; RV32I-NEXT: vmv1r.v v0, v8 51dba54fb0SJim Lin; RV32I-NEXT: #APP 52dba54fb0SJim Lin; RV32I-NEXT: vadd.vv v0, v9, v0 53dba54fb0SJim Lin; RV32I-NEXT: #NO_APP 54dba54fb0SJim Lin; RV32I-NEXT: ret 55dba54fb0SJim Lin; 56dba54fb0SJim Lin; RV64I-LABEL: constraint_vm: 57dba54fb0SJim Lin; RV64I: # %bb.0: 58*b6c0f1bfSLuke Lau; RV64I-NEXT: vsetivli zero, 1, e8, m1, ta, ma 59dba54fb0SJim Lin; RV64I-NEXT: vmv1r.v v9, v0 60dba54fb0SJim Lin; RV64I-NEXT: vmv1r.v v0, v8 61dba54fb0SJim Lin; RV64I-NEXT: #APP 62dba54fb0SJim Lin; RV64I-NEXT: vadd.vv v0, v9, v0 63dba54fb0SJim Lin; RV64I-NEXT: #NO_APP 64dba54fb0SJim Lin; RV64I-NEXT: ret 65dba54fb0SJim Lin %a = tail call <vscale x 1 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"( 66dba54fb0SJim Lin <vscale x 1 x i1> %0, <vscale x 1 x i1> %1) 67dba54fb0SJim Lin ret <vscale x 1 x i1> %a 68dba54fb0SJim Lin} 69