xref: /llvm-project/llvm/test/CodeGen/RISCV/float-round-conv.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343)
1be1cc64cSCraig Topper; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2be1cc64cSCraig Topper; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3be1cc64cSCraig Topper; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
4be1cc64cSCraig Topper; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5be1cc64cSCraig Topper; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
6fe558efeSShao-Ce SUN; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
7fe558efeSShao-Ce SUN; RUN:   -target-abi=ilp32 | FileCheck -check-prefix=RV32IZFINX %s
8fe558efeSShao-Ce SUN; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
9fe558efeSShao-Ce SUN; RUN:   -target-abi=lp64 | FileCheck -check-prefix=RV64IZFINX %s
10be1cc64cSCraig Topper
11be1cc64cSCraig Topperdefine signext i8 @test_floor_si8(float %x) {
12be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_si8:
13be1cc64cSCraig Topper; RV32IF:       # %bb.0:
14be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
15be1cc64cSCraig Topper; RV32IF-NEXT:    ret
16be1cc64cSCraig Topper;
17be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_si8:
18be1cc64cSCraig Topper; RV64IF:       # %bb.0:
19be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
20be1cc64cSCraig Topper; RV64IF-NEXT:    ret
21fe558efeSShao-Ce SUN;
22fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_si8:
23fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
24fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
25fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
26fe558efeSShao-Ce SUN;
27fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_si8:
28fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
29fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
30fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
31be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
32be1cc64cSCraig Topper  %b = fptosi float %a to i8
33be1cc64cSCraig Topper  ret i8 %b
34be1cc64cSCraig Topper}
35be1cc64cSCraig Topper
36be1cc64cSCraig Topperdefine signext i16 @test_floor_si16(float %x) {
37be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_si16:
38be1cc64cSCraig Topper; RV32IF:       # %bb.0:
39be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
40be1cc64cSCraig Topper; RV32IF-NEXT:    ret
41be1cc64cSCraig Topper;
42be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_si16:
43be1cc64cSCraig Topper; RV64IF:       # %bb.0:
44be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
45be1cc64cSCraig Topper; RV64IF-NEXT:    ret
46fe558efeSShao-Ce SUN;
47fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_si16:
48fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
49fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
50fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
51fe558efeSShao-Ce SUN;
52fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_si16:
53fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
54fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
55fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
56be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
57be1cc64cSCraig Topper  %b = fptosi float %a to i16
58be1cc64cSCraig Topper  ret i16 %b
59be1cc64cSCraig Topper}
60be1cc64cSCraig Topper
61be1cc64cSCraig Topperdefine signext i32 @test_floor_si32(float %x) {
62be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_si32:
63be1cc64cSCraig Topper; RV32IF:       # %bb.0:
64be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
65be1cc64cSCraig Topper; RV32IF-NEXT:    ret
66be1cc64cSCraig Topper;
67be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_si32:
68be1cc64cSCraig Topper; RV64IF:       # %bb.0:
69be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
70be1cc64cSCraig Topper; RV64IF-NEXT:    ret
71fe558efeSShao-Ce SUN;
72fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_si32:
73fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
74fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
75fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
76fe558efeSShao-Ce SUN;
77fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_si32:
78fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
79fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a0, a0, rdn
80fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
81be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
82be1cc64cSCraig Topper  %b = fptosi float %a to i32
83be1cc64cSCraig Topper  ret i32 %b
84be1cc64cSCraig Topper}
85be1cc64cSCraig Topper
86be1cc64cSCraig Topperdefine i64 @test_floor_si64(float %x) {
87be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_si64:
88be1cc64cSCraig Topper; RV32IF:       # %bb.0:
89d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
907b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
917b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
927b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
93e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB3_2
94e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
95e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
967b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
977b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
98e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB3_2:
99d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
100d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
101d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
102d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
103eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixsfdi
104be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
105*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
106be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
107*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
108be1cc64cSCraig Topper; RV32IF-NEXT:    ret
109be1cc64cSCraig Topper;
110be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_si64:
111be1cc64cSCraig Topper; RV64IF:       # %bb.0:
112be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
113be1cc64cSCraig Topper; RV64IF-NEXT:    ret
114fe558efeSShao-Ce SUN;
115fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_si64:
116fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
117fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
118fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
119fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
120fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB3_2
121fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
122fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rdn
123fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rdn
124fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
125fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB3_2:
126fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
127fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
128fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
129fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
130eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixsfdi
131fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
132*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
133fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
134*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
135fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
136fe558efeSShao-Ce SUN;
137fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_si64:
138fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
139fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rdn
140fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
141be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
142be1cc64cSCraig Topper  %b = fptosi float %a to i64
143be1cc64cSCraig Topper  ret i64 %b
144be1cc64cSCraig Topper}
145be1cc64cSCraig Topper
146be1cc64cSCraig Topperdefine zeroext i8 @test_floor_ui8(float %x) {
147be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_ui8:
148be1cc64cSCraig Topper; RV32IF:       # %bb.0:
149be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
150be1cc64cSCraig Topper; RV32IF-NEXT:    ret
151be1cc64cSCraig Topper;
152be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_ui8:
153be1cc64cSCraig Topper; RV64IF:       # %bb.0:
154be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
155be1cc64cSCraig Topper; RV64IF-NEXT:    ret
156fe558efeSShao-Ce SUN;
157fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_ui8:
158fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
159fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
160fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
161fe558efeSShao-Ce SUN;
162fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_ui8:
163fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
164fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
165fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
166be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
167be1cc64cSCraig Topper  %b = fptoui float %a to i8
168be1cc64cSCraig Topper  ret i8 %b
169be1cc64cSCraig Topper}
170be1cc64cSCraig Topper
171be1cc64cSCraig Topperdefine zeroext i16 @test_floor_ui16(float %x) {
172be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_ui16:
173be1cc64cSCraig Topper; RV32IF:       # %bb.0:
174be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
175be1cc64cSCraig Topper; RV32IF-NEXT:    ret
176be1cc64cSCraig Topper;
177be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_ui16:
178be1cc64cSCraig Topper; RV64IF:       # %bb.0:
179be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
180be1cc64cSCraig Topper; RV64IF-NEXT:    ret
181fe558efeSShao-Ce SUN;
182fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_ui16:
183fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
184fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
185fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
186fe558efeSShao-Ce SUN;
187fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_ui16:
188fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
189fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
190fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
191be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
192be1cc64cSCraig Topper  %b = fptoui float %a to i16
193be1cc64cSCraig Topper  ret i16 %b
194be1cc64cSCraig Topper}
195be1cc64cSCraig Topper
196be1cc64cSCraig Topperdefine signext i32 @test_floor_ui32(float %x) {
197be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_ui32:
198be1cc64cSCraig Topper; RV32IF:       # %bb.0:
199be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
200be1cc64cSCraig Topper; RV32IF-NEXT:    ret
201be1cc64cSCraig Topper;
202be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_ui32:
203be1cc64cSCraig Topper; RV64IF:       # %bb.0:
204be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
205be1cc64cSCraig Topper; RV64IF-NEXT:    ret
206fe558efeSShao-Ce SUN;
207fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_ui32:
208fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
209fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
210fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
211fe558efeSShao-Ce SUN;
212fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_ui32:
213fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
214fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.wu.s a0, a0, rdn
215fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
216be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
217be1cc64cSCraig Topper  %b = fptoui float %a to i32
218be1cc64cSCraig Topper  ret i32 %b
219be1cc64cSCraig Topper}
220be1cc64cSCraig Topper
221be1cc64cSCraig Topperdefine i64 @test_floor_ui64(float %x) {
222be1cc64cSCraig Topper; RV32IF-LABEL: test_floor_ui64:
223be1cc64cSCraig Topper; RV32IF:       # %bb.0:
224d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
2257b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
2267b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
2277b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
228e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB7_2
229e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
230e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
2317b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
2327b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
233e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB7_2:
234d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
235d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
236d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
237d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
238eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixunssfdi
239be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
240*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
241be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
242*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
243be1cc64cSCraig Topper; RV32IF-NEXT:    ret
244be1cc64cSCraig Topper;
245be1cc64cSCraig Topper; RV64IF-LABEL: test_floor_ui64:
246be1cc64cSCraig Topper; RV64IF:       # %bb.0:
247be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
248be1cc64cSCraig Topper; RV64IF-NEXT:    ret
249fe558efeSShao-Ce SUN;
250fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_ui64:
251fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
252fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
253fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
254fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
255fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB7_2
256fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
257fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rdn
258fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rdn
259fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
260fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB7_2:
261fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
262fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
263fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
264fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
265eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixunssfdi
266fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
267*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
268fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
269*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
270fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
271fe558efeSShao-Ce SUN;
272fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_ui64:
273fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
274fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rdn
275fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
276be1cc64cSCraig Topper  %a = call float @llvm.floor.f32(float %x)
277be1cc64cSCraig Topper  %b = fptoui float %a to i64
278be1cc64cSCraig Topper  ret i64 %b
279be1cc64cSCraig Topper}
280be1cc64cSCraig Topper
281be1cc64cSCraig Topperdefine signext i8 @test_ceil_si8(float %x) {
282be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_si8:
283be1cc64cSCraig Topper; RV32IF:       # %bb.0:
284be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
285be1cc64cSCraig Topper; RV32IF-NEXT:    ret
286be1cc64cSCraig Topper;
287be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_si8:
288be1cc64cSCraig Topper; RV64IF:       # %bb.0:
289be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
290be1cc64cSCraig Topper; RV64IF-NEXT:    ret
291fe558efeSShao-Ce SUN;
292fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_si8:
293fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
294fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rup
295fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
296fe558efeSShao-Ce SUN;
297fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_si8:
298fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
299fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
300fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
301be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
302be1cc64cSCraig Topper  %b = fptosi float %a to i8
303be1cc64cSCraig Topper  ret i8 %b
304be1cc64cSCraig Topper}
305be1cc64cSCraig Topper
306be1cc64cSCraig Topperdefine signext i16 @test_ceil_si16(float %x) {
307be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_si16:
308be1cc64cSCraig Topper; RV32IF:       # %bb.0:
309be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
310be1cc64cSCraig Topper; RV32IF-NEXT:    ret
311be1cc64cSCraig Topper;
312be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_si16:
313be1cc64cSCraig Topper; RV64IF:       # %bb.0:
314be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
315be1cc64cSCraig Topper; RV64IF-NEXT:    ret
316fe558efeSShao-Ce SUN;
317fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_si16:
318fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
319fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rup
320fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
321fe558efeSShao-Ce SUN;
322fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_si16:
323fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
324fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
325fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
326be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
327be1cc64cSCraig Topper  %b = fptosi float %a to i16
328be1cc64cSCraig Topper  ret i16 %b
329be1cc64cSCraig Topper}
330be1cc64cSCraig Topper
331be1cc64cSCraig Topperdefine signext i32 @test_ceil_si32(float %x) {
332be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_si32:
333be1cc64cSCraig Topper; RV32IF:       # %bb.0:
334be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
335be1cc64cSCraig Topper; RV32IF-NEXT:    ret
336be1cc64cSCraig Topper;
337be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_si32:
338be1cc64cSCraig Topper; RV64IF:       # %bb.0:
339be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
340be1cc64cSCraig Topper; RV64IF-NEXT:    ret
341fe558efeSShao-Ce SUN;
342fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_si32:
343fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
344fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rup
345fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
346fe558efeSShao-Ce SUN;
347fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_si32:
348fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
349fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a0, a0, rup
350fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
351be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
352be1cc64cSCraig Topper  %b = fptosi float %a to i32
353be1cc64cSCraig Topper  ret i32 %b
354be1cc64cSCraig Topper}
355be1cc64cSCraig Topper
356be1cc64cSCraig Topperdefine i64 @test_ceil_si64(float %x) {
357be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_si64:
358be1cc64cSCraig Topper; RV32IF:       # %bb.0:
359d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
3607b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
3617b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
3627b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
363e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB11_2
364e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
365e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
3667b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
3677b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
368e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB11_2:
369d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
370d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
371d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
372d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
373eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixsfdi
374be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
375*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
376be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
377*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
378be1cc64cSCraig Topper; RV32IF-NEXT:    ret
379be1cc64cSCraig Topper;
380be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_si64:
381be1cc64cSCraig Topper; RV64IF:       # %bb.0:
382be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
383be1cc64cSCraig Topper; RV64IF-NEXT:    ret
384fe558efeSShao-Ce SUN;
385fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_si64:
386fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
387fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
388fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
389fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
390fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB11_2
391fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
392fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rup
393fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rup
394fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
395fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB11_2:
396fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
397fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
398fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
399fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
400eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixsfdi
401fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
402*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
403fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
404*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
405fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
406fe558efeSShao-Ce SUN;
407fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_si64:
408fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
409fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rup
410fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
411be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
412be1cc64cSCraig Topper  %b = fptosi float %a to i64
413be1cc64cSCraig Topper  ret i64 %b
414be1cc64cSCraig Topper}
415be1cc64cSCraig Topper
416be1cc64cSCraig Topperdefine zeroext i8 @test_ceil_ui8(float %x) {
417be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_ui8:
418be1cc64cSCraig Topper; RV32IF:       # %bb.0:
419be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
420be1cc64cSCraig Topper; RV32IF-NEXT:    ret
421be1cc64cSCraig Topper;
422be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_ui8:
423be1cc64cSCraig Topper; RV64IF:       # %bb.0:
424be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
425be1cc64cSCraig Topper; RV64IF-NEXT:    ret
426fe558efeSShao-Ce SUN;
427fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_ui8:
428fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
429fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
430fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
431fe558efeSShao-Ce SUN;
432fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_ui8:
433fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
434fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
435fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
436be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
437be1cc64cSCraig Topper  %b = fptoui float %a to i8
438be1cc64cSCraig Topper  ret i8 %b
439be1cc64cSCraig Topper}
440be1cc64cSCraig Topper
441be1cc64cSCraig Topperdefine zeroext i16 @test_ceil_ui16(float %x) {
442be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_ui16:
443be1cc64cSCraig Topper; RV32IF:       # %bb.0:
444be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
445be1cc64cSCraig Topper; RV32IF-NEXT:    ret
446be1cc64cSCraig Topper;
447be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_ui16:
448be1cc64cSCraig Topper; RV64IF:       # %bb.0:
449be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
450be1cc64cSCraig Topper; RV64IF-NEXT:    ret
451fe558efeSShao-Ce SUN;
452fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_ui16:
453fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
454fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
455fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
456fe558efeSShao-Ce SUN;
457fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_ui16:
458fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
459fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
460fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
461be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
462be1cc64cSCraig Topper  %b = fptoui float %a to i16
463be1cc64cSCraig Topper  ret i16 %b
464be1cc64cSCraig Topper}
465be1cc64cSCraig Topper
466be1cc64cSCraig Topperdefine signext i32 @test_ceil_ui32(float %x) {
467be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_ui32:
468be1cc64cSCraig Topper; RV32IF:       # %bb.0:
469be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
470be1cc64cSCraig Topper; RV32IF-NEXT:    ret
471be1cc64cSCraig Topper;
472be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_ui32:
473be1cc64cSCraig Topper; RV64IF:       # %bb.0:
474be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
475be1cc64cSCraig Topper; RV64IF-NEXT:    ret
476fe558efeSShao-Ce SUN;
477fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_ui32:
478fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
479fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
480fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
481fe558efeSShao-Ce SUN;
482fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_ui32:
483fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
484fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.wu.s a0, a0, rup
485fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
486be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
487be1cc64cSCraig Topper  %b = fptoui float %a to i32
488be1cc64cSCraig Topper  ret i32 %b
489be1cc64cSCraig Topper}
490be1cc64cSCraig Topper
491be1cc64cSCraig Topperdefine i64 @test_ceil_ui64(float %x) {
492be1cc64cSCraig Topper; RV32IF-LABEL: test_ceil_ui64:
493be1cc64cSCraig Topper; RV32IF:       # %bb.0:
494d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
4957b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
4967b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
4977b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
498e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB15_2
499e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
500e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
5017b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
5027b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
503e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB15_2:
504d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
505d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
506d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
507d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
508eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixunssfdi
509be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
510*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
511be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
512*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
513be1cc64cSCraig Topper; RV32IF-NEXT:    ret
514be1cc64cSCraig Topper;
515be1cc64cSCraig Topper; RV64IF-LABEL: test_ceil_ui64:
516be1cc64cSCraig Topper; RV64IF:       # %bb.0:
517be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
518be1cc64cSCraig Topper; RV64IF-NEXT:    ret
519fe558efeSShao-Ce SUN;
520fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_ui64:
521fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
522fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
523fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
524fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
525fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB15_2
526fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
527fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rup
528fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rup
529fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
530fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB15_2:
531fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
532fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
533fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
534fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
535eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixunssfdi
536fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
537*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
538fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
539*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
540fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
541fe558efeSShao-Ce SUN;
542fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_ui64:
543fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
544fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rup
545fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
546be1cc64cSCraig Topper  %a = call float @llvm.ceil.f32(float %x)
547be1cc64cSCraig Topper  %b = fptoui float %a to i64
548be1cc64cSCraig Topper  ret i64 %b
549be1cc64cSCraig Topper}
550be1cc64cSCraig Topper
551be1cc64cSCraig Topperdefine signext i8 @test_trunc_si8(float %x) {
552be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_si8:
553be1cc64cSCraig Topper; RV32IF:       # %bb.0:
554be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
555be1cc64cSCraig Topper; RV32IF-NEXT:    ret
556be1cc64cSCraig Topper;
557be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_si8:
558be1cc64cSCraig Topper; RV64IF:       # %bb.0:
559be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
560be1cc64cSCraig Topper; RV64IF-NEXT:    ret
561fe558efeSShao-Ce SUN;
562fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_si8:
563fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
564fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
565fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
566fe558efeSShao-Ce SUN;
567fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_si8:
568fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
569fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
570fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
571be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
572be1cc64cSCraig Topper  %b = fptosi float %a to i8
573be1cc64cSCraig Topper  ret i8 %b
574be1cc64cSCraig Topper}
575be1cc64cSCraig Topper
576be1cc64cSCraig Topperdefine signext i16 @test_trunc_si16(float %x) {
577be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_si16:
578be1cc64cSCraig Topper; RV32IF:       # %bb.0:
579be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
580be1cc64cSCraig Topper; RV32IF-NEXT:    ret
581be1cc64cSCraig Topper;
582be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_si16:
583be1cc64cSCraig Topper; RV64IF:       # %bb.0:
584be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
585be1cc64cSCraig Topper; RV64IF-NEXT:    ret
586fe558efeSShao-Ce SUN;
587fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_si16:
588fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
589fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
590fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
591fe558efeSShao-Ce SUN;
592fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_si16:
593fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
594fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
595fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
596be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
597be1cc64cSCraig Topper  %b = fptosi float %a to i16
598be1cc64cSCraig Topper  ret i16 %b
599be1cc64cSCraig Topper}
600be1cc64cSCraig Topper
601be1cc64cSCraig Topperdefine signext i32 @test_trunc_si32(float %x) {
602be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_si32:
603be1cc64cSCraig Topper; RV32IF:       # %bb.0:
604be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
605be1cc64cSCraig Topper; RV32IF-NEXT:    ret
606be1cc64cSCraig Topper;
607be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_si32:
608be1cc64cSCraig Topper; RV64IF:       # %bb.0:
609be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
610be1cc64cSCraig Topper; RV64IF-NEXT:    ret
611fe558efeSShao-Ce SUN;
612fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_si32:
613fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
614fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
615fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
616fe558efeSShao-Ce SUN;
617fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_si32:
618fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
619fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a0, a0, rtz
620fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
621be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
622be1cc64cSCraig Topper  %b = fptosi float %a to i32
623be1cc64cSCraig Topper  ret i32 %b
624be1cc64cSCraig Topper}
625be1cc64cSCraig Topper
626be1cc64cSCraig Topperdefine i64 @test_trunc_si64(float %x) {
627be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_si64:
628be1cc64cSCraig Topper; RV32IF:       # %bb.0:
629d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
6307b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
6317b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
6327b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
633e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB19_2
634e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
635e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
6367b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
6377b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
638e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB19_2:
639d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
640d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
641d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
642d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
643eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixsfdi
644be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
645*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
646be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
647*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
648be1cc64cSCraig Topper; RV32IF-NEXT:    ret
649be1cc64cSCraig Topper;
650be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_si64:
651be1cc64cSCraig Topper; RV64IF:       # %bb.0:
652be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
653be1cc64cSCraig Topper; RV64IF-NEXT:    ret
654fe558efeSShao-Ce SUN;
655fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_si64:
656fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
657fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
658fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
659fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
660fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB19_2
661fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
662fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rtz
663fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rtz
664fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
665fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB19_2:
666fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
667fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
668fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
669fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
670eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixsfdi
671fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
672*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
673fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
674*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
675fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
676fe558efeSShao-Ce SUN;
677fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_si64:
678fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
679fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rtz
680fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
681be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
682be1cc64cSCraig Topper  %b = fptosi float %a to i64
683be1cc64cSCraig Topper  ret i64 %b
684be1cc64cSCraig Topper}
685be1cc64cSCraig Topper
686be1cc64cSCraig Topperdefine zeroext i8 @test_trunc_ui8(float %x) {
687be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_ui8:
688be1cc64cSCraig Topper; RV32IF:       # %bb.0:
689be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
690be1cc64cSCraig Topper; RV32IF-NEXT:    ret
691be1cc64cSCraig Topper;
692be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_ui8:
693be1cc64cSCraig Topper; RV64IF:       # %bb.0:
694be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
695be1cc64cSCraig Topper; RV64IF-NEXT:    ret
696fe558efeSShao-Ce SUN;
697fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_ui8:
698fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
699fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
700fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
701fe558efeSShao-Ce SUN;
702fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_ui8:
703fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
704fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
705fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
706be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
707be1cc64cSCraig Topper  %b = fptoui float %a to i8
708be1cc64cSCraig Topper  ret i8 %b
709be1cc64cSCraig Topper}
710be1cc64cSCraig Topper
711be1cc64cSCraig Topperdefine zeroext i16 @test_trunc_ui16(float %x) {
712be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_ui16:
713be1cc64cSCraig Topper; RV32IF:       # %bb.0:
714be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
715be1cc64cSCraig Topper; RV32IF-NEXT:    ret
716be1cc64cSCraig Topper;
717be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_ui16:
718be1cc64cSCraig Topper; RV64IF:       # %bb.0:
719be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
720be1cc64cSCraig Topper; RV64IF-NEXT:    ret
721fe558efeSShao-Ce SUN;
722fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_ui16:
723fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
724fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
725fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
726fe558efeSShao-Ce SUN;
727fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_ui16:
728fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
729fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
730fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
731be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
732be1cc64cSCraig Topper  %b = fptoui float %a to i16
733be1cc64cSCraig Topper  ret i16 %b
734be1cc64cSCraig Topper}
735be1cc64cSCraig Topper
736be1cc64cSCraig Topperdefine signext i32 @test_trunc_ui32(float %x) {
737be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_ui32:
738be1cc64cSCraig Topper; RV32IF:       # %bb.0:
739be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
740be1cc64cSCraig Topper; RV32IF-NEXT:    ret
741be1cc64cSCraig Topper;
742be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_ui32:
743be1cc64cSCraig Topper; RV64IF:       # %bb.0:
744be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
745be1cc64cSCraig Topper; RV64IF-NEXT:    ret
746fe558efeSShao-Ce SUN;
747fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_ui32:
748fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
749fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
750fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
751fe558efeSShao-Ce SUN;
752fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_ui32:
753fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
754fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.wu.s a0, a0, rtz
755fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
756be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
757be1cc64cSCraig Topper  %b = fptoui float %a to i32
758be1cc64cSCraig Topper  ret i32 %b
759be1cc64cSCraig Topper}
760be1cc64cSCraig Topper
761be1cc64cSCraig Topperdefine i64 @test_trunc_ui64(float %x) {
762be1cc64cSCraig Topper; RV32IF-LABEL: test_trunc_ui64:
763be1cc64cSCraig Topper; RV32IF:       # %bb.0:
764d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
7657b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
7667b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
7677b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
768e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB23_2
769e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
770e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
7717b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
7727b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
773e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB23_2:
774d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
775d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
776d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
777d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
778eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixunssfdi
779be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
780*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
781be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
782*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
783be1cc64cSCraig Topper; RV32IF-NEXT:    ret
784be1cc64cSCraig Topper;
785be1cc64cSCraig Topper; RV64IF-LABEL: test_trunc_ui64:
786be1cc64cSCraig Topper; RV64IF:       # %bb.0:
787be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
788be1cc64cSCraig Topper; RV64IF-NEXT:    ret
789fe558efeSShao-Ce SUN;
790fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_ui64:
791fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
792fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
793fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
794fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
795fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB23_2
796fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
797fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rtz
798fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rtz
799fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
800fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB23_2:
801fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
802fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
803fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
804fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
805eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixunssfdi
806fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
807*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
808fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
809*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
810fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
811fe558efeSShao-Ce SUN;
812fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_ui64:
813fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
814fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rtz
815fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
816be1cc64cSCraig Topper  %a = call float @llvm.trunc.f32(float %x)
817be1cc64cSCraig Topper  %b = fptoui float %a to i64
818be1cc64cSCraig Topper  ret i64 %b
819be1cc64cSCraig Topper}
820be1cc64cSCraig Topper
821be1cc64cSCraig Topperdefine signext i8 @test_round_si8(float %x) {
822be1cc64cSCraig Topper; RV32IF-LABEL: test_round_si8:
823be1cc64cSCraig Topper; RV32IF:       # %bb.0:
824be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
825be1cc64cSCraig Topper; RV32IF-NEXT:    ret
826be1cc64cSCraig Topper;
827be1cc64cSCraig Topper; RV64IF-LABEL: test_round_si8:
828be1cc64cSCraig Topper; RV64IF:       # %bb.0:
829be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
830be1cc64cSCraig Topper; RV64IF-NEXT:    ret
831fe558efeSShao-Ce SUN;
832fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_si8:
833fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
834fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
835fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
836fe558efeSShao-Ce SUN;
837fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_si8:
838fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
839fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
840fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
841be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
842be1cc64cSCraig Topper  %b = fptosi float %a to i8
843be1cc64cSCraig Topper  ret i8 %b
844be1cc64cSCraig Topper}
845be1cc64cSCraig Topper
846be1cc64cSCraig Topperdefine signext i16 @test_round_si16(float %x) {
847be1cc64cSCraig Topper; RV32IF-LABEL: test_round_si16:
848be1cc64cSCraig Topper; RV32IF:       # %bb.0:
849be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
850be1cc64cSCraig Topper; RV32IF-NEXT:    ret
851be1cc64cSCraig Topper;
852be1cc64cSCraig Topper; RV64IF-LABEL: test_round_si16:
853be1cc64cSCraig Topper; RV64IF:       # %bb.0:
854be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
855be1cc64cSCraig Topper; RV64IF-NEXT:    ret
856fe558efeSShao-Ce SUN;
857fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_si16:
858fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
859fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
860fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
861fe558efeSShao-Ce SUN;
862fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_si16:
863fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
864fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
865fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
866be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
867be1cc64cSCraig Topper  %b = fptosi float %a to i16
868be1cc64cSCraig Topper  ret i16 %b
869be1cc64cSCraig Topper}
870be1cc64cSCraig Topper
871be1cc64cSCraig Topperdefine signext i32 @test_round_si32(float %x) {
872be1cc64cSCraig Topper; RV32IF-LABEL: test_round_si32:
873be1cc64cSCraig Topper; RV32IF:       # %bb.0:
874be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
875be1cc64cSCraig Topper; RV32IF-NEXT:    ret
876be1cc64cSCraig Topper;
877be1cc64cSCraig Topper; RV64IF-LABEL: test_round_si32:
878be1cc64cSCraig Topper; RV64IF:       # %bb.0:
879be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
880be1cc64cSCraig Topper; RV64IF-NEXT:    ret
881fe558efeSShao-Ce SUN;
882fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_si32:
883fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
884fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
885fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
886fe558efeSShao-Ce SUN;
887fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_si32:
888fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
889fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a0, a0, rmm
890fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
891be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
892be1cc64cSCraig Topper  %b = fptosi float %a to i32
893be1cc64cSCraig Topper  ret i32 %b
894be1cc64cSCraig Topper}
895be1cc64cSCraig Topper
896be1cc64cSCraig Topperdefine i64 @test_round_si64(float %x) {
897be1cc64cSCraig Topper; RV32IF-LABEL: test_round_si64:
898be1cc64cSCraig Topper; RV32IF:       # %bb.0:
899d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
9007b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
9017b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
9027b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
903e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB27_2
904e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
905e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
9067b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
9077b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
908e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB27_2:
909d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
910d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
911d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
912d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
913eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixsfdi
914be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
915*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
916be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
917*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
918be1cc64cSCraig Topper; RV32IF-NEXT:    ret
919be1cc64cSCraig Topper;
920be1cc64cSCraig Topper; RV64IF-LABEL: test_round_si64:
921be1cc64cSCraig Topper; RV64IF:       # %bb.0:
922be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
923be1cc64cSCraig Topper; RV64IF-NEXT:    ret
924fe558efeSShao-Ce SUN;
925fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_si64:
926fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
927fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
928fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
929fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
930fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB27_2
931fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
932fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rmm
933fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rmm
934fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
935fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB27_2:
936fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
937fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
938fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
939fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
940eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixsfdi
941fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
942*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
943fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
944*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
945fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
946fe558efeSShao-Ce SUN;
947fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_si64:
948fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
949fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
950fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
951be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
952be1cc64cSCraig Topper  %b = fptosi float %a to i64
953be1cc64cSCraig Topper  ret i64 %b
954be1cc64cSCraig Topper}
955be1cc64cSCraig Topper
956be1cc64cSCraig Topperdefine zeroext i8 @test_round_ui8(float %x) {
957be1cc64cSCraig Topper; RV32IF-LABEL: test_round_ui8:
958be1cc64cSCraig Topper; RV32IF:       # %bb.0:
959be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
960be1cc64cSCraig Topper; RV32IF-NEXT:    ret
961be1cc64cSCraig Topper;
962be1cc64cSCraig Topper; RV64IF-LABEL: test_round_ui8:
963be1cc64cSCraig Topper; RV64IF:       # %bb.0:
964be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
965be1cc64cSCraig Topper; RV64IF-NEXT:    ret
966fe558efeSShao-Ce SUN;
967fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_ui8:
968fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
969fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
970fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
971fe558efeSShao-Ce SUN;
972fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_ui8:
973fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
974fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
975fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
976be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
977be1cc64cSCraig Topper  %b = fptoui float %a to i8
978be1cc64cSCraig Topper  ret i8 %b
979be1cc64cSCraig Topper}
980be1cc64cSCraig Topper
981be1cc64cSCraig Topperdefine zeroext i16 @test_round_ui16(float %x) {
982be1cc64cSCraig Topper; RV32IF-LABEL: test_round_ui16:
983be1cc64cSCraig Topper; RV32IF:       # %bb.0:
984be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
985be1cc64cSCraig Topper; RV32IF-NEXT:    ret
986be1cc64cSCraig Topper;
987be1cc64cSCraig Topper; RV64IF-LABEL: test_round_ui16:
988be1cc64cSCraig Topper; RV64IF:       # %bb.0:
989be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
990be1cc64cSCraig Topper; RV64IF-NEXT:    ret
991fe558efeSShao-Ce SUN;
992fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_ui16:
993fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
994fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
995fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
996fe558efeSShao-Ce SUN;
997fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_ui16:
998fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
999fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
1000fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1001be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
1002be1cc64cSCraig Topper  %b = fptoui float %a to i16
1003be1cc64cSCraig Topper  ret i16 %b
1004be1cc64cSCraig Topper}
1005be1cc64cSCraig Topper
1006be1cc64cSCraig Topperdefine signext i32 @test_round_ui32(float %x) {
1007be1cc64cSCraig Topper; RV32IF-LABEL: test_round_ui32:
1008be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1009be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
1010be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1011be1cc64cSCraig Topper;
1012be1cc64cSCraig Topper; RV64IF-LABEL: test_round_ui32:
1013be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1014be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
1015be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1016fe558efeSShao-Ce SUN;
1017fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_ui32:
1018fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1019fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
1020fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1021fe558efeSShao-Ce SUN;
1022fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_ui32:
1023fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1024fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.wu.s a0, a0, rmm
1025fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1026be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
1027be1cc64cSCraig Topper  %b = fptoui float %a to i32
1028be1cc64cSCraig Topper  ret i32 %b
1029be1cc64cSCraig Topper}
1030be1cc64cSCraig Topper
1031be1cc64cSCraig Topperdefine i64 @test_round_ui64(float %x) {
1032be1cc64cSCraig Topper; RV32IF-LABEL: test_round_ui64:
1033be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1034d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
10357b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
10367b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
10377b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1038e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB31_2
1039e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1040e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
10417b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
10427b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1043e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB31_2:
1044d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
1045d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
1046d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1047d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
1048eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixunssfdi
1049be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1050*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
1051be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
1052*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
1053be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1054be1cc64cSCraig Topper;
1055be1cc64cSCraig Topper; RV64IF-LABEL: test_round_ui64:
1056be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1057be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
1058be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1059fe558efeSShao-Ce SUN;
1060fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_ui64:
1061fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1062fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1063fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1064fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1065fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB31_2
1066fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1067fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rmm
1068fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rmm
1069fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1070fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB31_2:
1071fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
1072fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
1073fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1074fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
1075eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixunssfdi
1076fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1077*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
1078fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
1079*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
1080fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1081fe558efeSShao-Ce SUN;
1082fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_ui64:
1083fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1084fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rmm
1085fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1086be1cc64cSCraig Topper  %a = call float @llvm.round.f32(float %x)
1087be1cc64cSCraig Topper  %b = fptoui float %a to i64
1088be1cc64cSCraig Topper  ret i64 %b
1089be1cc64cSCraig Topper}
1090be1cc64cSCraig Topper
1091be1cc64cSCraig Topperdefine signext i8 @test_roundeven_si8(float %x) {
1092be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_si8:
1093be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1094be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
1095be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1096be1cc64cSCraig Topper;
1097be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_si8:
1098be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1099be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
1100be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1101fe558efeSShao-Ce SUN;
1102fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_si8:
1103fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1104fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rne
1105fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1106fe558efeSShao-Ce SUN;
1107fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_si8:
1108fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1109fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
1110fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1111be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1112be1cc64cSCraig Topper  %b = fptosi float %a to i8
1113be1cc64cSCraig Topper  ret i8 %b
1114be1cc64cSCraig Topper}
1115be1cc64cSCraig Topper
1116be1cc64cSCraig Topperdefine signext i16 @test_roundeven_si16(float %x) {
1117be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_si16:
1118be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1119be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
1120be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1121be1cc64cSCraig Topper;
1122be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_si16:
1123be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1124be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
1125be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1126fe558efeSShao-Ce SUN;
1127fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_si16:
1128fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1129fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rne
1130fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1131fe558efeSShao-Ce SUN;
1132fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_si16:
1133fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1134fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
1135fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1136be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1137be1cc64cSCraig Topper  %b = fptosi float %a to i16
1138be1cc64cSCraig Topper  ret i16 %b
1139be1cc64cSCraig Topper}
1140be1cc64cSCraig Topper
1141be1cc64cSCraig Topperdefine signext i32 @test_roundeven_si32(float %x) {
1142be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_si32:
1143be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1144be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
1145be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1146be1cc64cSCraig Topper;
1147be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_si32:
1148be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1149be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
1150be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1151fe558efeSShao-Ce SUN;
1152fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_si32:
1153fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1154fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a0, a0, rne
1155fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1156fe558efeSShao-Ce SUN;
1157fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_si32:
1158fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1159fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a0, a0, rne
1160fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1161be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1162be1cc64cSCraig Topper  %b = fptosi float %a to i32
1163be1cc64cSCraig Topper  ret i32 %b
1164be1cc64cSCraig Topper}
1165be1cc64cSCraig Topper
1166be1cc64cSCraig Topperdefine i64 @test_roundeven_si64(float %x) {
1167be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_si64:
1168be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1169d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
11707b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
11717b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
11727b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1173e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB35_2
1174e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1175e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
11767b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
11777b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1178e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB35_2:
1179d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
1180d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
1181d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1182d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
1183eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixsfdi
1184be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1185*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
1186be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
1187*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
1188be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1189be1cc64cSCraig Topper;
1190be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_si64:
1191be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1192be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
1193be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1194fe558efeSShao-Ce SUN;
1195fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_si64:
1196fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1197fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1198fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1199fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1200fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB35_2
1201fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1202fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rne
1203fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rne
1204fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1205fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB35_2:
1206fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
1207fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
1208fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1209fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
1210eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixsfdi
1211fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1212*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
1213fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
1214*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
1215fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1216fe558efeSShao-Ce SUN;
1217fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_si64:
1218fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1219fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rne
1220fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1221be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1222be1cc64cSCraig Topper  %b = fptosi float %a to i64
1223be1cc64cSCraig Topper  ret i64 %b
1224be1cc64cSCraig Topper}
1225be1cc64cSCraig Topper
1226be1cc64cSCraig Topperdefine zeroext i8 @test_roundeven_ui8(float %x) {
1227be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_ui8:
1228be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1229be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
1230be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1231be1cc64cSCraig Topper;
1232be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_ui8:
1233be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1234be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
1235be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1236fe558efeSShao-Ce SUN;
1237fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_ui8:
1238fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1239fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
1240fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1241fe558efeSShao-Ce SUN;
1242fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_ui8:
1243fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1244fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
1245fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1246be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1247be1cc64cSCraig Topper  %b = fptoui float %a to i8
1248be1cc64cSCraig Topper  ret i8 %b
1249be1cc64cSCraig Topper}
1250be1cc64cSCraig Topper
1251be1cc64cSCraig Topperdefine zeroext i16 @test_roundeven_ui16(float %x) {
1252be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_ui16:
1253be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1254be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
1255be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1256be1cc64cSCraig Topper;
1257be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_ui16:
1258be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1259be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
1260be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1261fe558efeSShao-Ce SUN;
1262fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_ui16:
1263fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1264fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
1265fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1266fe558efeSShao-Ce SUN;
1267fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_ui16:
1268fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1269fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
1270fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1271be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1272be1cc64cSCraig Topper  %b = fptoui float %a to i16
1273be1cc64cSCraig Topper  ret i16 %b
1274be1cc64cSCraig Topper}
1275be1cc64cSCraig Topper
1276be1cc64cSCraig Topperdefine signext i32 @test_roundeven_ui32(float %x) {
1277be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_ui32:
1278be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1279be1cc64cSCraig Topper; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
1280be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1281be1cc64cSCraig Topper;
1282be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_ui32:
1283be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1284be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
1285be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1286fe558efeSShao-Ce SUN;
1287fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_ui32:
1288fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1289fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
1290fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1291fe558efeSShao-Ce SUN;
1292fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_ui32:
1293fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1294fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.wu.s a0, a0, rne
1295fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1296be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1297be1cc64cSCraig Topper  %b = fptoui float %a to i32
1298be1cc64cSCraig Topper  ret i32 %b
1299be1cc64cSCraig Topper}
1300be1cc64cSCraig Topper
1301be1cc64cSCraig Topperdefine i64 @test_roundeven_ui64(float %x) {
1302be1cc64cSCraig Topper; RV32IF-LABEL: test_roundeven_ui64:
1303be1cc64cSCraig Topper; RV32IF:       # %bb.0:
1304d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
13057b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
13067b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
13077b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1308e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB39_2
1309e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1310e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
13117b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
13127b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1313e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB39_2:
1314d02b9869SHan-Kuan Chen; RV32IF-NEXT:    addi sp, sp, -16
1315d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_def_cfa_offset 16
1316d02b9869SHan-Kuan Chen; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1317d02b9869SHan-Kuan Chen; RV32IF-NEXT:    .cfi_offset ra, -4
1318eabaee0cSFangrui Song; RV32IF-NEXT:    call __fixunssfdi
1319be1cc64cSCraig Topper; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1320*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_restore ra
1321be1cc64cSCraig Topper; RV32IF-NEXT:    addi sp, sp, 16
1322*97982a8cSdlav-sc; RV32IF-NEXT:    .cfi_def_cfa_offset 0
1323be1cc64cSCraig Topper; RV32IF-NEXT:    ret
1324be1cc64cSCraig Topper;
1325be1cc64cSCraig Topper; RV64IF-LABEL: test_roundeven_ui64:
1326be1cc64cSCraig Topper; RV64IF:       # %bb.0:
1327be1cc64cSCraig Topper; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
1328be1cc64cSCraig Topper; RV64IF-NEXT:    ret
1329fe558efeSShao-Ce SUN;
1330fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_ui64:
1331fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1332fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1333fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1334fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1335fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB39_2
1336fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1337fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rne
1338fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rne
1339fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1340fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB39_2:
1341fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, -16
1342fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 16
1343fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1344fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    .cfi_offset ra, -4
1345eabaee0cSFangrui Song; RV32IZFINX-NEXT:    call __fixunssfdi
1346fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1347*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_restore ra
1348fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    addi sp, sp, 16
1349*97982a8cSdlav-sc; RV32IZFINX-NEXT:    .cfi_def_cfa_offset 0
1350fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1351fe558efeSShao-Ce SUN;
1352fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_ui64:
1353fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1354fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.lu.s a0, a0, rne
1355fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
1356be1cc64cSCraig Topper  %a = call float @llvm.roundeven.f32(float %x)
1357be1cc64cSCraig Topper  %b = fptoui float %a to i64
1358be1cc64cSCraig Topper  ret i64 %b
1359be1cc64cSCraig Topper}
1360be1cc64cSCraig Topper
136175b15a7eSPhilip Reamesdefine float @test_floor_float(float %x) {
136275b15a7eSPhilip Reames; RV32IFD-LABEL: test_floor_float:
136375b15a7eSPhilip Reames; RV32IFD:       # %bb.0:
136475b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, -16
136575b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
136675b15a7eSPhilip Reames; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
136775b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_offset ra, -4
136875b15a7eSPhilip Reames; RV32IFD-NEXT:    call floor@plt
136975b15a7eSPhilip Reames; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
137075b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, 16
137175b15a7eSPhilip Reames; RV32IFD-NEXT:    ret
137275b15a7eSPhilip Reames;
137375b15a7eSPhilip Reames; RV64IFD-LABEL: test_floor_float:
137475b15a7eSPhilip Reames; RV64IFD:       # %bb.0:
137575b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, -16
137675b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_def_cfa_offset 16
137775b15a7eSPhilip Reames; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
137875b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_offset ra, -8
137975b15a7eSPhilip Reames; RV64IFD-NEXT:    call floor@plt
138075b15a7eSPhilip Reames; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
138175b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, 16
138275b15a7eSPhilip Reames; RV64IFD-NEXT:    ret
138375b15a7eSPhilip Reames; RV32IF-LABEL: test_floor_float:
138475b15a7eSPhilip Reames; RV32IF:       # %bb.0:
1385d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
13867b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
13877b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
13887b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1389e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB40_2
1390e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1391e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
13927b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
13937b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1394e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB40_2:
1395e94dc58dSCraig Topper; RV32IF-NEXT:    ret
139675b15a7eSPhilip Reames;
139775b15a7eSPhilip Reames; RV64IF-LABEL: test_floor_float:
139875b15a7eSPhilip Reames; RV64IF:       # %bb.0:
1399d02b9869SHan-Kuan Chen; RV64IF-NEXT:    lui a0, 307200
14007b0c4184SCraig Topper; RV64IF-NEXT:    fmv.w.x fa5, a0
14017b0c4184SCraig Topper; RV64IF-NEXT:    fabs.s fa4, fa0
14027b0c4184SCraig Topper; RV64IF-NEXT:    flt.s a0, fa4, fa5
1403e94dc58dSCraig Topper; RV64IF-NEXT:    beqz a0, .LBB40_2
1404e94dc58dSCraig Topper; RV64IF-NEXT:  # %bb.1:
1405e94dc58dSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
14067b0c4184SCraig Topper; RV64IF-NEXT:    fcvt.s.w fa5, a0, rdn
14077b0c4184SCraig Topper; RV64IF-NEXT:    fsgnj.s fa0, fa5, fa0
1408e94dc58dSCraig Topper; RV64IF-NEXT:  .LBB40_2:
1409e94dc58dSCraig Topper; RV64IF-NEXT:    ret
1410fe558efeSShao-Ce SUN;
1411fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_floor_float:
1412fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1413fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1414fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1415fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1416fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB40_2
1417fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1418fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rdn
1419fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rdn
1420fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1421fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB40_2:
1422fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1423fe558efeSShao-Ce SUN;
1424fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_floor_float:
1425fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1426fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    lui a1, 307200
1427fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fabs.s a2, a0
1428fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    flt.s a1, a2, a1
1429fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    beqz a1, .LBB40_2
1430fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  # %bb.1:
1431fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a1, a0, rdn
1432fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.s.w a1, a1, rdn
1433fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fsgnj.s a0, a1, a0
1434fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  .LBB40_2:
1435fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
143675b15a7eSPhilip Reames  %a = call float @llvm.floor.f32(float %x)
143775b15a7eSPhilip Reames  ret float %a
143875b15a7eSPhilip Reames}
143975b15a7eSPhilip Reames
144075b15a7eSPhilip Reamesdefine float @test_ceil_float(float %x) {
144175b15a7eSPhilip Reames; RV32IFD-LABEL: test_ceil_float:
144275b15a7eSPhilip Reames; RV32IFD:       # %bb.0:
144375b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, -16
144475b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
144575b15a7eSPhilip Reames; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
144675b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_offset ra, -4
144775b15a7eSPhilip Reames; RV32IFD-NEXT:    call ceil@plt
144875b15a7eSPhilip Reames; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
144975b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, 16
145075b15a7eSPhilip Reames; RV32IFD-NEXT:    ret
145175b15a7eSPhilip Reames;
145275b15a7eSPhilip Reames; RV64IFD-LABEL: test_ceil_float:
145375b15a7eSPhilip Reames; RV64IFD:       # %bb.0:
145475b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, -16
145575b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_def_cfa_offset 16
145675b15a7eSPhilip Reames; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
145775b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_offset ra, -8
145875b15a7eSPhilip Reames; RV64IFD-NEXT:    call ceil@plt
145975b15a7eSPhilip Reames; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
146075b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, 16
146175b15a7eSPhilip Reames; RV64IFD-NEXT:    ret
146275b15a7eSPhilip Reames; RV32IF-LABEL: test_ceil_float:
146375b15a7eSPhilip Reames; RV32IF:       # %bb.0:
1464d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
14657b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
14667b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
14677b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1468e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB41_2
1469e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1470e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
14717b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
14727b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1473e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB41_2:
1474e94dc58dSCraig Topper; RV32IF-NEXT:    ret
147575b15a7eSPhilip Reames;
147675b15a7eSPhilip Reames; RV64IF-LABEL: test_ceil_float:
147775b15a7eSPhilip Reames; RV64IF:       # %bb.0:
1478d02b9869SHan-Kuan Chen; RV64IF-NEXT:    lui a0, 307200
14797b0c4184SCraig Topper; RV64IF-NEXT:    fmv.w.x fa5, a0
14807b0c4184SCraig Topper; RV64IF-NEXT:    fabs.s fa4, fa0
14817b0c4184SCraig Topper; RV64IF-NEXT:    flt.s a0, fa4, fa5
1482e94dc58dSCraig Topper; RV64IF-NEXT:    beqz a0, .LBB41_2
1483e94dc58dSCraig Topper; RV64IF-NEXT:  # %bb.1:
1484e94dc58dSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
14857b0c4184SCraig Topper; RV64IF-NEXT:    fcvt.s.w fa5, a0, rup
14867b0c4184SCraig Topper; RV64IF-NEXT:    fsgnj.s fa0, fa5, fa0
1487e94dc58dSCraig Topper; RV64IF-NEXT:  .LBB41_2:
1488e94dc58dSCraig Topper; RV64IF-NEXT:    ret
1489fe558efeSShao-Ce SUN;
1490fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_ceil_float:
1491fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1492fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1493fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1494fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1495fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB41_2
1496fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1497fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rup
1498fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rup
1499fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1500fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB41_2:
1501fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1502fe558efeSShao-Ce SUN;
1503fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_ceil_float:
1504fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1505fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    lui a1, 307200
1506fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fabs.s a2, a0
1507fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    flt.s a1, a2, a1
1508fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    beqz a1, .LBB41_2
1509fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  # %bb.1:
1510fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a1, a0, rup
1511fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.s.w a1, a1, rup
1512fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fsgnj.s a0, a1, a0
1513fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  .LBB41_2:
1514fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
151575b15a7eSPhilip Reames  %a = call float @llvm.ceil.f32(float %x)
151675b15a7eSPhilip Reames  ret float %a
151775b15a7eSPhilip Reames}
151875b15a7eSPhilip Reames
151975b15a7eSPhilip Reamesdefine float @test_trunc_float(float %x) {
152075b15a7eSPhilip Reames; RV32IFD-LABEL: test_trunc_float:
152175b15a7eSPhilip Reames; RV32IFD:       # %bb.0:
152275b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, -16
152375b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
152475b15a7eSPhilip Reames; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
152575b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_offset ra, -4
152675b15a7eSPhilip Reames; RV32IFD-NEXT:    call trunc@plt
152775b15a7eSPhilip Reames; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
152875b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, 16
152975b15a7eSPhilip Reames; RV32IFD-NEXT:    ret
153075b15a7eSPhilip Reames;
153175b15a7eSPhilip Reames; RV64IFD-LABEL: test_trunc_float:
153275b15a7eSPhilip Reames; RV64IFD:       # %bb.0:
153375b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, -16
153475b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_def_cfa_offset 16
153575b15a7eSPhilip Reames; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
153675b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_offset ra, -8
153775b15a7eSPhilip Reames; RV64IFD-NEXT:    call trunc@plt
153875b15a7eSPhilip Reames; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
153975b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, 16
154075b15a7eSPhilip Reames; RV64IFD-NEXT:    ret
154175b15a7eSPhilip Reames; RV32IF-LABEL: test_trunc_float:
154275b15a7eSPhilip Reames; RV32IF:       # %bb.0:
1543d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
15447b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
15457b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
15467b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1547e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB42_2
1548e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1549e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
15507b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
15517b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1552e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB42_2:
1553e94dc58dSCraig Topper; RV32IF-NEXT:    ret
155475b15a7eSPhilip Reames;
155575b15a7eSPhilip Reames; RV64IF-LABEL: test_trunc_float:
155675b15a7eSPhilip Reames; RV64IF:       # %bb.0:
1557d02b9869SHan-Kuan Chen; RV64IF-NEXT:    lui a0, 307200
15587b0c4184SCraig Topper; RV64IF-NEXT:    fmv.w.x fa5, a0
15597b0c4184SCraig Topper; RV64IF-NEXT:    fabs.s fa4, fa0
15607b0c4184SCraig Topper; RV64IF-NEXT:    flt.s a0, fa4, fa5
1561e94dc58dSCraig Topper; RV64IF-NEXT:    beqz a0, .LBB42_2
1562e94dc58dSCraig Topper; RV64IF-NEXT:  # %bb.1:
1563e94dc58dSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
15647b0c4184SCraig Topper; RV64IF-NEXT:    fcvt.s.w fa5, a0, rtz
15657b0c4184SCraig Topper; RV64IF-NEXT:    fsgnj.s fa0, fa5, fa0
1566e94dc58dSCraig Topper; RV64IF-NEXT:  .LBB42_2:
1567e94dc58dSCraig Topper; RV64IF-NEXT:    ret
1568fe558efeSShao-Ce SUN;
1569fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_trunc_float:
1570fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1571fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1572fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1573fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1574fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB42_2
1575fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1576fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rtz
1577fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rtz
1578fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1579fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB42_2:
1580fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1581fe558efeSShao-Ce SUN;
1582fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_trunc_float:
1583fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1584fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    lui a1, 307200
1585fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fabs.s a2, a0
1586fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    flt.s a1, a2, a1
1587fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    beqz a1, .LBB42_2
1588fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  # %bb.1:
1589fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a1, a0, rtz
1590fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.s.w a1, a1, rtz
1591fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fsgnj.s a0, a1, a0
1592fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  .LBB42_2:
1593fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
159475b15a7eSPhilip Reames  %a = call float @llvm.trunc.f32(float %x)
159575b15a7eSPhilip Reames  ret float %a
159675b15a7eSPhilip Reames}
159775b15a7eSPhilip Reames
159875b15a7eSPhilip Reamesdefine float @test_round_float(float %x) {
159975b15a7eSPhilip Reames; RV32IFD-LABEL: test_round_float:
160075b15a7eSPhilip Reames; RV32IFD:       # %bb.0:
160175b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, -16
160275b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
160375b15a7eSPhilip Reames; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
160475b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_offset ra, -4
160575b15a7eSPhilip Reames; RV32IFD-NEXT:    call round@plt
160675b15a7eSPhilip Reames; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
160775b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, 16
160875b15a7eSPhilip Reames; RV32IFD-NEXT:    ret
160975b15a7eSPhilip Reames;
161075b15a7eSPhilip Reames; RV64IFD-LABEL: test_round_float:
161175b15a7eSPhilip Reames; RV64IFD:       # %bb.0:
161275b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, -16
161375b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_def_cfa_offset 16
161475b15a7eSPhilip Reames; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
161575b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_offset ra, -8
161675b15a7eSPhilip Reames; RV64IFD-NEXT:    call round@plt
161775b15a7eSPhilip Reames; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
161875b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, 16
161975b15a7eSPhilip Reames; RV64IFD-NEXT:    ret
162075b15a7eSPhilip Reames; RV32IF-LABEL: test_round_float:
162175b15a7eSPhilip Reames; RV32IF:       # %bb.0:
1622d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
16237b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
16247b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
16257b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1626e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB43_2
1627e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1628e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
16297b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
16307b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1631e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB43_2:
1632e94dc58dSCraig Topper; RV32IF-NEXT:    ret
163375b15a7eSPhilip Reames;
163475b15a7eSPhilip Reames; RV64IF-LABEL: test_round_float:
163575b15a7eSPhilip Reames; RV64IF:       # %bb.0:
1636d02b9869SHan-Kuan Chen; RV64IF-NEXT:    lui a0, 307200
16377b0c4184SCraig Topper; RV64IF-NEXT:    fmv.w.x fa5, a0
16387b0c4184SCraig Topper; RV64IF-NEXT:    fabs.s fa4, fa0
16397b0c4184SCraig Topper; RV64IF-NEXT:    flt.s a0, fa4, fa5
1640e94dc58dSCraig Topper; RV64IF-NEXT:    beqz a0, .LBB43_2
1641e94dc58dSCraig Topper; RV64IF-NEXT:  # %bb.1:
1642e94dc58dSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
16437b0c4184SCraig Topper; RV64IF-NEXT:    fcvt.s.w fa5, a0, rmm
16447b0c4184SCraig Topper; RV64IF-NEXT:    fsgnj.s fa0, fa5, fa0
1645e94dc58dSCraig Topper; RV64IF-NEXT:  .LBB43_2:
1646e94dc58dSCraig Topper; RV64IF-NEXT:    ret
1647fe558efeSShao-Ce SUN;
1648fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_round_float:
1649fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1650fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1651fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1652fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1653fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB43_2
1654fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1655fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rmm
1656fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rmm
1657fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1658fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB43_2:
1659fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1660fe558efeSShao-Ce SUN;
1661fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_round_float:
1662fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1663fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    lui a1, 307200
1664fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fabs.s a2, a0
1665fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    flt.s a1, a2, a1
1666fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    beqz a1, .LBB43_2
1667fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  # %bb.1:
1668fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a1, a0, rmm
1669fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.s.w a1, a1, rmm
1670fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fsgnj.s a0, a1, a0
1671fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  .LBB43_2:
1672fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
167375b15a7eSPhilip Reames  %a = call float @llvm.round.f32(float %x)
167475b15a7eSPhilip Reames  ret float %a
167575b15a7eSPhilip Reames}
167675b15a7eSPhilip Reames
167775b15a7eSPhilip Reamesdefine float @test_roundeven_float(float %x) {
167875b15a7eSPhilip Reames; RV32IFD-LABEL: test_roundeven_float:
167975b15a7eSPhilip Reames; RV32IFD:       # %bb.0:
168075b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, -16
168175b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
168275b15a7eSPhilip Reames; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
168375b15a7eSPhilip Reames; RV32IFD-NEXT:    .cfi_offset ra, -4
168475b15a7eSPhilip Reames; RV32IFD-NEXT:    call roundeven@plt
168575b15a7eSPhilip Reames; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
168675b15a7eSPhilip Reames; RV32IFD-NEXT:    addi sp, sp, 16
168775b15a7eSPhilip Reames; RV32IFD-NEXT:    ret
168875b15a7eSPhilip Reames;
168975b15a7eSPhilip Reames; RV64IFD-LABEL: test_roundeven_float:
169075b15a7eSPhilip Reames; RV64IFD:       # %bb.0:
169175b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, -16
169275b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_def_cfa_offset 16
169375b15a7eSPhilip Reames; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
169475b15a7eSPhilip Reames; RV64IFD-NEXT:    .cfi_offset ra, -8
169575b15a7eSPhilip Reames; RV64IFD-NEXT:    call roundeven@plt
169675b15a7eSPhilip Reames; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
169775b15a7eSPhilip Reames; RV64IFD-NEXT:    addi sp, sp, 16
169875b15a7eSPhilip Reames; RV64IFD-NEXT:    ret
169975b15a7eSPhilip Reames; RV32IF-LABEL: test_roundeven_float:
170075b15a7eSPhilip Reames; RV32IF:       # %bb.0:
1701d02b9869SHan-Kuan Chen; RV32IF-NEXT:    lui a0, 307200
17027b0c4184SCraig Topper; RV32IF-NEXT:    fmv.w.x fa5, a0
17037b0c4184SCraig Topper; RV32IF-NEXT:    fabs.s fa4, fa0
17047b0c4184SCraig Topper; RV32IF-NEXT:    flt.s a0, fa4, fa5
1705e94dc58dSCraig Topper; RV32IF-NEXT:    beqz a0, .LBB44_2
1706e94dc58dSCraig Topper; RV32IF-NEXT:  # %bb.1:
1707e94dc58dSCraig Topper; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
17087b0c4184SCraig Topper; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
17097b0c4184SCraig Topper; RV32IF-NEXT:    fsgnj.s fa0, fa5, fa0
1710e94dc58dSCraig Topper; RV32IF-NEXT:  .LBB44_2:
1711e94dc58dSCraig Topper; RV32IF-NEXT:    ret
171275b15a7eSPhilip Reames;
171375b15a7eSPhilip Reames; RV64IF-LABEL: test_roundeven_float:
171475b15a7eSPhilip Reames; RV64IF:       # %bb.0:
1715d02b9869SHan-Kuan Chen; RV64IF-NEXT:    lui a0, 307200
17167b0c4184SCraig Topper; RV64IF-NEXT:    fmv.w.x fa5, a0
17177b0c4184SCraig Topper; RV64IF-NEXT:    fabs.s fa4, fa0
17187b0c4184SCraig Topper; RV64IF-NEXT:    flt.s a0, fa4, fa5
1719e94dc58dSCraig Topper; RV64IF-NEXT:    beqz a0, .LBB44_2
1720e94dc58dSCraig Topper; RV64IF-NEXT:  # %bb.1:
1721e94dc58dSCraig Topper; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
17227b0c4184SCraig Topper; RV64IF-NEXT:    fcvt.s.w fa5, a0, rne
17237b0c4184SCraig Topper; RV64IF-NEXT:    fsgnj.s fa0, fa5, fa0
1724e94dc58dSCraig Topper; RV64IF-NEXT:  .LBB44_2:
1725e94dc58dSCraig Topper; RV64IF-NEXT:    ret
1726fe558efeSShao-Ce SUN;
1727fe558efeSShao-Ce SUN; RV32IZFINX-LABEL: test_roundeven_float:
1728fe558efeSShao-Ce SUN; RV32IZFINX:       # %bb.0:
1729fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    lui a1, 307200
1730fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fabs.s a2, a0
1731fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    flt.s a1, a2, a1
1732fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    beqz a1, .LBB44_2
1733fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  # %bb.1:
1734fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.w.s a1, a0, rne
1735fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fcvt.s.w a1, a1, rne
1736fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    fsgnj.s a0, a1, a0
1737fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:  .LBB44_2:
1738fe558efeSShao-Ce SUN; RV32IZFINX-NEXT:    ret
1739fe558efeSShao-Ce SUN;
1740fe558efeSShao-Ce SUN; RV64IZFINX-LABEL: test_roundeven_float:
1741fe558efeSShao-Ce SUN; RV64IZFINX:       # %bb.0:
1742fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    lui a1, 307200
1743fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fabs.s a2, a0
1744fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    flt.s a1, a2, a1
1745fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    beqz a1, .LBB44_2
1746fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  # %bb.1:
1747fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.w.s a1, a0, rne
1748fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fcvt.s.w a1, a1, rne
1749fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    fsgnj.s a0, a1, a0
1750fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:  .LBB44_2:
1751fe558efeSShao-Ce SUN; RV64IZFINX-NEXT:    ret
175275b15a7eSPhilip Reames  %a = call float @llvm.roundeven.f32(float %x)
175375b15a7eSPhilip Reames  ret float %a
175475b15a7eSPhilip Reames}
175575b15a7eSPhilip Reames
1756be1cc64cSCraig Topperdeclare float @llvm.floor.f32(float)
1757be1cc64cSCraig Topperdeclare float @llvm.ceil.f32(float)
1758be1cc64cSCraig Topperdeclare float @llvm.trunc.f32(float)
1759be1cc64cSCraig Topperdeclare float @llvm.round.f32(float)
1760be1cc64cSCraig Topperdeclare float @llvm.roundeven.f32(float)
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