10d47c7abSLuís Marques; REQUIRES: asserts 20d47c7abSLuís Marques; RUN: llc -mtriple=riscv32 -debug-only=machine-scheduler < %s \ 30d47c7abSLuís Marques; RUN: -o /dev/null 2>&1 | FileCheck %s 40d47c7abSLuís Marques; RUN: llc -mtriple=riscv64 -debug-only=machine-scheduler < %s \ 50d47c7abSLuís Marques; RUN: -o /dev/null 2>&1 | FileCheck %s 60d47c7abSLuís Marques 70d47c7abSLuís Marques; This test exercises the areMemAccessesTriviallyDisjoint hook. 80d47c7abSLuís Marques; Test that the two stores are disjoint memory accesses. If the corresponding 90d47c7abSLuís Marques; store machine instructions don't depend on each other, the second store should 100d47c7abSLuís Marques; not appear in the successors list of the first one and the first one should 110d47c7abSLuís Marques; not appear on the predecessors list of the second one. 12*1456b686SNikita Popovdefine i32 @test_disjoint(ptr %P, i32 %v) { 130d47c7abSLuís Marquesentry: 140d47c7abSLuís Marques; CHECK: ********** MI Scheduling ********** 150d47c7abSLuís Marques; CHECK-LABEL: test_disjoint:%bb.0 16fae05692SMatt Arsenault; CHECK:SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx) 170d47c7abSLuís Marques; CHECK-NOT: Successors: 18fae05692SMatt Arsenault; CHECK:SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1) 190d47c7abSLuís Marques; CHECK: Predecessors: 200d47c7abSLuís Marques; CHECK-NOT: SU(2): Ord Latency=0 Memory 21*1456b686SNikita Popov %arrayidx = getelementptr inbounds i32, ptr %P, i32 3 22*1456b686SNikita Popov store i32 %v, ptr %arrayidx 23*1456b686SNikita Popov %arrayidx1 = getelementptr inbounds i32, ptr %P, i32 2 24*1456b686SNikita Popov store i32 %v, ptr %arrayidx1 250d47c7abSLuís Marques ret i32 %v 260d47c7abSLuís Marques} 27