xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll (revision dde5546b79f784ab71cac325e0a0698c67c4dcde)
18677aaa1SCraig Topper; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
28677aaa1SCraig Topper; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs -O0 < %s \
38677aaa1SCraig Topper; RUN:   | FileCheck %s --check-prefixes=RV32,RV32-O0
48677aaa1SCraig Topper; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs -O0 < %s \
58677aaa1SCraig Topper; RUN:   | FileCheck %s --check-prefixes=RV64,RV64-O0
68677aaa1SCraig Topper; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
78677aaa1SCraig Topper; RUN:   | FileCheck %s --check-prefixes=RV32,RV32-OPT
88677aaa1SCraig Topper; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
98677aaa1SCraig Topper; RUN:   | FileCheck %s --check-prefixes=RV64,RV64-OPT
108677aaa1SCraig Topper
118677aaa1SCraig Topperdefine i32 @constant_to_rhs(i32 %x) {
128677aaa1SCraig Topper; RV32-O0-LABEL: constant_to_rhs:
138677aaa1SCraig Topper; RV32-O0:       # %bb.0:
148677aaa1SCraig Topper; RV32-O0-NEXT:    mv a1, a0
158677aaa1SCraig Topper; RV32-O0-NEXT:    li a0, 1
168677aaa1SCraig Topper; RV32-O0-NEXT:    add a0, a0, a1
178677aaa1SCraig Topper; RV32-O0-NEXT:    ret
188677aaa1SCraig Topper;
198677aaa1SCraig Topper; RV64-O0-LABEL: constant_to_rhs:
208677aaa1SCraig Topper; RV64-O0:       # %bb.0:
218677aaa1SCraig Topper; RV64-O0-NEXT:    mv a1, a0
228677aaa1SCraig Topper; RV64-O0-NEXT:    li a0, 1
23c280522fSCraig Topper; RV64-O0-NEXT:    add a0, a0, a1
24*dde5546bSLuke Quinn; RV64-O0-NEXT:    sext.w a0, a0
258677aaa1SCraig Topper; RV64-O0-NEXT:    ret
268677aaa1SCraig Topper;
278677aaa1SCraig Topper; RV32-OPT-LABEL: constant_to_rhs:
288677aaa1SCraig Topper; RV32-OPT:       # %bb.0:
298677aaa1SCraig Topper; RV32-OPT-NEXT:    addi a0, a0, 1
308677aaa1SCraig Topper; RV32-OPT-NEXT:    ret
318677aaa1SCraig Topper;
328677aaa1SCraig Topper; RV64-OPT-LABEL: constant_to_rhs:
338677aaa1SCraig Topper; RV64-OPT:       # %bb.0:
34*dde5546bSLuke Quinn; RV64-OPT-NEXT:    addiw a0, a0, 1
358677aaa1SCraig Topper; RV64-OPT-NEXT:    ret
368677aaa1SCraig Topper  %a = add i32 1, %x
378677aaa1SCraig Topper  ret i32 %a
388677aaa1SCraig Topper}
398677aaa1SCraig Topper
408677aaa1SCraig Topperdefine i32 @mul_to_shift(i32 %x) {
418677aaa1SCraig Topper; RV32-LABEL: mul_to_shift:
428677aaa1SCraig Topper; RV32:       # %bb.0:
438677aaa1SCraig Topper; RV32-NEXT:    slli a0, a0, 2
448677aaa1SCraig Topper; RV32-NEXT:    ret
458677aaa1SCraig Topper;
466a857fe8SCraig Topper; RV64-LABEL: mul_to_shift:
476a857fe8SCraig Topper; RV64:       # %bb.0:
486a857fe8SCraig Topper; RV64-NEXT:    slli a0, a0, 2
496a857fe8SCraig Topper; RV64-NEXT:    ret
508677aaa1SCraig Topper  %a = mul i32 %x, 4
518677aaa1SCraig Topper  ret i32 %a
528677aaa1SCraig Topper}
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