1d7e0ea20SChen Zheng; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2d7e0ea20SChen Zheng; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3d7e0ea20SChen Zheng; RUN: -stop-after=finalize-isel -verify-machineinstrs < %s | \ 4d7e0ea20SChen Zheng; RUN: FileCheck %s 5d7e0ea20SChen Zheng 6d7e0ea20SChen Zhengdefine <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { 7d7e0ea20SChen Zheng ; CHECK-LABEL: name: foo 8d7e0ea20SChen Zheng ; CHECK: bb.0 (%ir-block.0): 9d7e0ea20SChen Zheng ; CHECK-NEXT: liveins: $x3, $x4, $x5 10d7e0ea20SChen Zheng ; CHECK-NEXT: {{ $}} 11d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x5 12d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x4 13d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3 14d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32 15d7e0ea20SChen Zheng ; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]] 16d7e0ea20SChen Zheng ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ]], %subreg.sub_64 17d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32 18d7e0ea20SChen Zheng ; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]] 19d7e0ea20SChen Zheng ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ1]], %subreg.sub_64 20d7e0ea20SChen Zheng ; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]] 21d7e0ea20SChen Zheng ; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got) 22d7e0ea20SChen Zheng ; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool) 23d7e0ea20SChen Zheng ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 24d7e0ea20SChen Zheng ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] 25d7e0ea20SChen Zheng ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 26d7e0ea20SChen Zheng ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] 27*053750c3SChen Zheng ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8 28d7e0ea20SChen Zheng ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] 29d7e0ea20SChen Zheng ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2 30d7e0ea20SChen Zheng %1 = insertelement <4 x i1> poison, i1 %c1, i64 0 31d7e0ea20SChen Zheng %2 = insertelement <4 x i1> %1, i1 %c2, i64 1 32d7e0ea20SChen Zheng %3 = insertelement <4 x i1> %2, i1 %c3, i64 3 33d7e0ea20SChen Zheng %4 = shufflevector <4 x i1> %3, <4 x i1> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3> 34d7e0ea20SChen Zheng ret <4 x i1> %4 35d7e0ea20SChen Zheng} 36