xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll (revision 0cfa7b7ad035cd349be419b8601748bfcb1edf1b) 
1; Test the vector rotate and shift doubleword instructions that were added in P8
2; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
3; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
4
5declare <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64>, <2 x i64>) nounwind readnone
6declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone
7declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
8declare <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64>, <2 x i64>) nounwind readnone
9
10define <2 x i64> @test_vrld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
11       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64> %x, <2 x i64> %y)
12       ret <2 x i64> %tmp
13; CHECK: vrld 2, 2, 3
14}
15
16define <2 x i64> @test_vsld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
17       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64> %x, <2 x i64> %y)
18       ret <2 x i64> %tmp
19; CHECK: vsld 2, 2, 3
20}
21
22define <2 x i64> @test_vsrd(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
23       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64> %x, <2 x i64> %y)
24       ret <2 x i64> %tmp
25; CHECK: vsrd 2, 2, 3
26}
27
28define <2 x i64> @test_vsrad(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
29       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64> %x, <2 x i64> %y)
30       ret <2 x i64> %tmp
31; CHECK: vsrad 2, 2, 3
32}
33
34