1*a4751804SRolandF77; RUN: llc -mcpu=pwr10 -mtriple=powerpc64-ibm-aix -ppc-asm-full-reg-names \ 2*a4751804SRolandF77; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 3*a4751804SRolandF77; RUN: llc -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \ 4*a4751804SRolandF77; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s 5*a4751804SRolandF77; RUN: llc -mcpu=pwr10 -mtriple=powerpc-ibm-aix -ppc-asm-full-reg-names \ 6*a4751804SRolandF77; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 7*a4751804SRolandF77 8*a4751804SRolandF77define signext i32 @cmpgtw(<4 x i32> noundef %a, <4 x i32> noundef %b) local_unnamed_addr { 9*a4751804SRolandF77; CHECK: vcmpgtsw. v2, v2, v3 10*a4751804SRolandF77; CHECK: setbc r3, 4*cr6+lt 11*a4751804SRolandF77entry: 12*a4751804SRolandF77 %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b) 13*a4751804SRolandF77 ret i32 %0 14*a4751804SRolandF77} 15*a4751804SRolandF77 16*a4751804SRolandF77define signext i32 @cmpanynew(<4 x i32> noundef %a, <4 x i32> noundef %b) local_unnamed_addr { 17*a4751804SRolandF77; CHECK: vcmpequw. v2, v2, v3 18*a4751804SRolandF77; CHECK: setbcr r3, 4*cr6+lt 19*a4751804SRolandF77entry: 20*a4751804SRolandF77 %0 = tail call i32 @llvm.ppc.altivec.vcmpequw.p(i32 3, <4 x i32> %a, <4 x i32> %b) 21*a4751804SRolandF77 ret i32 %0 22*a4751804SRolandF77} 23*a4751804SRolandF77 24*a4751804SRolandF77define signext i32 @cmpallneh(<8 x i16> noundef %a, <8 x i16> noundef %b) local_unnamed_addr { 25*a4751804SRolandF77; CHECK: vcmpequh. v2, v2, v3 26*a4751804SRolandF77; CHECK: setbc r3, 4*cr6+eq 27*a4751804SRolandF77entry: 28*a4751804SRolandF77 %0 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 0, <8 x i16> %a, <8 x i16> %b) 29*a4751804SRolandF77 ret i32 %0 30*a4751804SRolandF77} 31*a4751804SRolandF77 32*a4751804SRolandF77define signext i32 @cmpeqb(<16 x i8> noundef %a, <16 x i8> noundef %b) local_unnamed_addr { 33*a4751804SRolandF77; CHECK: vcmpequb. v2, v2, v3 34*a4751804SRolandF77; CHECK: setbcr r3, 4*cr6+eq 35*a4751804SRolandF77entry: 36*a4751804SRolandF77 %0 = tail call i32 @llvm.ppc.altivec.vcmpequb.p(i32 1, <16 x i8> %a, <16 x i8> %b) 37*a4751804SRolandF77 ret i32 %0 38*a4751804SRolandF77} 39*a4751804SRolandF77 40*a4751804SRolandF77declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>) 41*a4751804SRolandF77 42*a4751804SRolandF77declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>) 43*a4751804SRolandF77 44*a4751804SRolandF77declare i32 @llvm.ppc.altivec.vcmpequh.p(i32, <8 x i16>, <8 x i16>) 45*a4751804SRolandF77 46*a4751804SRolandF77declare i32 @llvm.ppc.altivec.vcmpequb.p(i32, <16 x i8>, <16 x i8>) 47