xref: /llvm-project/llvm/test/CodeGen/PowerPC/reduce_scalarization.ll (revision 351a0d8a9053f14f5bee6d762ce5b40e08f3ceb4)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
3; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names \
4; RUN:     -ppc-vsr-nums-as-vr < %s | FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
6; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names \
7; RUN:     -ppc-vsr-nums-as-vr < %s | FileCheck %s
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
9; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
10; RUN:     < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
12; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
13; RUN:     < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
14
15; Function Attrs: norecurse nounwind readonly
16define dso_local <2 x double> @test1(<2 x float>* nocapture readonly %Ptr) {
17; CHECK-LABEL: test1:
18; CHECK:       # %bb.0: # %entry
19; CHECK-NEXT:    lfd f0, 0(r3)
20; CHECK-NEXT:    xxmrghw vs0, vs0, vs0
21; CHECK-NEXT:    xvcvspdp v2, vs0
22; CHECK-NEXT:    blr
23entry:
24  %0 = load <2 x float>, <2 x float>* %Ptr, align 8
25  %1 = fpext <2 x float> %0 to <2 x double>
26  ret <2 x double> %1
27}
28
29; Function Attrs: norecurse nounwind readonly
30define dso_local <2 x double> @test2(<2 x float>* nocapture readonly %a, <2 x float>* nocapture readonly %b) {
31; CHECK-LABEL: test2:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    lfd f0, 0(r4)
34; CHECK-NEXT:    lfd f1, 0(r3)
35; CHECK-NEXT:    xvsubsp vs0, vs1, vs0
36; CHECK-NEXT:    xxmrghw vs0, vs0, vs0
37; CHECK-NEXT:    xvcvspdp v2, vs0
38; CHECK-NEXT:    blr
39entry:
40  %0 = load <2 x float>, <2 x float>* %a, align 8
41  %1 = load <2 x float>, <2 x float>* %b, align 8
42  %sub = fsub <2 x float> %0, %1
43  %2 = fpext <2 x float> %sub to <2 x double>
44  ret <2 x double> %2
45}
46
47; Function Attrs: norecurse nounwind readonly
48; Function Attrs: norecurse nounwind readonly
49define dso_local <2 x double> @test3(<2 x float>* nocapture readonly %a, <2 x float>* nocapture readonly %b) {
50; CHECK-LABEL: test3:
51; CHECK:       # %bb.0: # %entry
52; CHECK-NEXT:    lfd f0, 0(r4)
53; CHECK-NEXT:    lfd f1, 0(r3)
54; CHECK-NEXT:    xvaddsp vs0, vs1, vs0
55; CHECK-NEXT:    xxmrghw vs0, vs0, vs0
56; CHECK-NEXT:    xvcvspdp v2, vs0
57; CHECK-NEXT:    blr
58entry:
59  %0 = load <2 x float>, <2 x float>* %a, align 8
60  %1 = load <2 x float>, <2 x float>* %b, align 8
61  %sub = fadd <2 x float> %0, %1
62  %2 = fpext <2 x float> %sub to <2 x double>
63  ret <2 x double> %2
64}
65
66; Function Attrs: norecurse nounwind readonly
67; Function Attrs: norecurse nounwind readonly
68define dso_local <2 x double> @test4(<2 x float>* nocapture readonly %a, <2 x float>* nocapture readonly %b) {
69; CHECK-LABEL: test4:
70; CHECK:       # %bb.0: # %entry
71; CHECK-NEXT:    lfd f0, 0(r4)
72; CHECK-NEXT:    lfd f1, 0(r3)
73; CHECK-NEXT:    xvmulsp vs0, vs1, vs0
74; CHECK-NEXT:    xxmrghw vs0, vs0, vs0
75; CHECK-NEXT:    xvcvspdp v2, vs0
76; CHECK-NEXT:    blr
77entry:
78  %0 = load <2 x float>, <2 x float>* %a, align 8
79  %1 = load <2 x float>, <2 x float>* %b, align 8
80  %sub = fmul <2 x float> %0, %1
81  %2 = fpext <2 x float> %sub to <2 x double>
82  ret <2 x double> %2
83}
84
85@G = dso_local local_unnamed_addr global <2 x float> <float 3.000000e+00, float 0x3FF3333340000000>, align 8
86
87; Function Attrs: mustprogress nofree norecurse nosync nounwind readonly uwtable willreturn
88define dso_local <2 x double> @test5(<2 x double> %a) {
89; CHECK-P10-LABEL: test5:
90; CHECK-P10:       # %bb.0: # %entry
91; CHECK-P10-NEXT:    plfd f0, G@PCREL(0), 1
92; CHECK-P10-NEXT:    xxmrghw vs0, vs0, vs0
93; CHECK-P10-NEXT:    xvcvspdp vs0, vs0
94; CHECK-P10-NEXT:    xvadddp v2, vs0, v2
95; CHECK-P10-NEXT:    blr
96;
97; CHECK-P10-BE-LABEL: test5:
98; CHECK-P10-BE:       # %bb.0: # %entry
99; CHECK-P10-BE-NEXT:    addis r3, r2, G@toc@ha
100; CHECK-P10-BE-NEXT:    lfd f0, G@toc@l(r3)
101; CHECK-P10-BE-NEXT:    xxmrghw vs0, vs0, vs0
102; CHECK-P10-BE-NEXT:    xvcvspdp vs0, vs0
103; CHECK-P10-BE-NEXT:    xvadddp v2, vs0, v2
104; CHECK-P10-BE-NEXT:    blr
105entry:
106  %0 = load <2 x float>, <2 x float>* @G, align 8
107  %1 = fpext <2 x float> %0 to <2 x double>
108  %add = fadd <2 x double> %1, %a
109  ret <2 x double> %add
110}
111