11445b77eSZi Xuan Wu; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64-- | FileCheck %s -check-prefixes=PWR8-CHECK,CHECK 21445b77eSZi Xuan Wu; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64le-- | FileCheck %s -check-prefixes=PWR9-CHECK,CHECK 31445b77eSZi Xuan Wu 41445b77eSZi Xuan Wudefine i32 @test1(i32 %a) { 51445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, 16 ; <i32> [#uses=1] 61445b77eSZi Xuan Wu ret i32 %tmp.1 71445b77eSZi Xuan Wu} 81445b77eSZi Xuan Wu; CHECK-LABEL: test1: 91445b77eSZi Xuan Wu; CHECK-NOT: mul 101445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 4 111445b77eSZi Xuan Wu 121445b77eSZi Xuan Wudefine i32 @test2(i32 %a) { 131445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, 17 ; <i32> [#uses=1] 141445b77eSZi Xuan Wu ret i32 %tmp.1 151445b77eSZi Xuan Wu} 161445b77eSZi Xuan Wu; CHECK-LABEL: test2: 171445b77eSZi Xuan Wu; CHECK-NOT: mul 181445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 4 191445b77eSZi Xuan Wu; CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]] 201445b77eSZi Xuan Wu 211445b77eSZi Xuan Wudefine i32 @test3(i32 %a) { 221445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, 15 ; <i32> [#uses=1] 231445b77eSZi Xuan Wu ret i32 %tmp.1 241445b77eSZi Xuan Wu} 251445b77eSZi Xuan Wu; CHECK-LABEL: test3: 261445b77eSZi Xuan Wu; CHECK-NOT: mul 271445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 4 28*86e3abc9SKang Zhang; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3 291445b77eSZi Xuan Wu 301445b77eSZi Xuan Wu; negtive constant 311445b77eSZi Xuan Wu 321445b77eSZi Xuan Wudefine i32 @test4(i32 %a) { 331445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, -16 ; <i32> [#uses=1] 341445b77eSZi Xuan Wu ret i32 %tmp.1 351445b77eSZi Xuan Wu} 361445b77eSZi Xuan Wu; CHECK-LABEL: test4: 371445b77eSZi Xuan Wu; CHECK-NOT: mul 381445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 4 391445b77eSZi Xuan Wu; CHECK-NEXT: neg r[[REG2:[0-9]+]], r[[REG1]] 401445b77eSZi Xuan Wu 411445b77eSZi Xuan Wudefine i32 @test5(i32 %a) { 421445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, -17 ; <i32> [#uses=1] 431445b77eSZi Xuan Wu ret i32 %tmp.1 441445b77eSZi Xuan Wu} 451445b77eSZi Xuan Wu; CHECK-LABEL: test5: 461445b77eSZi Xuan Wu; PWR9-CHECK: mulli r[[REG1:[0-9]+]], r3, -17 471445b77eSZi Xuan Wu; PWR8-CHECK-NOT: mul 481445b77eSZi Xuan Wu; PWR8-CHECK: slwi r[[REG1:[0-9]+]], r3, 4 491445b77eSZi Xuan Wu; PWR8-CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]] 501445b77eSZi Xuan Wu; PWR8-CHECK-NEXT: neg r{{[0-9]+}}, r[[REG2]] 511445b77eSZi Xuan Wu 521445b77eSZi Xuan Wudefine i32 @test6(i32 %a) { 531445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, -15 ; <i32> [#uses=1] 541445b77eSZi Xuan Wu ret i32 %tmp.1 551445b77eSZi Xuan Wu} 561445b77eSZi Xuan Wu; CHECK-LABEL: test6: 571445b77eSZi Xuan Wu; CHECK-NOT: mul 581445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 4 59*86e3abc9SKang Zhang; CHECK-NEXT: sub r[[REG2:[0-9]+]], r3, r[[REG1]] 601445b77eSZi Xuan Wu; CHECK-NOT: neg 611445b77eSZi Xuan Wu 621445b77eSZi Xuan Wu; boundary case 631445b77eSZi Xuan Wu 641445b77eSZi Xuan Wudefine i32 @test7(i32 %a) { 651445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, -2147483648 ; <i32> [#uses=1] 661445b77eSZi Xuan Wu ret i32 %tmp.1 671445b77eSZi Xuan Wu} 681445b77eSZi Xuan Wu; CHECK-LABEL: test7: 691445b77eSZi Xuan Wu; CHECK-NOT: mul 701445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 31 711445b77eSZi Xuan Wu 721445b77eSZi Xuan Wudefine i32 @test8(i32 %a) { 731445b77eSZi Xuan Wu %tmp.1 = mul nsw i32 %a, 2147483647 ; <i32> [#uses=1] 741445b77eSZi Xuan Wu ret i32 %tmp.1 751445b77eSZi Xuan Wu} 761445b77eSZi Xuan Wu; CHECK-LABEL: test8: 771445b77eSZi Xuan Wu; CHECK-NOT: mul 781445b77eSZi Xuan Wu; CHECK: slwi r[[REG1:[0-9]+]], r3, 31 79*86e3abc9SKang Zhang; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3 80