xref: /llvm-project/llvm/test/CodeGen/PowerPC/i32-to-float.ll (revision a538b0f023e858d0f71a1295bb9084e851ddd361)
1*a538b0f0SEhsan Amiri; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
2*a538b0f0SEhsan Amiri; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
3*a538b0f0SEhsan Amiri; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
4*a538b0f0SEhsan Amiri; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
5e53429a1SHal Finkeltarget datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
6e53429a1SHal Finkeltarget triple = "powerpc64-unknown-linux-gnu"
7e53429a1SHal Finkel
8e53429a1SHal Finkeldefine float @foo(i32 %a) nounwind {
9e53429a1SHal Finkelentry:
10e53429a1SHal Finkel  %x = sitofp i32 %a to float
11e53429a1SHal Finkel  ret float %x
12e53429a1SHal Finkel
13e53429a1SHal Finkel; CHECK: @foo
14e53429a1SHal Finkel; CHECK: extsw [[REG:[0-9]+]], 3
15e53429a1SHal Finkel; CHECK: std [[REG]],
16e53429a1SHal Finkel; CHECK: lfd [[REG2:[0-9]+]],
17e53429a1SHal Finkel; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
18e53429a1SHal Finkel; CHECK: frsp 1, [[REG3]]
19e53429a1SHal Finkel; CHECK: blr
20beb296beSHal Finkel
21f6d45f23SHal Finkel; CHECK-PWR6: @foo
22f6d45f23SHal Finkel; CHECK-PWR6: stw 3,
23f6d45f23SHal Finkel; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
24f6d45f23SHal Finkel; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
25f6d45f23SHal Finkel; CHECK-PWR6: frsp 1, [[REG2]]
26f6d45f23SHal Finkel; CHECK-PWR6: blr
27f6d45f23SHal Finkel
28beb296beSHal Finkel; CHECK-A2: @foo
29beb296beSHal Finkel; CHECK-A2: stw 3,
30beb296beSHal Finkel; CHECK-A2: lfiwax [[REG:[0-9]+]],
31f6d45f23SHal Finkel; CHECK-A2: fcfids 1, [[REG]]
32beb296beSHal Finkel; CHECK-A2: blr
334a912250SHal Finkel
344a912250SHal Finkel; CHECK-VSX: @foo
354a912250SHal Finkel; CHECK-VSX: stw 3,
364a912250SHal Finkel; CHECK-VSX: lfiwax [[REG:[0-9]+]],
374a912250SHal Finkel; CHECK-VSX: fcfids 1, [[REG]]
384a912250SHal Finkel; CHECK-VSX: blr
39e53429a1SHal Finkel}
40e53429a1SHal Finkel
41e53429a1SHal Finkeldefine double @goo(i32 %a) nounwind {
42e53429a1SHal Finkelentry:
43e53429a1SHal Finkel  %x = sitofp i32 %a to double
44e53429a1SHal Finkel  ret double %x
45e53429a1SHal Finkel
46e53429a1SHal Finkel; CHECK: @goo
47e53429a1SHal Finkel; CHECK: extsw [[REG:[0-9]+]], 3
48e53429a1SHal Finkel; CHECK: std [[REG]],
49e53429a1SHal Finkel; CHECK: lfd [[REG2:[0-9]+]],
50e53429a1SHal Finkel; CHECK: fcfid 1, [[REG2]]
51e53429a1SHal Finkel; CHECK: blr
52beb296beSHal Finkel
53f6d45f23SHal Finkel; CHECK-PWR6: @goo
54f6d45f23SHal Finkel; CHECK-PWR6: stw 3,
55f6d45f23SHal Finkel; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
56f6d45f23SHal Finkel; CHECK-PWR6: fcfid 1, [[REG]]
57f6d45f23SHal Finkel; CHECK-PWR6: blr
58f6d45f23SHal Finkel
59beb296beSHal Finkel; CHECK-A2: @goo
60beb296beSHal Finkel; CHECK-A2: stw 3,
61beb296beSHal Finkel; CHECK-A2: lfiwax [[REG:[0-9]+]],
62beb296beSHal Finkel; CHECK-A2: fcfid 1, [[REG]]
63beb296beSHal Finkel; CHECK-A2: blr
644a912250SHal Finkel
654a912250SHal Finkel; CHECK-VSX: @goo
664a912250SHal Finkel; CHECK-VSX: stw 3,
674a912250SHal Finkel; CHECK-VSX: lfiwax [[REG:[0-9]+]],
684a912250SHal Finkel; CHECK-VSX: xscvsxddp 1, [[REG]]
694a912250SHal Finkel; CHECK-VSX: blr
70e53429a1SHal Finkel}
71e53429a1SHal Finkel
72f6d45f23SHal Finkeldefine float @foou(i32 %a) nounwind {
73f6d45f23SHal Finkelentry:
74f6d45f23SHal Finkel  %x = uitofp i32 %a to float
75f6d45f23SHal Finkel  ret float %x
76f6d45f23SHal Finkel
77f6d45f23SHal Finkel; CHECK-A2: @foou
78f6d45f23SHal Finkel; CHECK-A2: stw 3,
79f6d45f23SHal Finkel; CHECK-A2: lfiwzx [[REG:[0-9]+]],
80f6d45f23SHal Finkel; CHECK-A2: fcfidus 1, [[REG]]
81f6d45f23SHal Finkel; CHECK-A2: blr
824a912250SHal Finkel
834a912250SHal Finkel; CHECK-VSX: @foou
844a912250SHal Finkel; CHECK-VSX: stw 3,
854a912250SHal Finkel; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
864a912250SHal Finkel; CHECK-VSX: fcfidus 1, [[REG]]
874a912250SHal Finkel; CHECK-VSX: blr
88f6d45f23SHal Finkel}
89f6d45f23SHal Finkel
90f6d45f23SHal Finkeldefine double @goou(i32 %a) nounwind {
91f6d45f23SHal Finkelentry:
92f6d45f23SHal Finkel  %x = uitofp i32 %a to double
93f6d45f23SHal Finkel  ret double %x
94f6d45f23SHal Finkel
95f6d45f23SHal Finkel; CHECK-A2: @goou
96f6d45f23SHal Finkel; CHECK-A2: stw 3,
97f6d45f23SHal Finkel; CHECK-A2: lfiwzx [[REG:[0-9]+]],
98f6d45f23SHal Finkel; CHECK-A2: fcfidu 1, [[REG]]
99f6d45f23SHal Finkel; CHECK-A2: blr
1004a912250SHal Finkel
1014a912250SHal Finkel; CHECK-VSX: @goou
1024a912250SHal Finkel; CHECK-VSX: stw 3,
1034a912250SHal Finkel; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
1044a912250SHal Finkel; CHECK-VSX: xscvuxddp 1, [[REG]]
1054a912250SHal Finkel; CHECK-VSX: blr
106f6d45f23SHal Finkel}
107f6d45f23SHal Finkel
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