1e8d2ff22SQiu Chaofan; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2e8d2ff22SQiu Chaofan; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3e8d2ff22SQiu Chaofan; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s 4e8d2ff22SQiu Chaofan; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 5e8d2ff22SQiu Chaofan; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s 6e8d2ff22SQiu Chaofan 7e8d2ff22SQiu Chaofandeclare <4 x float> @llvm.experimental.constrained.maxnum.v4f32(<4 x float>, <4 x float>, metadata) 8e8d2ff22SQiu Chaofandeclare <2 x double> @llvm.experimental.constrained.maxnum.v2f64(<2 x double>, <2 x double>, metadata) 9e8d2ff22SQiu Chaofandeclare <4 x float> @llvm.experimental.constrained.minnum.v4f32(<4 x float>, <4 x float>, metadata) 10e8d2ff22SQiu Chaofandeclare <2 x double> @llvm.experimental.constrained.minnum.v2f64(<2 x double>, <2 x double>, metadata) 11e8d2ff22SQiu Chaofan 12*66d1899eSKevin P. Nealdefine <4 x float> @fmaxnum_v4f32(<4 x float> %vf0, <4 x float> %vf1) #0 { 13e8d2ff22SQiu Chaofan; CHECK-LABEL: fmaxnum_v4f32: 14e8d2ff22SQiu Chaofan; CHECK: # %bb.0: 15e8d2ff22SQiu Chaofan; CHECK-NEXT: xvmaxsp v2, v2, v3 16e8d2ff22SQiu Chaofan; CHECK-NEXT: blr 17e8d2ff22SQiu Chaofan %res = call <4 x float> @llvm.experimental.constrained.maxnum.v4f32( 18e8d2ff22SQiu Chaofan <4 x float> %vf0, <4 x float> %vf1, 19*66d1899eSKevin P. Neal metadata !"fpexcept.strict") #0 20e8d2ff22SQiu Chaofan ret <4 x float> %res 21e8d2ff22SQiu Chaofan} 22e8d2ff22SQiu Chaofan 23*66d1899eSKevin P. Nealdefine <2 x double> @fmaxnum_v2f64(<2 x double> %vf0, <2 x double> %vf1) #0 { 24e8d2ff22SQiu Chaofan; CHECK-LABEL: fmaxnum_v2f64: 25e8d2ff22SQiu Chaofan; CHECK: # %bb.0: 26e8d2ff22SQiu Chaofan; CHECK-NEXT: xvmaxdp v2, v2, v3 27e8d2ff22SQiu Chaofan; CHECK-NEXT: blr 28e8d2ff22SQiu Chaofan %res = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64( 29e8d2ff22SQiu Chaofan <2 x double> %vf0, <2 x double> %vf1, 30*66d1899eSKevin P. Neal metadata !"fpexcept.strict") #0 31e8d2ff22SQiu Chaofan ret <2 x double> %res 32e8d2ff22SQiu Chaofan} 33e8d2ff22SQiu Chaofan 34e8d2ff22SQiu Chaofan 35*66d1899eSKevin P. Nealdefine <4 x float> @fminnum_v4f32(<4 x float> %vf0, <4 x float> %vf1) #0 { 36e8d2ff22SQiu Chaofan; CHECK-LABEL: fminnum_v4f32: 37e8d2ff22SQiu Chaofan; CHECK: # %bb.0: 38e8d2ff22SQiu Chaofan; CHECK-NEXT: xvminsp v2, v2, v3 39e8d2ff22SQiu Chaofan; CHECK-NEXT: blr 40e8d2ff22SQiu Chaofan %res = call <4 x float> @llvm.experimental.constrained.minnum.v4f32( 41e8d2ff22SQiu Chaofan <4 x float> %vf0, <4 x float> %vf1, 42*66d1899eSKevin P. Neal metadata !"fpexcept.strict") #0 43e8d2ff22SQiu Chaofan ret <4 x float> %res 44e8d2ff22SQiu Chaofan} 45e8d2ff22SQiu Chaofan 46*66d1899eSKevin P. Nealdefine <2 x double> @fminnum_v2f64(<2 x double> %vf0, <2 x double> %vf1) #0 { 47e8d2ff22SQiu Chaofan; CHECK-LABEL: fminnum_v2f64: 48e8d2ff22SQiu Chaofan; CHECK: # %bb.0: 49e8d2ff22SQiu Chaofan; CHECK-NEXT: xvmindp v2, v2, v3 50e8d2ff22SQiu Chaofan; CHECK-NEXT: blr 51e8d2ff22SQiu Chaofan %res = call <2 x double> @llvm.experimental.constrained.minnum.v2f64( 52e8d2ff22SQiu Chaofan <2 x double> %vf0, <2 x double> %vf1, 53*66d1899eSKevin P. Neal metadata !"fpexcept.strict") #0 54e8d2ff22SQiu Chaofan ret <2 x double> %res 55e8d2ff22SQiu Chaofan} 56*66d1899eSKevin P. Neal 57*66d1899eSKevin P. Nealattributes #0 = { strictfp } 58