1*89bbcbe2SRolandF77; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2*89bbcbe2SRolandF77; RUN: llc -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu \ 3*89bbcbe2SRolandF77; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 4*89bbcbe2SRolandF77; RUN: < %s | FileCheck %s 5*89bbcbe2SRolandF77 6*89bbcbe2SRolandF77define void @_blah() { 7*89bbcbe2SRolandF77; CHECK-LABEL: _blah: 8*89bbcbe2SRolandF77; CHECK: # %bb.0: # %entry 9*89bbcbe2SRolandF77; CHECK-NEXT: li r3, 0 10*89bbcbe2SRolandF77; CHECK-NEXT: li r4, 15 11*89bbcbe2SRolandF77; CHECK-NEXT: lvx v3, 0, r4 12*89bbcbe2SRolandF77; CHECK-NEXT: addi r5, r1, -64 13*89bbcbe2SRolandF77; CHECK-NEXT: lvx v4, 0, r3 14*89bbcbe2SRolandF77; CHECK-NEXT: lvsl v2, 0, r3 15*89bbcbe2SRolandF77; CHECK-NEXT: vperm v2, v4, v3, v2 16*89bbcbe2SRolandF77; CHECK-NEXT: lwz r4, 16(0) 17*89bbcbe2SRolandF77; CHECK-NEXT: stvx v2, 0, r5 18*89bbcbe2SRolandF77; CHECK-NEXT: lhz r5, -64(r1) 19*89bbcbe2SRolandF77; CHECK-NEXT: lhz r6, -58(r1) 20*89bbcbe2SRolandF77; CHECK-NEXT: lhz r7, -52(r1) 21*89bbcbe2SRolandF77; CHECK-NEXT: sth r4, -34(r1) 22*89bbcbe2SRolandF77; CHECK-NEXT: sth r3, -36(r1) 23*89bbcbe2SRolandF77; CHECK-NEXT: sth r3, -40(r1) 24*89bbcbe2SRolandF77; CHECK-NEXT: sth r3, -44(r1) 25*89bbcbe2SRolandF77; CHECK-NEXT: sth r3, -48(r1) 26*89bbcbe2SRolandF77; CHECK-NEXT: addi r3, r1, -48 27*89bbcbe2SRolandF77; CHECK-NEXT: sth r7, -38(r1) 28*89bbcbe2SRolandF77; CHECK-NEXT: sth r6, -42(r1) 29*89bbcbe2SRolandF77; CHECK-NEXT: sth r5, -46(r1) 30*89bbcbe2SRolandF77; CHECK-NEXT: lvx v2, 0, r3 31*89bbcbe2SRolandF77; CHECK-NEXT: addi r3, r1, -32 32*89bbcbe2SRolandF77; CHECK-NEXT: vsldoi v3, v2, v2, 8 33*89bbcbe2SRolandF77; CHECK-NEXT: vmaxuw v2, v2, v3 34*89bbcbe2SRolandF77; CHECK-NEXT: vspltw v3, v2, 1 35*89bbcbe2SRolandF77; CHECK-NEXT: vmaxuw v2, v2, v3 36*89bbcbe2SRolandF77; CHECK-NEXT: stvx v2, 0, r3 37*89bbcbe2SRolandF77; CHECK-NEXT: lwz r3, -32(r1) 38*89bbcbe2SRolandF77; CHECK-NEXT: cmplwi r3, 0 39*89bbcbe2SRolandF77; CHECK-NEXT: blr 40*89bbcbe2SRolandF77entry: 41*89bbcbe2SRolandF77 %wide.vec904 = load <12 x i16>, ptr null, align 2 42*89bbcbe2SRolandF77 %strided.vec905 = shufflevector <12 x i16> %wide.vec904, <12 x i16> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 6, i32 9> 43*89bbcbe2SRolandF77 %0 = zext <4 x i16> %strided.vec905 to <4 x i32> 44*89bbcbe2SRolandF77 %1 = tail call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %0) 45*89bbcbe2SRolandF77 %cmp55.not823 = icmp ugt i32 1, %1 46*89bbcbe2SRolandF77 br i1 %cmp55.not823, label %for.cond.cleanup56, label %for.body57.lr.ph 47*89bbcbe2SRolandF77 48*89bbcbe2SRolandF77for.body57.lr.ph: ; preds = %entry 49*89bbcbe2SRolandF77 ret void 50*89bbcbe2SRolandF77 51*89bbcbe2SRolandF77for.cond.cleanup56: ; preds = %entry 52*89bbcbe2SRolandF77 ret void 53*89bbcbe2SRolandF77} 54*89bbcbe2SRolandF77 55*89bbcbe2SRolandF77declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>) 56