xref: /llvm-project/llvm/test/CodeGen/PowerPC/cgp-select.ll (revision 5ecd363295089ad2db3c428ab1ee08ef1864ce3b)
1c0da8a4eSKai Luo; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2c0da8a4eSKai Luo; RUN: llc -O3 -mcpu=pwr9 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
3c0da8a4eSKai Luo
4*427fb351SKai Nackedefine dso_local void @wibble(ptr nocapture readonly %arg, i32 signext %arg1, ptr nocapture %arg2, ptr nocapture %arg3) {
5c0da8a4eSKai Luo; CHECK-LABEL: wibble:
6c0da8a4eSKai Luo; CHECK:       # %bb.0: # %bb
7c0da8a4eSKai Luo; CHECK-NEXT:    lfs 0, 0(3)
8c0da8a4eSKai Luo; CHECK-NEXT:    li 7, 7
9c0da8a4eSKai Luo; CHECK-NEXT:    cmpwi 4, 2
10c0da8a4eSKai Luo; CHECK-NEXT:    xsaddsp 0, 0, 0
11c0da8a4eSKai Luo; CHECK-NEXT:    blt 0, .LBB0_5
12c0da8a4eSKai Luo; CHECK-NEXT:  # %bb.1: # %bb6
13c0da8a4eSKai Luo; CHECK-NEXT:    clrldi 4, 4, 32
14c0da8a4eSKai Luo; CHECK-NEXT:    addi 4, 4, -1
15c0da8a4eSKai Luo; CHECK-NEXT:    mtctr 4
16c0da8a4eSKai Luo; CHECK-NEXT:    li 4, 8
17c0da8a4eSKai Luo; CHECK-NEXT:    b .LBB0_3
18c0da8a4eSKai Luo; CHECK-NEXT:    .p2align 5
19c0da8a4eSKai Luo; CHECK-NEXT:  .LBB0_2: # %bb11
20c0da8a4eSKai Luo; CHECK-NEXT:    #
21c0da8a4eSKai Luo; CHECK-NEXT:    iselgt 7, 4, 7
22c0da8a4eSKai Luo; CHECK-NEXT:    addi 4, 4, 1
23c0da8a4eSKai Luo; CHECK-NEXT:    bdz .LBB0_5
24c0da8a4eSKai Luo; CHECK-NEXT:  .LBB0_3: # %bb11
25c0da8a4eSKai Luo; CHECK-NEXT:    #
26c0da8a4eSKai Luo; CHECK-NEXT:    lfsu 1, 4(3)
27c0da8a4eSKai Luo; CHECK-NEXT:    fcmpu 0, 1, 0
28c0da8a4eSKai Luo; CHECK-NEXT:    ble 0, .LBB0_2
29c0da8a4eSKai Luo; CHECK-NEXT:  # %bb.4:
30c0da8a4eSKai Luo; CHECK-NEXT:    xsaddsp 0, 1, 1
31c0da8a4eSKai Luo; CHECK-NEXT:    b .LBB0_2
32c0da8a4eSKai Luo; CHECK-NEXT:  .LBB0_5: # %bb8
33c0da8a4eSKai Luo; CHECK-NEXT:    stw 7, 0(5)
34c0da8a4eSKai Luo; CHECK-NEXT:    stfs 0, 0(6)
35c0da8a4eSKai Luo; CHECK-NEXT:    blr
36c0da8a4eSKai Luobb:
37*427fb351SKai Nacke  %tmp = load float, ptr %arg, align 4
38c0da8a4eSKai Luo  %tmp4 = fmul float %tmp, 2.000000e+00
39c0da8a4eSKai Luo  %tmp5 = icmp sgt i32 %arg1, 1
40c0da8a4eSKai Luo  br i1 %tmp5, label %bb6, label %bb8
41c0da8a4eSKai Luo
42c0da8a4eSKai Luobb6:                                              ; preds = %bb
43c0da8a4eSKai Luo  %tmp7 = zext i32 %arg1 to i64
44c0da8a4eSKai Luo  br label %bb11
45c0da8a4eSKai Luo
46c0da8a4eSKai Luobb8:                                              ; preds = %bb11, %bb
47c0da8a4eSKai Luo  %tmp9 = phi float [ %tmp4, %bb ], [ %tmp19, %bb11 ]
48c0da8a4eSKai Luo  %tmp10 = phi i32 [ 7, %bb ], [ %tmp22, %bb11 ]
49*427fb351SKai Nacke  store i32 %tmp10, ptr %arg2, align 4
50*427fb351SKai Nacke  store float %tmp9, ptr %arg3, align 4
51c0da8a4eSKai Luo  ret void
52c0da8a4eSKai Luo
53c0da8a4eSKai Luobb11:                                             ; preds = %bb11, %bb6
54c0da8a4eSKai Luo  %tmp12 = phi i64 [ 1, %bb6 ], [ %tmp23, %bb11 ]
55c0da8a4eSKai Luo  %tmp13 = phi i32 [ 7, %bb6 ], [ %tmp22, %bb11 ]
56c0da8a4eSKai Luo  %tmp14 = phi float [ %tmp4, %bb6 ], [ %tmp19, %bb11 ]
57*427fb351SKai Nacke  %tmp15 = getelementptr inbounds float, ptr %arg, i64 %tmp12
58*427fb351SKai Nacke  %tmp16 = load float, ptr %tmp15, align 4
59c0da8a4eSKai Luo  %tmp17 = fcmp ogt float %tmp16, %tmp14
60c0da8a4eSKai Luo  %tmp18 = fmul float %tmp16, 2.000000e+00
61c0da8a4eSKai Luo  %tmp19 = select i1 %tmp17, float %tmp18, float %tmp14
62c0da8a4eSKai Luo  %tmp20 = trunc i64 %tmp12 to i32
63c0da8a4eSKai Luo  %tmp21 = add i32 %tmp20, 7
64c0da8a4eSKai Luo  %tmp22 = select i1 %tmp17, i32 %tmp21, i32 %tmp13
65c0da8a4eSKai Luo  %tmp23 = add nuw nsw i64 %tmp12, 1
66c0da8a4eSKai Luo  %tmp24 = icmp eq i64 %tmp23, %tmp7
67c0da8a4eSKai Luo  br i1 %tmp24, label %bb8, label %bb11
68c0da8a4eSKai Luo}
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