1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(double *ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(float *ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(double *ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(float *ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(double *ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(float *ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712; Function Attrs: norecurse nounwind readnone 713define <4 x i32> @allZeroi() { 714; P9BE-LABEL: allZeroi: 715; P9BE: # %bb.0: # %entry 716; P9BE-NEXT: xxlxor v2, v2, v2 717; P9BE-NEXT: blr 718; 719; P9LE-LABEL: allZeroi: 720; P9LE: # %bb.0: # %entry 721; P9LE-NEXT: xxlxor v2, v2, v2 722; P9LE-NEXT: blr 723; 724; P8BE-LABEL: allZeroi: 725; P8BE: # %bb.0: # %entry 726; P8BE-NEXT: xxlxor v2, v2, v2 727; P8BE-NEXT: blr 728; 729; P8LE-LABEL: allZeroi: 730; P8LE: # %bb.0: # %entry 731; P8LE-NEXT: xxlxor v2, v2, v2 732; P8LE-NEXT: blr 733entry: 734 ret <4 x i32> zeroinitializer 735} 736 737; Function Attrs: norecurse nounwind readnone 738define <4 x i32> @spltConst1i() { 739; P9BE-LABEL: spltConst1i: 740; P9BE: # %bb.0: # %entry 741; P9BE-NEXT: vspltisw v2, 1 742; P9BE-NEXT: blr 743; 744; P9LE-LABEL: spltConst1i: 745; P9LE: # %bb.0: # %entry 746; P9LE-NEXT: vspltisw v2, 1 747; P9LE-NEXT: blr 748; 749; P8BE-LABEL: spltConst1i: 750; P8BE: # %bb.0: # %entry 751; P8BE-NEXT: vspltisw v2, 1 752; P8BE-NEXT: blr 753; 754; P8LE-LABEL: spltConst1i: 755; P8LE: # %bb.0: # %entry 756; P8LE-NEXT: vspltisw v2, 1 757; P8LE-NEXT: blr 758entry: 759 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 760} 761 762; Function Attrs: norecurse nounwind readnone 763define <4 x i32> @spltConst16ki() { 764; P9BE-LABEL: spltConst16ki: 765; P9BE: # %bb.0: # %entry 766; P9BE-NEXT: vspltisw v2, -15 767; P9BE-NEXT: vsrw v2, v2, v2 768; P9BE-NEXT: blr 769; 770; P9LE-LABEL: spltConst16ki: 771; P9LE: # %bb.0: # %entry 772; P9LE-NEXT: vspltisw v2, -15 773; P9LE-NEXT: vsrw v2, v2, v2 774; P9LE-NEXT: blr 775; 776; P8BE-LABEL: spltConst16ki: 777; P8BE: # %bb.0: # %entry 778; P8BE-NEXT: vspltisw v2, -15 779; P8BE-NEXT: vsrw v2, v2, v2 780; P8BE-NEXT: blr 781; 782; P8LE-LABEL: spltConst16ki: 783; P8LE: # %bb.0: # %entry 784; P8LE-NEXT: vspltisw v2, -15 785; P8LE-NEXT: vsrw v2, v2, v2 786; P8LE-NEXT: blr 787entry: 788 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 789} 790 791; Function Attrs: norecurse nounwind readnone 792define <4 x i32> @spltConst32ki() { 793; P9BE-LABEL: spltConst32ki: 794; P9BE: # %bb.0: # %entry 795; P9BE-NEXT: vspltisw v2, -16 796; P9BE-NEXT: vsrw v2, v2, v2 797; P9BE-NEXT: blr 798; 799; P9LE-LABEL: spltConst32ki: 800; P9LE: # %bb.0: # %entry 801; P9LE-NEXT: vspltisw v2, -16 802; P9LE-NEXT: vsrw v2, v2, v2 803; P9LE-NEXT: blr 804; 805; P8BE-LABEL: spltConst32ki: 806; P8BE: # %bb.0: # %entry 807; P8BE-NEXT: vspltisw v2, -16 808; P8BE-NEXT: vsrw v2, v2, v2 809; P8BE-NEXT: blr 810; 811; P8LE-LABEL: spltConst32ki: 812; P8LE: # %bb.0: # %entry 813; P8LE-NEXT: vspltisw v2, -16 814; P8LE-NEXT: vsrw v2, v2, v2 815; P8LE-NEXT: blr 816entry: 817 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 818} 819 820; Function Attrs: norecurse nounwind readnone 821define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 822; P9BE-LABEL: fromRegsi: 823; P9BE: # %bb.0: # %entry 824; P9BE-NEXT: rldimi r6, r5, 32, 0 825; P9BE-NEXT: rldimi r4, r3, 32, 0 826; P9BE-NEXT: mtvsrdd v2, r4, r6 827; P9BE-NEXT: blr 828; 829; P9LE-LABEL: fromRegsi: 830; P9LE: # %bb.0: # %entry 831; P9LE-NEXT: rldimi r3, r4, 32, 0 832; P9LE-NEXT: rldimi r5, r6, 32, 0 833; P9LE-NEXT: mtvsrdd v2, r5, r3 834; P9LE-NEXT: blr 835; 836; P8BE-LABEL: fromRegsi: 837; P8BE: # %bb.0: # %entry 838; P8BE-NEXT: rldimi r6, r5, 32, 0 839; P8BE-NEXT: rldimi r4, r3, 32, 0 840; P8BE-NEXT: mtvsrd f0, r6 841; P8BE-NEXT: mtvsrd f1, r4 842; P8BE-NEXT: xxmrghd v2, vs1, vs0 843; P8BE-NEXT: blr 844; 845; P8LE-LABEL: fromRegsi: 846; P8LE: # %bb.0: # %entry 847; P8LE-NEXT: rldimi r3, r4, 32, 0 848; P8LE-NEXT: rldimi r5, r6, 32, 0 849; P8LE-NEXT: mtvsrd f0, r3 850; P8LE-NEXT: mtvsrd f1, r5 851; P8LE-NEXT: xxmrghd v2, vs1, vs0 852; P8LE-NEXT: blr 853entry: 854 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 855 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 856 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 857 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 858 ret <4 x i32> %vecinit3 859} 860 861; Function Attrs: norecurse nounwind readnone 862define <4 x i32> @fromDiffConstsi() { 863; P9BE-LABEL: fromDiffConstsi: 864; P9BE: # %bb.0: # %entry 865; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 866; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 867; P9BE-NEXT: lxvx v2, 0, r3 868; P9BE-NEXT: blr 869; 870; P9LE-LABEL: fromDiffConstsi: 871; P9LE: # %bb.0: # %entry 872; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 873; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 874; P9LE-NEXT: lxvx v2, 0, r3 875; P9LE-NEXT: blr 876; 877; P8BE-LABEL: fromDiffConstsi: 878; P8BE: # %bb.0: # %entry 879; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 880; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 881; P8BE-NEXT: lxvw4x v2, 0, r3 882; P8BE-NEXT: blr 883; 884; P8LE-LABEL: fromDiffConstsi: 885; P8LE: # %bb.0: # %entry 886; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 887; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 888; P8LE-NEXT: lvx v2, 0, r3 889; P8LE-NEXT: blr 890entry: 891 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 892} 893 894; Function Attrs: norecurse nounwind readonly 895define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 896; P9BE-LABEL: fromDiffMemConsAi: 897; P9BE: # %bb.0: # %entry 898; P9BE-NEXT: lxv v2, 0(r3) 899; P9BE-NEXT: blr 900; 901; P9LE-LABEL: fromDiffMemConsAi: 902; P9LE: # %bb.0: # %entry 903; P9LE-NEXT: lxv v2, 0(r3) 904; P9LE-NEXT: blr 905; 906; P8BE-LABEL: fromDiffMemConsAi: 907; P8BE: # %bb.0: # %entry 908; P8BE-NEXT: lxvw4x v2, 0, r3 909; P8BE-NEXT: blr 910; 911; P8LE-LABEL: fromDiffMemConsAi: 912; P8LE: # %bb.0: # %entry 913; P8LE-NEXT: lxvd2x vs0, 0, r3 914; P8LE-NEXT: xxswapd v2, vs0 915; P8LE-NEXT: blr 916entry: 917 %0 = load i32, i32* %arr, align 4 918 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 919 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 920 %1 = load i32, i32* %arrayidx1, align 4 921 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 922 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 923 %2 = load i32, i32* %arrayidx3, align 4 924 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 925 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 926 %3 = load i32, i32* %arrayidx5, align 4 927 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 928 ret <4 x i32> %vecinit6 929} 930 931; Function Attrs: norecurse nounwind readonly 932define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 933; P9BE-LABEL: fromDiffMemConsDi: 934; P9BE: # %bb.0: # %entry 935; P9BE-NEXT: lxv v2, 0(r3) 936; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 937; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 938; P9BE-NEXT: lxvx v3, 0, r3 939; P9BE-NEXT: vperm v2, v2, v2, v3 940; P9BE-NEXT: blr 941; 942; P9LE-LABEL: fromDiffMemConsDi: 943; P9LE: # %bb.0: # %entry 944; P9LE-NEXT: lxvw4x v2, 0, r3 945; P9LE-NEXT: blr 946; 947; P8BE-LABEL: fromDiffMemConsDi: 948; P8BE: # %bb.0: # %entry 949; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 950; P8BE-NEXT: lxvw4x v2, 0, r3 951; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l 952; P8BE-NEXT: lxvw4x v3, 0, r4 953; P8BE-NEXT: vperm v2, v2, v2, v3 954; P8BE-NEXT: blr 955; 956; P8LE-LABEL: fromDiffMemConsDi: 957; P8LE: # %bb.0: # %entry 958; P8LE-NEXT: lxvd2x vs0, 0, r3 959; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 960; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l 961; P8LE-NEXT: lvx v2, 0, r3 962; P8LE-NEXT: xxswapd v3, vs0 963; P8LE-NEXT: vperm v2, v3, v3, v2 964; P8LE-NEXT: blr 965entry: 966 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 967 %0 = load i32, i32* %arrayidx, align 4 968 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 969 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 970 %1 = load i32, i32* %arrayidx1, align 4 971 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 972 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 973 %2 = load i32, i32* %arrayidx3, align 4 974 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 975 %3 = load i32, i32* %arr, align 4 976 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 977 ret <4 x i32> %vecinit6 978} 979 980; Function Attrs: norecurse nounwind readonly 981define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 982; P9BE-LABEL: fromDiffMemVarAi: 983; P9BE: # %bb.0: # %entry 984; P9BE-NEXT: sldi r4, r4, 2 985; P9BE-NEXT: lxvx v2, r3, r4 986; P9BE-NEXT: blr 987; 988; P9LE-LABEL: fromDiffMemVarAi: 989; P9LE: # %bb.0: # %entry 990; P9LE-NEXT: sldi r4, r4, 2 991; P9LE-NEXT: lxvx v2, r3, r4 992; P9LE-NEXT: blr 993; 994; P8BE-LABEL: fromDiffMemVarAi: 995; P8BE: # %bb.0: # %entry 996; P8BE-NEXT: sldi r4, r4, 2 997; P8BE-NEXT: lxvw4x v2, r3, r4 998; P8BE-NEXT: blr 999; 1000; P8LE-LABEL: fromDiffMemVarAi: 1001; P8LE: # %bb.0: # %entry 1002; P8LE-NEXT: sldi r4, r4, 2 1003; P8LE-NEXT: lxvd2x vs0, r3, r4 1004; P8LE-NEXT: xxswapd v2, vs0 1005; P8LE-NEXT: blr 1006entry: 1007 %idxprom = sext i32 %elem to i64 1008 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1009 %0 = load i32, i32* %arrayidx, align 4 1010 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1011 %add = add nsw i32 %elem, 1 1012 %idxprom1 = sext i32 %add to i64 1013 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1014 %1 = load i32, i32* %arrayidx2, align 4 1015 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1016 %add4 = add nsw i32 %elem, 2 1017 %idxprom5 = sext i32 %add4 to i64 1018 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1019 %2 = load i32, i32* %arrayidx6, align 4 1020 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1021 %add8 = add nsw i32 %elem, 3 1022 %idxprom9 = sext i32 %add8 to i64 1023 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1024 %3 = load i32, i32* %arrayidx10, align 4 1025 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1026 ret <4 x i32> %vecinit11 1027} 1028 1029; Function Attrs: norecurse nounwind readonly 1030define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1031; P9BE-LABEL: fromDiffMemVarDi: 1032; P9BE: # %bb.0: # %entry 1033; P9BE-NEXT: sldi r4, r4, 2 1034; P9BE-NEXT: add r3, r3, r4 1035; P9BE-NEXT: addi r3, r3, -12 1036; P9BE-NEXT: lxvx v2, 0, r3 1037; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1038; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1039; P9BE-NEXT: lxvx v3, 0, r3 1040; P9BE-NEXT: vperm v2, v2, v2, v3 1041; P9BE-NEXT: blr 1042; 1043; P9LE-LABEL: fromDiffMemVarDi: 1044; P9LE: # %bb.0: # %entry 1045; P9LE-NEXT: sldi r4, r4, 2 1046; P9LE-NEXT: add r3, r3, r4 1047; P9LE-NEXT: addi r3, r3, -12 1048; P9LE-NEXT: lxvx v2, 0, r3 1049; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1050; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1051; P9LE-NEXT: lxvx v3, 0, r3 1052; P9LE-NEXT: vperm v2, v2, v2, v3 1053; P9LE-NEXT: blr 1054; 1055; P8BE-LABEL: fromDiffMemVarDi: 1056; P8BE: # %bb.0: # %entry 1057; P8BE-NEXT: sldi r4, r4, 2 1058; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1059; P8BE-NEXT: add r3, r3, r4 1060; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1061; P8BE-NEXT: addi r3, r3, -12 1062; P8BE-NEXT: lxvw4x v3, 0, r4 1063; P8BE-NEXT: lxvw4x v2, 0, r3 1064; P8BE-NEXT: vperm v2, v2, v2, v3 1065; P8BE-NEXT: blr 1066; 1067; P8LE-LABEL: fromDiffMemVarDi: 1068; P8LE: # %bb.0: # %entry 1069; P8LE-NEXT: sldi r4, r4, 2 1070; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1071; P8LE-NEXT: add r3, r3, r4 1072; P8LE-NEXT: addi r3, r3, -12 1073; P8LE-NEXT: lxvd2x vs0, 0, r3 1074; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l 1075; P8LE-NEXT: lvx v3, 0, r3 1076; P8LE-NEXT: xxswapd v2, vs0 1077; P8LE-NEXT: vperm v2, v2, v2, v3 1078; P8LE-NEXT: blr 1079entry: 1080 %idxprom = sext i32 %elem to i64 1081 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1082 %0 = load i32, i32* %arrayidx, align 4 1083 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1084 %sub = add nsw i32 %elem, -1 1085 %idxprom1 = sext i32 %sub to i64 1086 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1087 %1 = load i32, i32* %arrayidx2, align 4 1088 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1089 %sub4 = add nsw i32 %elem, -2 1090 %idxprom5 = sext i32 %sub4 to i64 1091 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1092 %2 = load i32, i32* %arrayidx6, align 4 1093 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1094 %sub8 = add nsw i32 %elem, -3 1095 %idxprom9 = sext i32 %sub8 to i64 1096 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1097 %3 = load i32, i32* %arrayidx10, align 4 1098 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1099 ret <4 x i32> %vecinit11 1100} 1101 1102; Function Attrs: norecurse nounwind readonly 1103define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1104; P9BE-LABEL: fromRandMemConsi: 1105; P9BE: # %bb.0: # %entry 1106; P9BE-NEXT: lwz r4, 16(r3) 1107; P9BE-NEXT: lwz r5, 72(r3) 1108; P9BE-NEXT: lwz r6, 8(r3) 1109; P9BE-NEXT: lwz r3, 352(r3) 1110; P9BE-NEXT: rldimi r3, r6, 32, 0 1111; P9BE-NEXT: rldimi r5, r4, 32, 0 1112; P9BE-NEXT: mtvsrdd v2, r5, r3 1113; P9BE-NEXT: blr 1114; 1115; P9LE-LABEL: fromRandMemConsi: 1116; P9LE: # %bb.0: # %entry 1117; P9LE-NEXT: lwz r4, 16(r3) 1118; P9LE-NEXT: lwz r5, 72(r3) 1119; P9LE-NEXT: lwz r6, 8(r3) 1120; P9LE-NEXT: lwz r3, 352(r3) 1121; P9LE-NEXT: rldimi r4, r5, 32, 0 1122; P9LE-NEXT: rldimi r6, r3, 32, 0 1123; P9LE-NEXT: mtvsrdd v2, r6, r4 1124; P9LE-NEXT: blr 1125; 1126; P8BE-LABEL: fromRandMemConsi: 1127; P8BE: # %bb.0: # %entry 1128; P8BE-NEXT: lwz r4, 8(r3) 1129; P8BE-NEXT: lwz r5, 352(r3) 1130; P8BE-NEXT: lwz r6, 16(r3) 1131; P8BE-NEXT: lwz r3, 72(r3) 1132; P8BE-NEXT: rldimi r5, r4, 32, 0 1133; P8BE-NEXT: rldimi r3, r6, 32, 0 1134; P8BE-NEXT: mtvsrd f0, r5 1135; P8BE-NEXT: mtvsrd f1, r3 1136; P8BE-NEXT: xxmrghd v2, vs1, vs0 1137; P8BE-NEXT: blr 1138; 1139; P8LE-LABEL: fromRandMemConsi: 1140; P8LE: # %bb.0: # %entry 1141; P8LE-NEXT: lwz r4, 16(r3) 1142; P8LE-NEXT: lwz r5, 72(r3) 1143; P8LE-NEXT: lwz r6, 8(r3) 1144; P8LE-NEXT: lwz r3, 352(r3) 1145; P8LE-NEXT: rldimi r4, r5, 32, 0 1146; P8LE-NEXT: rldimi r6, r3, 32, 0 1147; P8LE-NEXT: mtvsrd f0, r4 1148; P8LE-NEXT: mtvsrd f1, r6 1149; P8LE-NEXT: xxmrghd v2, vs1, vs0 1150; P8LE-NEXT: blr 1151entry: 1152 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1153 %0 = load i32, i32* %arrayidx, align 4 1154 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1155 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1156 %1 = load i32, i32* %arrayidx1, align 4 1157 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1158 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1159 %2 = load i32, i32* %arrayidx3, align 4 1160 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1161 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1162 %3 = load i32, i32* %arrayidx5, align 4 1163 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1164 ret <4 x i32> %vecinit6 1165} 1166 1167; Function Attrs: norecurse nounwind readonly 1168define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1169; P9BE-LABEL: fromRandMemVari: 1170; P9BE: # %bb.0: # %entry 1171; P9BE-NEXT: sldi r4, r4, 2 1172; P9BE-NEXT: add r3, r3, r4 1173; P9BE-NEXT: lwz r4, 16(r3) 1174; P9BE-NEXT: lwz r5, 4(r3) 1175; P9BE-NEXT: lwz r6, 8(r3) 1176; P9BE-NEXT: lwz r3, 32(r3) 1177; P9BE-NEXT: rldimi r3, r6, 32, 0 1178; P9BE-NEXT: rldimi r5, r4, 32, 0 1179; P9BE-NEXT: mtvsrdd v2, r5, r3 1180; P9BE-NEXT: blr 1181; 1182; P9LE-LABEL: fromRandMemVari: 1183; P9LE: # %bb.0: # %entry 1184; P9LE-NEXT: sldi r4, r4, 2 1185; P9LE-NEXT: add r3, r3, r4 1186; P9LE-NEXT: lwz r4, 16(r3) 1187; P9LE-NEXT: lwz r5, 4(r3) 1188; P9LE-NEXT: lwz r6, 8(r3) 1189; P9LE-NEXT: lwz r3, 32(r3) 1190; P9LE-NEXT: rldimi r4, r5, 32, 0 1191; P9LE-NEXT: rldimi r6, r3, 32, 0 1192; P9LE-NEXT: mtvsrdd v2, r6, r4 1193; P9LE-NEXT: blr 1194; 1195; P8BE-LABEL: fromRandMemVari: 1196; P8BE: # %bb.0: # %entry 1197; P8BE-NEXT: sldi r4, r4, 2 1198; P8BE-NEXT: add r3, r3, r4 1199; P8BE-NEXT: lwz r4, 8(r3) 1200; P8BE-NEXT: lwz r5, 32(r3) 1201; P8BE-NEXT: lwz r6, 16(r3) 1202; P8BE-NEXT: lwz r3, 4(r3) 1203; P8BE-NEXT: rldimi r5, r4, 32, 0 1204; P8BE-NEXT: rldimi r3, r6, 32, 0 1205; P8BE-NEXT: mtvsrd f0, r5 1206; P8BE-NEXT: mtvsrd f1, r3 1207; P8BE-NEXT: xxmrghd v2, vs1, vs0 1208; P8BE-NEXT: blr 1209; 1210; P8LE-LABEL: fromRandMemVari: 1211; P8LE: # %bb.0: # %entry 1212; P8LE-NEXT: sldi r4, r4, 2 1213; P8LE-NEXT: add r3, r3, r4 1214; P8LE-NEXT: lwz r4, 16(r3) 1215; P8LE-NEXT: lwz r5, 4(r3) 1216; P8LE-NEXT: lwz r6, 8(r3) 1217; P8LE-NEXT: lwz r3, 32(r3) 1218; P8LE-NEXT: rldimi r4, r5, 32, 0 1219; P8LE-NEXT: rldimi r6, r3, 32, 0 1220; P8LE-NEXT: mtvsrd f0, r4 1221; P8LE-NEXT: mtvsrd f1, r6 1222; P8LE-NEXT: xxmrghd v2, vs1, vs0 1223; P8LE-NEXT: blr 1224entry: 1225 %add = add nsw i32 %elem, 4 1226 %idxprom = sext i32 %add to i64 1227 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1228 %0 = load i32, i32* %arrayidx, align 4 1229 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1230 %add1 = add nsw i32 %elem, 1 1231 %idxprom2 = sext i32 %add1 to i64 1232 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1233 %1 = load i32, i32* %arrayidx3, align 4 1234 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1235 %add5 = add nsw i32 %elem, 2 1236 %idxprom6 = sext i32 %add5 to i64 1237 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1238 %2 = load i32, i32* %arrayidx7, align 4 1239 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1240 %add9 = add nsw i32 %elem, 8 1241 %idxprom10 = sext i32 %add9 to i64 1242 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1243 %3 = load i32, i32* %arrayidx11, align 4 1244 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1245 ret <4 x i32> %vecinit12 1246} 1247 1248; Function Attrs: norecurse nounwind readnone 1249define <4 x i32> @spltRegVali(i32 signext %val) { 1250; P9BE-LABEL: spltRegVali: 1251; P9BE: # %bb.0: # %entry 1252; P9BE-NEXT: mtvsrws v2, r3 1253; P9BE-NEXT: blr 1254; 1255; P9LE-LABEL: spltRegVali: 1256; P9LE: # %bb.0: # %entry 1257; P9LE-NEXT: mtvsrws v2, r3 1258; P9LE-NEXT: blr 1259; 1260; P8BE-LABEL: spltRegVali: 1261; P8BE: # %bb.0: # %entry 1262; P8BE-NEXT: mtvsrwz f0, r3 1263; P8BE-NEXT: xxspltw v2, vs0, 1 1264; P8BE-NEXT: blr 1265; 1266; P8LE-LABEL: spltRegVali: 1267; P8LE: # %bb.0: # %entry 1268; P8LE-NEXT: mtvsrwz f0, r3 1269; P8LE-NEXT: xxspltw v2, vs0, 1 1270; P8LE-NEXT: blr 1271entry: 1272 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1273 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1274 ret <4 x i32> %splat.splat 1275} 1276 1277; Function Attrs: norecurse nounwind readonly 1278define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1279; P9BE-LABEL: spltMemVali: 1280; P9BE: # %bb.0: # %entry 1281; P9BE-NEXT: lfiwzx f0, 0, r3 1282; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 1283; P9BE-NEXT: xxspltw v2, vs0, 0 1284; P9BE-NEXT: blr 1285; 1286; P9LE-LABEL: spltMemVali: 1287; P9LE: # %bb.0: # %entry 1288; P9LE-NEXT: lfiwzx f0, 0, r3 1289; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 1290; P9LE-NEXT: xxspltw v2, vs0, 3 1291; P9LE-NEXT: blr 1292; 1293; P8BE-LABEL: spltMemVali: 1294; P8BE: # %bb.0: # %entry 1295; P8BE-NEXT: lfiwzx f0, 0, r3 1296; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 1297; P8BE-NEXT: xxspltw v2, vs0, 0 1298; P8BE-NEXT: blr 1299; 1300; P8LE-LABEL: spltMemVali: 1301; P8LE: # %bb.0: # %entry 1302; P8LE-NEXT: lfiwzx f0, 0, r3 1303; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 1304; P8LE-NEXT: xxspltw v2, vs0, 3 1305; P8LE-NEXT: blr 1306entry: 1307 %0 = load i32, i32* %ptr, align 4 1308 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1309 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1310 ret <4 x i32> %splat.splat 1311} 1312 1313; Function Attrs: norecurse nounwind readnone 1314define <4 x i32> @spltCnstConvftoi() { 1315; P9BE-LABEL: spltCnstConvftoi: 1316; P9BE: # %bb.0: # %entry 1317; P9BE-NEXT: vspltisw v2, 4 1318; P9BE-NEXT: blr 1319; 1320; P9LE-LABEL: spltCnstConvftoi: 1321; P9LE: # %bb.0: # %entry 1322; P9LE-NEXT: vspltisw v2, 4 1323; P9LE-NEXT: blr 1324; 1325; P8BE-LABEL: spltCnstConvftoi: 1326; P8BE: # %bb.0: # %entry 1327; P8BE-NEXT: vspltisw v2, 4 1328; P8BE-NEXT: blr 1329; 1330; P8LE-LABEL: spltCnstConvftoi: 1331; P8LE: # %bb.0: # %entry 1332; P8LE-NEXT: vspltisw v2, 4 1333; P8LE-NEXT: blr 1334entry: 1335 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1336} 1337 1338; Function Attrs: norecurse nounwind readnone 1339define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1340; P9BE-LABEL: fromRegsConvftoi: 1341; P9BE: # %bb.0: # %entry 1342; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1343; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1344; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1345; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1346; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1347; P9BE-NEXT: xvcvdpsxws v2, vs0 1348; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1349; P9BE-NEXT: xvcvdpsxws v3, vs0 1350; P9BE-NEXT: vmrgew v2, v3, v2 1351; P9BE-NEXT: blr 1352; 1353; P9LE-LABEL: fromRegsConvftoi: 1354; P9LE: # %bb.0: # %entry 1355; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1356; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1357; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1358; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1359; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1360; P9LE-NEXT: xvcvdpsxws v2, vs0 1361; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1362; P9LE-NEXT: xvcvdpsxws v3, vs0 1363; P9LE-NEXT: vmrgew v2, v3, v2 1364; P9LE-NEXT: blr 1365; 1366; P8BE-LABEL: fromRegsConvftoi: 1367; P8BE: # %bb.0: # %entry 1368; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1369; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1370; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1371; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1372; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1373; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1374; P8BE-NEXT: xvcvdpsxws v2, vs0 1375; P8BE-NEXT: xvcvdpsxws v3, vs1 1376; P8BE-NEXT: vmrgew v2, v3, v2 1377; P8BE-NEXT: blr 1378; 1379; P8LE-LABEL: fromRegsConvftoi: 1380; P8LE: # %bb.0: # %entry 1381; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1382; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1383; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1384; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1385; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1386; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1387; P8LE-NEXT: xvcvdpsxws v2, vs0 1388; P8LE-NEXT: xvcvdpsxws v3, vs1 1389; P8LE-NEXT: vmrgew v2, v3, v2 1390; P8LE-NEXT: blr 1391entry: 1392 %conv = fptosi float %a to i32 1393 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1394 %conv1 = fptosi float %b to i32 1395 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1396 %conv3 = fptosi float %c to i32 1397 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1398 %conv5 = fptosi float %d to i32 1399 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1400 ret <4 x i32> %vecinit6 1401} 1402 1403; Function Attrs: norecurse nounwind readnone 1404define <4 x i32> @fromDiffConstsConvftoi() { 1405; P9BE-LABEL: fromDiffConstsConvftoi: 1406; P9BE: # %bb.0: # %entry 1407; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1408; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1409; P9BE-NEXT: lxvx v2, 0, r3 1410; P9BE-NEXT: blr 1411; 1412; P9LE-LABEL: fromDiffConstsConvftoi: 1413; P9LE: # %bb.0: # %entry 1414; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1415; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1416; P9LE-NEXT: lxvx v2, 0, r3 1417; P9LE-NEXT: blr 1418; 1419; P8BE-LABEL: fromDiffConstsConvftoi: 1420; P8BE: # %bb.0: # %entry 1421; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1422; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1423; P8BE-NEXT: lxvw4x v2, 0, r3 1424; P8BE-NEXT: blr 1425; 1426; P8LE-LABEL: fromDiffConstsConvftoi: 1427; P8LE: # %bb.0: # %entry 1428; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1429; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1430; P8LE-NEXT: lvx v2, 0, r3 1431; P8LE-NEXT: blr 1432entry: 1433 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1434} 1435 1436; Function Attrs: norecurse nounwind readonly 1437define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1438; P9BE-LABEL: fromDiffMemConsAConvftoi: 1439; P9BE: # %bb.0: # %entry 1440; P9BE-NEXT: lxv vs0, 0(r3) 1441; P9BE-NEXT: xvcvspsxws v2, vs0 1442; P9BE-NEXT: blr 1443; 1444; P9LE-LABEL: fromDiffMemConsAConvftoi: 1445; P9LE: # %bb.0: # %entry 1446; P9LE-NEXT: lxv vs0, 0(r3) 1447; P9LE-NEXT: xvcvspsxws v2, vs0 1448; P9LE-NEXT: blr 1449; 1450; P8BE-LABEL: fromDiffMemConsAConvftoi: 1451; P8BE: # %bb.0: # %entry 1452; P8BE-NEXT: lxvw4x vs0, 0, r3 1453; P8BE-NEXT: xvcvspsxws v2, vs0 1454; P8BE-NEXT: blr 1455; 1456; P8LE-LABEL: fromDiffMemConsAConvftoi: 1457; P8LE: # %bb.0: # %entry 1458; P8LE-NEXT: lxvd2x vs0, 0, r3 1459; P8LE-NEXT: xxswapd v2, vs0 1460; P8LE-NEXT: xvcvspsxws v2, v2 1461; P8LE-NEXT: blr 1462entry: 1463 %0 = bitcast float* %ptr to <4 x float>* 1464 %1 = load <4 x float>, <4 x float>* %0, align 4 1465 %2 = fptosi <4 x float> %1 to <4 x i32> 1466 ret <4 x i32> %2 1467} 1468 1469; Function Attrs: norecurse nounwind readonly 1470define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1471; P9BE-LABEL: fromDiffMemConsDConvftoi: 1472; P9BE: # %bb.0: # %entry 1473; P9BE-NEXT: lxv v2, 0(r3) 1474; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1475; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1476; P9BE-NEXT: lxvx v3, 0, r3 1477; P9BE-NEXT: vperm v2, v2, v2, v3 1478; P9BE-NEXT: xvcvspsxws v2, v2 1479; P9BE-NEXT: blr 1480; 1481; P9LE-LABEL: fromDiffMemConsDConvftoi: 1482; P9LE: # %bb.0: # %entry 1483; P9LE-NEXT: lxv v2, 0(r3) 1484; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1485; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1486; P9LE-NEXT: lxvx v3, 0, r3 1487; P9LE-NEXT: vperm v2, v2, v2, v3 1488; P9LE-NEXT: xvcvspsxws v2, v2 1489; P9LE-NEXT: blr 1490; 1491; P8BE-LABEL: fromDiffMemConsDConvftoi: 1492; P8BE: # %bb.0: # %entry 1493; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1494; P8BE-NEXT: lxvw4x v2, 0, r3 1495; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1496; P8BE-NEXT: lxvw4x v3, 0, r4 1497; P8BE-NEXT: vperm v2, v2, v2, v3 1498; P8BE-NEXT: xvcvspsxws v2, v2 1499; P8BE-NEXT: blr 1500; 1501; P8LE-LABEL: fromDiffMemConsDConvftoi: 1502; P8LE: # %bb.0: # %entry 1503; P8LE-NEXT: lxvd2x vs0, 0, r3 1504; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1505; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l 1506; P8LE-NEXT: lvx v2, 0, r3 1507; P8LE-NEXT: xxswapd v3, vs0 1508; P8LE-NEXT: vperm v2, v3, v3, v2 1509; P8LE-NEXT: xvcvspsxws v2, v2 1510; P8LE-NEXT: blr 1511entry: 1512 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1513 %0 = load float, float* %arrayidx, align 4 1514 %conv = fptosi float %0 to i32 1515 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1516 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1517 %1 = load float, float* %arrayidx1, align 4 1518 %conv2 = fptosi float %1 to i32 1519 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1520 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1521 %2 = load float, float* %arrayidx4, align 4 1522 %conv5 = fptosi float %2 to i32 1523 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1524 %3 = load float, float* %ptr, align 4 1525 %conv8 = fptosi float %3 to i32 1526 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1527 ret <4 x i32> %vecinit9 1528} 1529 1530; Function Attrs: norecurse nounwind readonly 1531define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1532; P9BE-LABEL: fromDiffMemVarAConvftoi: 1533; P9BE: # %bb.0: # %entry 1534; P9BE-NEXT: sldi r4, r4, 2 1535; P9BE-NEXT: lfsux f0, r3, r4 1536; P9BE-NEXT: lfs f1, 12(r3) 1537; P9BE-NEXT: lfs f2, 4(r3) 1538; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1539; P9BE-NEXT: xvcvdpsp v2, vs1 1540; P9BE-NEXT: lfs f1, 8(r3) 1541; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1542; P9BE-NEXT: xvcvdpsp v3, vs0 1543; P9BE-NEXT: vmrgew v2, v3, v2 1544; P9BE-NEXT: xvcvspsxws v2, v2 1545; P9BE-NEXT: blr 1546; 1547; P9LE-LABEL: fromDiffMemVarAConvftoi: 1548; P9LE: # %bb.0: # %entry 1549; P9LE-NEXT: sldi r4, r4, 2 1550; P9LE-NEXT: lfsux f0, r3, r4 1551; P9LE-NEXT: lfs f1, 8(r3) 1552; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1553; P9LE-NEXT: lfs f1, 12(r3) 1554; P9LE-NEXT: xvcvdpsp v2, vs0 1555; P9LE-NEXT: lfs f0, 4(r3) 1556; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1557; P9LE-NEXT: xvcvdpsp v3, vs0 1558; P9LE-NEXT: vmrgew v2, v3, v2 1559; P9LE-NEXT: xvcvspsxws v2, v2 1560; P9LE-NEXT: blr 1561; 1562; P8BE-LABEL: fromDiffMemVarAConvftoi: 1563; P8BE: # %bb.0: # %entry 1564; P8BE-NEXT: sldi r4, r4, 2 1565; P8BE-NEXT: lfsux f0, r3, r4 1566; P8BE-NEXT: lfs f1, 12(r3) 1567; P8BE-NEXT: lfs f2, 4(r3) 1568; P8BE-NEXT: lfs f3, 8(r3) 1569; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1570; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1571; P8BE-NEXT: xvcvdpsp v2, vs1 1572; P8BE-NEXT: xvcvdpsp v3, vs0 1573; P8BE-NEXT: vmrgew v2, v3, v2 1574; P8BE-NEXT: xvcvspsxws v2, v2 1575; P8BE-NEXT: blr 1576; 1577; P8LE-LABEL: fromDiffMemVarAConvftoi: 1578; P8LE: # %bb.0: # %entry 1579; P8LE-NEXT: sldi r4, r4, 2 1580; P8LE-NEXT: lfsux f0, r3, r4 1581; P8LE-NEXT: lfs f1, 8(r3) 1582; P8LE-NEXT: lfs f2, 4(r3) 1583; P8LE-NEXT: lfs f3, 12(r3) 1584; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1585; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1586; P8LE-NEXT: xvcvdpsp v2, vs0 1587; P8LE-NEXT: xvcvdpsp v3, vs1 1588; P8LE-NEXT: vmrgew v2, v3, v2 1589; P8LE-NEXT: xvcvspsxws v2, v2 1590; P8LE-NEXT: blr 1591entry: 1592 %idxprom = sext i32 %elem to i64 1593 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1594 %0 = load float, float* %arrayidx, align 4 1595 %conv = fptosi float %0 to i32 1596 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1597 %add = add nsw i32 %elem, 1 1598 %idxprom1 = sext i32 %add to i64 1599 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1600 %1 = load float, float* %arrayidx2, align 4 1601 %conv3 = fptosi float %1 to i32 1602 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1603 %add5 = add nsw i32 %elem, 2 1604 %idxprom6 = sext i32 %add5 to i64 1605 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1606 %2 = load float, float* %arrayidx7, align 4 1607 %conv8 = fptosi float %2 to i32 1608 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1609 %add10 = add nsw i32 %elem, 3 1610 %idxprom11 = sext i32 %add10 to i64 1611 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1612 %3 = load float, float* %arrayidx12, align 4 1613 %conv13 = fptosi float %3 to i32 1614 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1615 ret <4 x i32> %vecinit14 1616; FIXME: implement finding consecutive loads with pre-inc 1617} 1618 1619; Function Attrs: norecurse nounwind readonly 1620define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1621; P9BE-LABEL: fromDiffMemVarDConvftoi: 1622; P9BE: # %bb.0: # %entry 1623; P9BE-NEXT: sldi r4, r4, 2 1624; P9BE-NEXT: lfsux f0, r3, r4 1625; P9BE-NEXT: lfs f1, -12(r3) 1626; P9BE-NEXT: lfs f2, -4(r3) 1627; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1628; P9BE-NEXT: xvcvdpsp v2, vs1 1629; P9BE-NEXT: lfs f1, -8(r3) 1630; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1631; P9BE-NEXT: xvcvdpsp v3, vs0 1632; P9BE-NEXT: vmrgew v2, v3, v2 1633; P9BE-NEXT: xvcvspsxws v2, v2 1634; P9BE-NEXT: blr 1635; 1636; P9LE-LABEL: fromDiffMemVarDConvftoi: 1637; P9LE: # %bb.0: # %entry 1638; P9LE-NEXT: sldi r4, r4, 2 1639; P9LE-NEXT: lfsux f0, r3, r4 1640; P9LE-NEXT: lfs f1, -8(r3) 1641; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1642; P9LE-NEXT: lfs f1, -12(r3) 1643; P9LE-NEXT: xvcvdpsp v2, vs0 1644; P9LE-NEXT: lfs f0, -4(r3) 1645; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1646; P9LE-NEXT: xvcvdpsp v3, vs0 1647; P9LE-NEXT: vmrgew v2, v3, v2 1648; P9LE-NEXT: xvcvspsxws v2, v2 1649; P9LE-NEXT: blr 1650; 1651; P8BE-LABEL: fromDiffMemVarDConvftoi: 1652; P8BE: # %bb.0: # %entry 1653; P8BE-NEXT: sldi r4, r4, 2 1654; P8BE-NEXT: lfsux f0, r3, r4 1655; P8BE-NEXT: lfs f1, -12(r3) 1656; P8BE-NEXT: lfs f2, -4(r3) 1657; P8BE-NEXT: lfs f3, -8(r3) 1658; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1659; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1660; P8BE-NEXT: xvcvdpsp v2, vs1 1661; P8BE-NEXT: xvcvdpsp v3, vs0 1662; P8BE-NEXT: vmrgew v2, v3, v2 1663; P8BE-NEXT: xvcvspsxws v2, v2 1664; P8BE-NEXT: blr 1665; 1666; P8LE-LABEL: fromDiffMemVarDConvftoi: 1667; P8LE: # %bb.0: # %entry 1668; P8LE-NEXT: sldi r4, r4, 2 1669; P8LE-NEXT: lfsux f0, r3, r4 1670; P8LE-NEXT: lfs f1, -8(r3) 1671; P8LE-NEXT: lfs f2, -4(r3) 1672; P8LE-NEXT: lfs f3, -12(r3) 1673; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1674; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1675; P8LE-NEXT: xvcvdpsp v2, vs0 1676; P8LE-NEXT: xvcvdpsp v3, vs1 1677; P8LE-NEXT: vmrgew v2, v3, v2 1678; P8LE-NEXT: xvcvspsxws v2, v2 1679; P8LE-NEXT: blr 1680entry: 1681 %idxprom = sext i32 %elem to i64 1682 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1683 %0 = load float, float* %arrayidx, align 4 1684 %conv = fptosi float %0 to i32 1685 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1686 %sub = add nsw i32 %elem, -1 1687 %idxprom1 = sext i32 %sub to i64 1688 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1689 %1 = load float, float* %arrayidx2, align 4 1690 %conv3 = fptosi float %1 to i32 1691 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1692 %sub5 = add nsw i32 %elem, -2 1693 %idxprom6 = sext i32 %sub5 to i64 1694 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1695 %2 = load float, float* %arrayidx7, align 4 1696 %conv8 = fptosi float %2 to i32 1697 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1698 %sub10 = add nsw i32 %elem, -3 1699 %idxprom11 = sext i32 %sub10 to i64 1700 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1701 %3 = load float, float* %arrayidx12, align 4 1702 %conv13 = fptosi float %3 to i32 1703 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1704 ret <4 x i32> %vecinit14 1705; FIXME: implement finding consecutive loads with pre-inc 1706} 1707 1708; Function Attrs: norecurse nounwind readnone 1709define <4 x i32> @spltRegValConvftoi(float %val) { 1710; P9BE-LABEL: spltRegValConvftoi: 1711; P9BE: # %bb.0: # %entry 1712; P9BE-NEXT: xscvdpsxws f0, f1 1713; P9BE-NEXT: xxspltw v2, vs0, 1 1714; P9BE-NEXT: blr 1715; 1716; P9LE-LABEL: spltRegValConvftoi: 1717; P9LE: # %bb.0: # %entry 1718; P9LE-NEXT: xscvdpsxws f0, f1 1719; P9LE-NEXT: xxspltw v2, vs0, 1 1720; P9LE-NEXT: blr 1721; 1722; P8BE-LABEL: spltRegValConvftoi: 1723; P8BE: # %bb.0: # %entry 1724; P8BE-NEXT: xscvdpsxws f0, f1 1725; P8BE-NEXT: xxspltw v2, vs0, 1 1726; P8BE-NEXT: blr 1727; 1728; P8LE-LABEL: spltRegValConvftoi: 1729; P8LE: # %bb.0: # %entry 1730; P8LE-NEXT: xscvdpsxws f0, f1 1731; P8LE-NEXT: xxspltw v2, vs0, 1 1732; P8LE-NEXT: blr 1733entry: 1734 %conv = fptosi float %val to i32 1735 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1736 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1737 ret <4 x i32> %splat.splat 1738} 1739 1740; Function Attrs: norecurse nounwind readonly 1741define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1742; P9BE-LABEL: spltMemValConvftoi: 1743; P9BE: # %bb.0: # %entry 1744; P9BE-NEXT: lxvwsx vs0, 0, r3 1745; P9BE-NEXT: xvcvspsxws v2, vs0 1746; P9BE-NEXT: blr 1747; 1748; P9LE-LABEL: spltMemValConvftoi: 1749; P9LE: # %bb.0: # %entry 1750; P9LE-NEXT: lxvwsx vs0, 0, r3 1751; P9LE-NEXT: xvcvspsxws v2, vs0 1752; P9LE-NEXT: blr 1753; 1754; P8BE-LABEL: spltMemValConvftoi: 1755; P8BE: # %bb.0: # %entry 1756; P8BE-NEXT: lfsx f0, 0, r3 1757; P8BE-NEXT: xscvdpsxws f0, f0 1758; P8BE-NEXT: xxspltw v2, vs0, 1 1759; P8BE-NEXT: blr 1760; 1761; P8LE-LABEL: spltMemValConvftoi: 1762; P8LE: # %bb.0: # %entry 1763; P8LE-NEXT: lfsx f0, 0, r3 1764; P8LE-NEXT: xscvdpsxws f0, f0 1765; P8LE-NEXT: xxspltw v2, vs0, 1 1766; P8LE-NEXT: blr 1767entry: 1768 %0 = load float, float* %ptr, align 4 1769 %conv = fptosi float %0 to i32 1770 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1771 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1772 ret <4 x i32> %splat.splat 1773} 1774 1775; Function Attrs: norecurse nounwind readnone 1776define <4 x i32> @spltCnstConvdtoi() { 1777; P9BE-LABEL: spltCnstConvdtoi: 1778; P9BE: # %bb.0: # %entry 1779; P9BE-NEXT: vspltisw v2, 4 1780; P9BE-NEXT: blr 1781; 1782; P9LE-LABEL: spltCnstConvdtoi: 1783; P9LE: # %bb.0: # %entry 1784; P9LE-NEXT: vspltisw v2, 4 1785; P9LE-NEXT: blr 1786; 1787; P8BE-LABEL: spltCnstConvdtoi: 1788; P8BE: # %bb.0: # %entry 1789; P8BE-NEXT: vspltisw v2, 4 1790; P8BE-NEXT: blr 1791; 1792; P8LE-LABEL: spltCnstConvdtoi: 1793; P8LE: # %bb.0: # %entry 1794; P8LE-NEXT: vspltisw v2, 4 1795; P8LE-NEXT: blr 1796entry: 1797 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1798} 1799 1800; Function Attrs: norecurse nounwind readnone 1801define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1802; P9BE-LABEL: fromRegsConvdtoi: 1803; P9BE: # %bb.0: # %entry 1804; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1805; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1806; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1807; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1808; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1809; P9BE-NEXT: xvcvdpsxws v2, vs0 1810; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1811; P9BE-NEXT: xvcvdpsxws v3, vs0 1812; P9BE-NEXT: vmrgew v2, v3, v2 1813; P9BE-NEXT: blr 1814; 1815; P9LE-LABEL: fromRegsConvdtoi: 1816; P9LE: # %bb.0: # %entry 1817; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1818; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1819; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1820; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1821; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1822; P9LE-NEXT: xvcvdpsxws v2, vs0 1823; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1824; P9LE-NEXT: xvcvdpsxws v3, vs0 1825; P9LE-NEXT: vmrgew v2, v3, v2 1826; P9LE-NEXT: blr 1827; 1828; P8BE-LABEL: fromRegsConvdtoi: 1829; P8BE: # %bb.0: # %entry 1830; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1831; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1832; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1833; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1834; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1835; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1836; P8BE-NEXT: xvcvdpsxws v2, vs0 1837; P8BE-NEXT: xvcvdpsxws v3, vs1 1838; P8BE-NEXT: vmrgew v2, v3, v2 1839; P8BE-NEXT: blr 1840; 1841; P8LE-LABEL: fromRegsConvdtoi: 1842; P8LE: # %bb.0: # %entry 1843; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1844; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1845; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1846; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1847; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1848; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1849; P8LE-NEXT: xvcvdpsxws v2, vs0 1850; P8LE-NEXT: xvcvdpsxws v3, vs1 1851; P8LE-NEXT: vmrgew v2, v3, v2 1852; P8LE-NEXT: blr 1853entry: 1854 %conv = fptosi double %a to i32 1855 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1856 %conv1 = fptosi double %b to i32 1857 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1858 %conv3 = fptosi double %c to i32 1859 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1860 %conv5 = fptosi double %d to i32 1861 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1862 ret <4 x i32> %vecinit6 1863} 1864 1865; Function Attrs: norecurse nounwind readnone 1866define <4 x i32> @fromDiffConstsConvdtoi() { 1867; P9BE-LABEL: fromDiffConstsConvdtoi: 1868; P9BE: # %bb.0: # %entry 1869; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1870; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1871; P9BE-NEXT: lxvx v2, 0, r3 1872; P9BE-NEXT: blr 1873; 1874; P9LE-LABEL: fromDiffConstsConvdtoi: 1875; P9LE: # %bb.0: # %entry 1876; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1877; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1878; P9LE-NEXT: lxvx v2, 0, r3 1879; P9LE-NEXT: blr 1880; 1881; P8BE-LABEL: fromDiffConstsConvdtoi: 1882; P8BE: # %bb.0: # %entry 1883; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1884; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1885; P8BE-NEXT: lxvw4x v2, 0, r3 1886; P8BE-NEXT: blr 1887; 1888; P8LE-LABEL: fromDiffConstsConvdtoi: 1889; P8LE: # %bb.0: # %entry 1890; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1891; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1892; P8LE-NEXT: lvx v2, 0, r3 1893; P8LE-NEXT: blr 1894entry: 1895 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1896} 1897 1898; Function Attrs: norecurse nounwind readonly 1899define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1900; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1901; P9BE: # %bb.0: # %entry 1902; P9BE-NEXT: lxv vs0, 0(r3) 1903; P9BE-NEXT: lxv vs1, 16(r3) 1904; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1905; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1906; P9BE-NEXT: xvcvdpsxws v2, vs2 1907; P9BE-NEXT: xvcvdpsxws v3, vs0 1908; P9BE-NEXT: vmrgew v2, v3, v2 1909; P9BE-NEXT: blr 1910; 1911; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1912; P9LE: # %bb.0: # %entry 1913; P9LE-NEXT: lxv vs0, 0(r3) 1914; P9LE-NEXT: lxv vs1, 16(r3) 1915; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1916; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1917; P9LE-NEXT: xvcvdpsxws v2, vs2 1918; P9LE-NEXT: xvcvdpsxws v3, vs0 1919; P9LE-NEXT: vmrgew v2, v3, v2 1920; P9LE-NEXT: blr 1921; 1922; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1923; P8BE: # %bb.0: # %entry 1924; P8BE-NEXT: li r4, 16 1925; P8BE-NEXT: lxvd2x vs0, 0, r3 1926; P8BE-NEXT: lxvd2x vs1, r3, r4 1927; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1928; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1929; P8BE-NEXT: xvcvdpsxws v2, vs2 1930; P8BE-NEXT: xvcvdpsxws v3, vs0 1931; P8BE-NEXT: vmrgew v2, v3, v2 1932; P8BE-NEXT: blr 1933; 1934; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1935; P8LE: # %bb.0: # %entry 1936; P8LE-NEXT: li r4, 16 1937; P8LE-NEXT: lxvd2x vs0, 0, r3 1938; P8LE-NEXT: lxvd2x vs1, r3, r4 1939; P8LE-NEXT: xxswapd vs0, vs0 1940; P8LE-NEXT: xxswapd vs1, vs1 1941; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1942; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1943; P8LE-NEXT: xvcvdpsxws v2, vs2 1944; P8LE-NEXT: xvcvdpsxws v3, vs0 1945; P8LE-NEXT: vmrgew v2, v3, v2 1946; P8LE-NEXT: blr 1947entry: 1948 %0 = bitcast double* %ptr to <2 x double>* 1949 %1 = load <2 x double>, <2 x double>* %0, align 8 1950 %2 = fptosi <2 x double> %1 to <2 x i32> 1951 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1952 %3 = bitcast double* %arrayidx4 to <2 x double>* 1953 %4 = load <2 x double>, <2 x double>* %3, align 8 1954 %5 = fptosi <2 x double> %4 to <2 x i32> 1955 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1956 ret <4 x i32> %vecinit9 1957} 1958 1959; Function Attrs: norecurse nounwind readonly 1960define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1961; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1962; P9BE: # %bb.0: # %entry 1963; P9BE-NEXT: lfd f0, 24(r3) 1964; P9BE-NEXT: lfd f1, 16(r3) 1965; P9BE-NEXT: lfd f2, 8(r3) 1966; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1967; P9BE-NEXT: lfd f3, 0(r3) 1968; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1969; P9BE-NEXT: xvcvdpsxws v2, vs1 1970; P9BE-NEXT: xvcvdpsxws v3, vs0 1971; P9BE-NEXT: vmrgew v2, v3, v2 1972; P9BE-NEXT: blr 1973; 1974; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1975; P9LE: # %bb.0: # %entry 1976; P9LE-NEXT: lfd f0, 24(r3) 1977; P9LE-NEXT: lfd f2, 8(r3) 1978; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1979; P9LE-NEXT: lfd f1, 16(r3) 1980; P9LE-NEXT: lfd f3, 0(r3) 1981; P9LE-NEXT: xvcvdpsxws v2, vs0 1982; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1983; P9LE-NEXT: xvcvdpsxws v3, vs0 1984; P9LE-NEXT: vmrgew v2, v3, v2 1985; P9LE-NEXT: blr 1986; 1987; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1988; P8BE: # %bb.0: # %entry 1989; P8BE-NEXT: lfdx f3, 0, r3 1990; P8BE-NEXT: lfd f0, 24(r3) 1991; P8BE-NEXT: lfd f1, 8(r3) 1992; P8BE-NEXT: lfd f2, 16(r3) 1993; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1994; P8BE-NEXT: xxmrghd vs1, vs2, vs3 1995; P8BE-NEXT: xvcvdpsxws v2, vs0 1996; P8BE-NEXT: xvcvdpsxws v3, vs1 1997; P8BE-NEXT: vmrgew v2, v2, v3 1998; P8BE-NEXT: blr 1999; 2000; P8LE-LABEL: fromDiffMemConsDConvdtoi: 2001; P8LE: # %bb.0: # %entry 2002; P8LE-NEXT: lfdx f3, 0, r3 2003; P8LE-NEXT: lfd f0, 24(r3) 2004; P8LE-NEXT: lfd f1, 8(r3) 2005; P8LE-NEXT: lfd f2, 16(r3) 2006; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2007; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2008; P8LE-NEXT: xvcvdpsxws v2, vs0 2009; P8LE-NEXT: xvcvdpsxws v3, vs1 2010; P8LE-NEXT: vmrgew v2, v3, v2 2011; P8LE-NEXT: blr 2012entry: 2013 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2014 %0 = load double, double* %arrayidx, align 8 2015 %conv = fptosi double %0 to i32 2016 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2017 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2018 %1 = load double, double* %arrayidx1, align 8 2019 %conv2 = fptosi double %1 to i32 2020 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2021 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2022 %2 = load double, double* %arrayidx4, align 8 2023 %conv5 = fptosi double %2 to i32 2024 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2025 %3 = load double, double* %ptr, align 8 2026 %conv8 = fptosi double %3 to i32 2027 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2028 ret <4 x i32> %vecinit9 2029} 2030 2031; Function Attrs: norecurse nounwind readonly 2032define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2033; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2034; P9BE: # %bb.0: # %entry 2035; P9BE-NEXT: sldi r4, r4, 3 2036; P9BE-NEXT: lfdux f0, r3, r4 2037; P9BE-NEXT: lfd f1, 8(r3) 2038; P9BE-NEXT: lfd f2, 16(r3) 2039; P9BE-NEXT: lfd f3, 24(r3) 2040; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2041; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2042; P9BE-NEXT: xvcvdpsxws v2, vs1 2043; P9BE-NEXT: xvcvdpsxws v3, vs0 2044; P9BE-NEXT: vmrgew v2, v3, v2 2045; P9BE-NEXT: blr 2046; 2047; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2048; P9LE: # %bb.0: # %entry 2049; P9LE-NEXT: sldi r4, r4, 3 2050; P9LE-NEXT: lfdux f0, r3, r4 2051; P9LE-NEXT: lfd f2, 16(r3) 2052; P9LE-NEXT: lfd f1, 8(r3) 2053; P9LE-NEXT: lfd f3, 24(r3) 2054; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2055; P9LE-NEXT: xvcvdpsxws v2, vs0 2056; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2057; P9LE-NEXT: xvcvdpsxws v3, vs0 2058; P9LE-NEXT: vmrgew v2, v3, v2 2059; P9LE-NEXT: blr 2060; 2061; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2062; P8BE: # %bb.0: # %entry 2063; P8BE-NEXT: sldi r4, r4, 3 2064; P8BE-NEXT: lfdux f0, r3, r4 2065; P8BE-NEXT: lfd f1, 8(r3) 2066; P8BE-NEXT: lfd f2, 24(r3) 2067; P8BE-NEXT: lfd f3, 16(r3) 2068; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2069; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2070; P8BE-NEXT: xvcvdpsxws v2, vs1 2071; P8BE-NEXT: xvcvdpsxws v3, vs0 2072; P8BE-NEXT: vmrgew v2, v3, v2 2073; P8BE-NEXT: blr 2074; 2075; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2076; P8LE: # %bb.0: # %entry 2077; P8LE-NEXT: sldi r4, r4, 3 2078; P8LE-NEXT: lfdux f0, r3, r4 2079; P8LE-NEXT: lfd f1, 16(r3) 2080; P8LE-NEXT: lfd f2, 8(r3) 2081; P8LE-NEXT: lfd f3, 24(r3) 2082; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2083; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2084; P8LE-NEXT: xvcvdpsxws v2, vs0 2085; P8LE-NEXT: xvcvdpsxws v3, vs1 2086; P8LE-NEXT: vmrgew v2, v3, v2 2087; P8LE-NEXT: blr 2088entry: 2089 %idxprom = sext i32 %elem to i64 2090 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2091 %0 = load double, double* %arrayidx, align 8 2092 %conv = fptosi double %0 to i32 2093 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2094 %add = add nsw i32 %elem, 1 2095 %idxprom1 = sext i32 %add to i64 2096 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2097 %1 = load double, double* %arrayidx2, align 8 2098 %conv3 = fptosi double %1 to i32 2099 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2100 %add5 = add nsw i32 %elem, 2 2101 %idxprom6 = sext i32 %add5 to i64 2102 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2103 %2 = load double, double* %arrayidx7, align 8 2104 %conv8 = fptosi double %2 to i32 2105 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2106 %add10 = add nsw i32 %elem, 3 2107 %idxprom11 = sext i32 %add10 to i64 2108 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2109 %3 = load double, double* %arrayidx12, align 8 2110 %conv13 = fptosi double %3 to i32 2111 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2112 ret <4 x i32> %vecinit14 2113} 2114 2115; Function Attrs: norecurse nounwind readonly 2116define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2117; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2118; P9BE: # %bb.0: # %entry 2119; P9BE-NEXT: sldi r4, r4, 3 2120; P9BE-NEXT: lfdux f0, r3, r4 2121; P9BE-NEXT: lfd f1, -8(r3) 2122; P9BE-NEXT: lfd f2, -16(r3) 2123; P9BE-NEXT: lfd f3, -24(r3) 2124; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2125; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2126; P9BE-NEXT: xvcvdpsxws v2, vs1 2127; P9BE-NEXT: xvcvdpsxws v3, vs0 2128; P9BE-NEXT: vmrgew v2, v3, v2 2129; P9BE-NEXT: blr 2130; 2131; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2132; P9LE: # %bb.0: # %entry 2133; P9LE-NEXT: sldi r4, r4, 3 2134; P9LE-NEXT: lfdux f0, r3, r4 2135; P9LE-NEXT: lfd f2, -16(r3) 2136; P9LE-NEXT: lfd f1, -8(r3) 2137; P9LE-NEXT: lfd f3, -24(r3) 2138; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2139; P9LE-NEXT: xvcvdpsxws v2, vs0 2140; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2141; P9LE-NEXT: xvcvdpsxws v3, vs0 2142; P9LE-NEXT: vmrgew v2, v3, v2 2143; P9LE-NEXT: blr 2144; 2145; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2146; P8BE: # %bb.0: # %entry 2147; P8BE-NEXT: sldi r4, r4, 3 2148; P8BE-NEXT: lfdux f0, r3, r4 2149; P8BE-NEXT: lfd f1, -8(r3) 2150; P8BE-NEXT: lfd f2, -24(r3) 2151; P8BE-NEXT: lfd f3, -16(r3) 2152; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2153; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2154; P8BE-NEXT: xvcvdpsxws v2, vs1 2155; P8BE-NEXT: xvcvdpsxws v3, vs0 2156; P8BE-NEXT: vmrgew v2, v3, v2 2157; P8BE-NEXT: blr 2158; 2159; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2160; P8LE: # %bb.0: # %entry 2161; P8LE-NEXT: sldi r4, r4, 3 2162; P8LE-NEXT: lfdux f0, r3, r4 2163; P8LE-NEXT: lfd f1, -16(r3) 2164; P8LE-NEXT: lfd f2, -8(r3) 2165; P8LE-NEXT: lfd f3, -24(r3) 2166; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2167; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2168; P8LE-NEXT: xvcvdpsxws v2, vs0 2169; P8LE-NEXT: xvcvdpsxws v3, vs1 2170; P8LE-NEXT: vmrgew v2, v3, v2 2171; P8LE-NEXT: blr 2172entry: 2173 %idxprom = sext i32 %elem to i64 2174 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2175 %0 = load double, double* %arrayidx, align 8 2176 %conv = fptosi double %0 to i32 2177 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2178 %sub = add nsw i32 %elem, -1 2179 %idxprom1 = sext i32 %sub to i64 2180 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2181 %1 = load double, double* %arrayidx2, align 8 2182 %conv3 = fptosi double %1 to i32 2183 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2184 %sub5 = add nsw i32 %elem, -2 2185 %idxprom6 = sext i32 %sub5 to i64 2186 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2187 %2 = load double, double* %arrayidx7, align 8 2188 %conv8 = fptosi double %2 to i32 2189 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2190 %sub10 = add nsw i32 %elem, -3 2191 %idxprom11 = sext i32 %sub10 to i64 2192 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2193 %3 = load double, double* %arrayidx12, align 8 2194 %conv13 = fptosi double %3 to i32 2195 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2196 ret <4 x i32> %vecinit14 2197} 2198 2199; Function Attrs: norecurse nounwind readnone 2200define <4 x i32> @spltRegValConvdtoi(double %val) { 2201; P9BE-LABEL: spltRegValConvdtoi: 2202; P9BE: # %bb.0: # %entry 2203; P9BE-NEXT: xscvdpsxws f0, f1 2204; P9BE-NEXT: xxspltw v2, vs0, 1 2205; P9BE-NEXT: blr 2206; 2207; P9LE-LABEL: spltRegValConvdtoi: 2208; P9LE: # %bb.0: # %entry 2209; P9LE-NEXT: xscvdpsxws f0, f1 2210; P9LE-NEXT: xxspltw v2, vs0, 1 2211; P9LE-NEXT: blr 2212; 2213; P8BE-LABEL: spltRegValConvdtoi: 2214; P8BE: # %bb.0: # %entry 2215; P8BE-NEXT: xscvdpsxws f0, f1 2216; P8BE-NEXT: xxspltw v2, vs0, 1 2217; P8BE-NEXT: blr 2218; 2219; P8LE-LABEL: spltRegValConvdtoi: 2220; P8LE: # %bb.0: # %entry 2221; P8LE-NEXT: xscvdpsxws f0, f1 2222; P8LE-NEXT: xxspltw v2, vs0, 1 2223; P8LE-NEXT: blr 2224entry: 2225 %conv = fptosi double %val to i32 2226 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2227 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2228 ret <4 x i32> %splat.splat 2229} 2230 2231; Function Attrs: norecurse nounwind readonly 2232define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2233; P9BE-LABEL: spltMemValConvdtoi: 2234; P9BE: # %bb.0: # %entry 2235; P9BE-NEXT: lfd f0, 0(r3) 2236; P9BE-NEXT: xscvdpsxws f0, f0 2237; P9BE-NEXT: xxspltw v2, vs0, 1 2238; P9BE-NEXT: blr 2239; 2240; P9LE-LABEL: spltMemValConvdtoi: 2241; P9LE: # %bb.0: # %entry 2242; P9LE-NEXT: lfd f0, 0(r3) 2243; P9LE-NEXT: xscvdpsxws f0, f0 2244; P9LE-NEXT: xxspltw v2, vs0, 1 2245; P9LE-NEXT: blr 2246; 2247; P8BE-LABEL: spltMemValConvdtoi: 2248; P8BE: # %bb.0: # %entry 2249; P8BE-NEXT: lfdx f0, 0, r3 2250; P8BE-NEXT: xscvdpsxws f0, f0 2251; P8BE-NEXT: xxspltw v2, vs0, 1 2252; P8BE-NEXT: blr 2253; 2254; P8LE-LABEL: spltMemValConvdtoi: 2255; P8LE: # %bb.0: # %entry 2256; P8LE-NEXT: lfdx f0, 0, r3 2257; P8LE-NEXT: xscvdpsxws f0, f0 2258; P8LE-NEXT: xxspltw v2, vs0, 1 2259; P8LE-NEXT: blr 2260entry: 2261 %0 = load double, double* %ptr, align 8 2262 %conv = fptosi double %0 to i32 2263 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2264 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2265 ret <4 x i32> %splat.splat 2266} 2267; Function Attrs: norecurse nounwind readnone 2268define <4 x i32> @allZeroui() { 2269; P9BE-LABEL: allZeroui: 2270; P9BE: # %bb.0: # %entry 2271; P9BE-NEXT: xxlxor v2, v2, v2 2272; P9BE-NEXT: blr 2273; 2274; P9LE-LABEL: allZeroui: 2275; P9LE: # %bb.0: # %entry 2276; P9LE-NEXT: xxlxor v2, v2, v2 2277; P9LE-NEXT: blr 2278; 2279; P8BE-LABEL: allZeroui: 2280; P8BE: # %bb.0: # %entry 2281; P8BE-NEXT: xxlxor v2, v2, v2 2282; P8BE-NEXT: blr 2283; 2284; P8LE-LABEL: allZeroui: 2285; P8LE: # %bb.0: # %entry 2286; P8LE-NEXT: xxlxor v2, v2, v2 2287; P8LE-NEXT: blr 2288entry: 2289 ret <4 x i32> zeroinitializer 2290} 2291 2292; Function Attrs: norecurse nounwind readnone 2293define <4 x i32> @spltConst1ui() { 2294; P9BE-LABEL: spltConst1ui: 2295; P9BE: # %bb.0: # %entry 2296; P9BE-NEXT: vspltisw v2, 1 2297; P9BE-NEXT: blr 2298; 2299; P9LE-LABEL: spltConst1ui: 2300; P9LE: # %bb.0: # %entry 2301; P9LE-NEXT: vspltisw v2, 1 2302; P9LE-NEXT: blr 2303; 2304; P8BE-LABEL: spltConst1ui: 2305; P8BE: # %bb.0: # %entry 2306; P8BE-NEXT: vspltisw v2, 1 2307; P8BE-NEXT: blr 2308; 2309; P8LE-LABEL: spltConst1ui: 2310; P8LE: # %bb.0: # %entry 2311; P8LE-NEXT: vspltisw v2, 1 2312; P8LE-NEXT: blr 2313entry: 2314 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2315} 2316 2317; Function Attrs: norecurse nounwind readnone 2318define <4 x i32> @spltConst16kui() { 2319; P9BE-LABEL: spltConst16kui: 2320; P9BE: # %bb.0: # %entry 2321; P9BE-NEXT: vspltisw v2, -15 2322; P9BE-NEXT: vsrw v2, v2, v2 2323; P9BE-NEXT: blr 2324; 2325; P9LE-LABEL: spltConst16kui: 2326; P9LE: # %bb.0: # %entry 2327; P9LE-NEXT: vspltisw v2, -15 2328; P9LE-NEXT: vsrw v2, v2, v2 2329; P9LE-NEXT: blr 2330; 2331; P8BE-LABEL: spltConst16kui: 2332; P8BE: # %bb.0: # %entry 2333; P8BE-NEXT: vspltisw v2, -15 2334; P8BE-NEXT: vsrw v2, v2, v2 2335; P8BE-NEXT: blr 2336; 2337; P8LE-LABEL: spltConst16kui: 2338; P8LE: # %bb.0: # %entry 2339; P8LE-NEXT: vspltisw v2, -15 2340; P8LE-NEXT: vsrw v2, v2, v2 2341; P8LE-NEXT: blr 2342entry: 2343 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2344} 2345 2346; Function Attrs: norecurse nounwind readnone 2347define <4 x i32> @spltConst32kui() { 2348; P9BE-LABEL: spltConst32kui: 2349; P9BE: # %bb.0: # %entry 2350; P9BE-NEXT: vspltisw v2, -16 2351; P9BE-NEXT: vsrw v2, v2, v2 2352; P9BE-NEXT: blr 2353; 2354; P9LE-LABEL: spltConst32kui: 2355; P9LE: # %bb.0: # %entry 2356; P9LE-NEXT: vspltisw v2, -16 2357; P9LE-NEXT: vsrw v2, v2, v2 2358; P9LE-NEXT: blr 2359; 2360; P8BE-LABEL: spltConst32kui: 2361; P8BE: # %bb.0: # %entry 2362; P8BE-NEXT: vspltisw v2, -16 2363; P8BE-NEXT: vsrw v2, v2, v2 2364; P8BE-NEXT: blr 2365; 2366; P8LE-LABEL: spltConst32kui: 2367; P8LE: # %bb.0: # %entry 2368; P8LE-NEXT: vspltisw v2, -16 2369; P8LE-NEXT: vsrw v2, v2, v2 2370; P8LE-NEXT: blr 2371entry: 2372 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2373} 2374 2375; Function Attrs: norecurse nounwind readnone 2376define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2377; P9BE-LABEL: fromRegsui: 2378; P9BE: # %bb.0: # %entry 2379; P9BE-NEXT: rldimi r6, r5, 32, 0 2380; P9BE-NEXT: rldimi r4, r3, 32, 0 2381; P9BE-NEXT: mtvsrdd v2, r4, r6 2382; P9BE-NEXT: blr 2383; 2384; P9LE-LABEL: fromRegsui: 2385; P9LE: # %bb.0: # %entry 2386; P9LE-NEXT: rldimi r3, r4, 32, 0 2387; P9LE-NEXT: rldimi r5, r6, 32, 0 2388; P9LE-NEXT: mtvsrdd v2, r5, r3 2389; P9LE-NEXT: blr 2390; 2391; P8BE-LABEL: fromRegsui: 2392; P8BE: # %bb.0: # %entry 2393; P8BE-NEXT: rldimi r6, r5, 32, 0 2394; P8BE-NEXT: rldimi r4, r3, 32, 0 2395; P8BE-NEXT: mtvsrd f0, r6 2396; P8BE-NEXT: mtvsrd f1, r4 2397; P8BE-NEXT: xxmrghd v2, vs1, vs0 2398; P8BE-NEXT: blr 2399; 2400; P8LE-LABEL: fromRegsui: 2401; P8LE: # %bb.0: # %entry 2402; P8LE-NEXT: rldimi r3, r4, 32, 0 2403; P8LE-NEXT: rldimi r5, r6, 32, 0 2404; P8LE-NEXT: mtvsrd f0, r3 2405; P8LE-NEXT: mtvsrd f1, r5 2406; P8LE-NEXT: xxmrghd v2, vs1, vs0 2407; P8LE-NEXT: blr 2408entry: 2409 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2410 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2411 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2412 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2413 ret <4 x i32> %vecinit3 2414} 2415 2416; Function Attrs: norecurse nounwind readnone 2417define <4 x i32> @fromDiffConstsui() { 2418; P9BE-LABEL: fromDiffConstsui: 2419; P9BE: # %bb.0: # %entry 2420; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2421; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2422; P9BE-NEXT: lxvx v2, 0, r3 2423; P9BE-NEXT: blr 2424; 2425; P9LE-LABEL: fromDiffConstsui: 2426; P9LE: # %bb.0: # %entry 2427; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2428; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2429; P9LE-NEXT: lxvx v2, 0, r3 2430; P9LE-NEXT: blr 2431; 2432; P8BE-LABEL: fromDiffConstsui: 2433; P8BE: # %bb.0: # %entry 2434; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2435; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2436; P8BE-NEXT: lxvw4x v2, 0, r3 2437; P8BE-NEXT: blr 2438; 2439; P8LE-LABEL: fromDiffConstsui: 2440; P8LE: # %bb.0: # %entry 2441; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2442; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2443; P8LE-NEXT: lvx v2, 0, r3 2444; P8LE-NEXT: blr 2445entry: 2446 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2447} 2448 2449; Function Attrs: norecurse nounwind readonly 2450define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2451; P9BE-LABEL: fromDiffMemConsAui: 2452; P9BE: # %bb.0: # %entry 2453; P9BE-NEXT: lxv v2, 0(r3) 2454; P9BE-NEXT: blr 2455; 2456; P9LE-LABEL: fromDiffMemConsAui: 2457; P9LE: # %bb.0: # %entry 2458; P9LE-NEXT: lxv v2, 0(r3) 2459; P9LE-NEXT: blr 2460; 2461; P8BE-LABEL: fromDiffMemConsAui: 2462; P8BE: # %bb.0: # %entry 2463; P8BE-NEXT: lxvw4x v2, 0, r3 2464; P8BE-NEXT: blr 2465; 2466; P8LE-LABEL: fromDiffMemConsAui: 2467; P8LE: # %bb.0: # %entry 2468; P8LE-NEXT: lxvd2x vs0, 0, r3 2469; P8LE-NEXT: xxswapd v2, vs0 2470; P8LE-NEXT: blr 2471entry: 2472 %0 = load i32, i32* %arr, align 4 2473 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2474 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2475 %1 = load i32, i32* %arrayidx1, align 4 2476 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2477 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2478 %2 = load i32, i32* %arrayidx3, align 4 2479 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2480 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2481 %3 = load i32, i32* %arrayidx5, align 4 2482 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2483 ret <4 x i32> %vecinit6 2484} 2485 2486; Function Attrs: norecurse nounwind readonly 2487define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2488; P9BE-LABEL: fromDiffMemConsDui: 2489; P9BE: # %bb.0: # %entry 2490; P9BE-NEXT: lxv v2, 0(r3) 2491; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2492; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2493; P9BE-NEXT: lxvx v3, 0, r3 2494; P9BE-NEXT: vperm v2, v2, v2, v3 2495; P9BE-NEXT: blr 2496; 2497; P9LE-LABEL: fromDiffMemConsDui: 2498; P9LE: # %bb.0: # %entry 2499; P9LE-NEXT: lxvw4x v2, 0, r3 2500; P9LE-NEXT: blr 2501; 2502; P8BE-LABEL: fromDiffMemConsDui: 2503; P8BE: # %bb.0: # %entry 2504; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2505; P8BE-NEXT: lxvw4x v2, 0, r3 2506; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2507; P8BE-NEXT: lxvw4x v3, 0, r4 2508; P8BE-NEXT: vperm v2, v2, v2, v3 2509; P8BE-NEXT: blr 2510; 2511; P8LE-LABEL: fromDiffMemConsDui: 2512; P8LE: # %bb.0: # %entry 2513; P8LE-NEXT: lxvd2x vs0, 0, r3 2514; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2515; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l 2516; P8LE-NEXT: lvx v2, 0, r3 2517; P8LE-NEXT: xxswapd v3, vs0 2518; P8LE-NEXT: vperm v2, v3, v3, v2 2519; P8LE-NEXT: blr 2520entry: 2521 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2522 %0 = load i32, i32* %arrayidx, align 4 2523 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2524 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2525 %1 = load i32, i32* %arrayidx1, align 4 2526 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2527 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2528 %2 = load i32, i32* %arrayidx3, align 4 2529 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2530 %3 = load i32, i32* %arr, align 4 2531 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2532 ret <4 x i32> %vecinit6 2533} 2534 2535; Function Attrs: norecurse nounwind readonly 2536define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2537; P9BE-LABEL: fromDiffMemVarAui: 2538; P9BE: # %bb.0: # %entry 2539; P9BE-NEXT: sldi r4, r4, 2 2540; P9BE-NEXT: lxvx v2, r3, r4 2541; P9BE-NEXT: blr 2542; 2543; P9LE-LABEL: fromDiffMemVarAui: 2544; P9LE: # %bb.0: # %entry 2545; P9LE-NEXT: sldi r4, r4, 2 2546; P9LE-NEXT: lxvx v2, r3, r4 2547; P9LE-NEXT: blr 2548; 2549; P8BE-LABEL: fromDiffMemVarAui: 2550; P8BE: # %bb.0: # %entry 2551; P8BE-NEXT: sldi r4, r4, 2 2552; P8BE-NEXT: lxvw4x v2, r3, r4 2553; P8BE-NEXT: blr 2554; 2555; P8LE-LABEL: fromDiffMemVarAui: 2556; P8LE: # %bb.0: # %entry 2557; P8LE-NEXT: sldi r4, r4, 2 2558; P8LE-NEXT: lxvd2x vs0, r3, r4 2559; P8LE-NEXT: xxswapd v2, vs0 2560; P8LE-NEXT: blr 2561entry: 2562 %idxprom = sext i32 %elem to i64 2563 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2564 %0 = load i32, i32* %arrayidx, align 4 2565 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2566 %add = add nsw i32 %elem, 1 2567 %idxprom1 = sext i32 %add to i64 2568 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2569 %1 = load i32, i32* %arrayidx2, align 4 2570 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2571 %add4 = add nsw i32 %elem, 2 2572 %idxprom5 = sext i32 %add4 to i64 2573 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2574 %2 = load i32, i32* %arrayidx6, align 4 2575 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2576 %add8 = add nsw i32 %elem, 3 2577 %idxprom9 = sext i32 %add8 to i64 2578 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2579 %3 = load i32, i32* %arrayidx10, align 4 2580 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2581 ret <4 x i32> %vecinit11 2582} 2583 2584; Function Attrs: norecurse nounwind readonly 2585define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2586; P9BE-LABEL: fromDiffMemVarDui: 2587; P9BE: # %bb.0: # %entry 2588; P9BE-NEXT: sldi r4, r4, 2 2589; P9BE-NEXT: add r3, r3, r4 2590; P9BE-NEXT: addi r3, r3, -12 2591; P9BE-NEXT: lxvx v2, 0, r3 2592; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2593; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2594; P9BE-NEXT: lxvx v3, 0, r3 2595; P9BE-NEXT: vperm v2, v2, v2, v3 2596; P9BE-NEXT: blr 2597; 2598; P9LE-LABEL: fromDiffMemVarDui: 2599; P9LE: # %bb.0: # %entry 2600; P9LE-NEXT: sldi r4, r4, 2 2601; P9LE-NEXT: add r3, r3, r4 2602; P9LE-NEXT: addi r3, r3, -12 2603; P9LE-NEXT: lxvx v2, 0, r3 2604; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2605; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2606; P9LE-NEXT: lxvx v3, 0, r3 2607; P9LE-NEXT: vperm v2, v2, v2, v3 2608; P9LE-NEXT: blr 2609; 2610; P8BE-LABEL: fromDiffMemVarDui: 2611; P8BE: # %bb.0: # %entry 2612; P8BE-NEXT: sldi r4, r4, 2 2613; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2614; P8BE-NEXT: add r3, r3, r4 2615; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2616; P8BE-NEXT: addi r3, r3, -12 2617; P8BE-NEXT: lxvw4x v3, 0, r4 2618; P8BE-NEXT: lxvw4x v2, 0, r3 2619; P8BE-NEXT: vperm v2, v2, v2, v3 2620; P8BE-NEXT: blr 2621; 2622; P8LE-LABEL: fromDiffMemVarDui: 2623; P8LE: # %bb.0: # %entry 2624; P8LE-NEXT: sldi r4, r4, 2 2625; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2626; P8LE-NEXT: add r3, r3, r4 2627; P8LE-NEXT: addi r3, r3, -12 2628; P8LE-NEXT: lxvd2x vs0, 0, r3 2629; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l 2630; P8LE-NEXT: lvx v3, 0, r3 2631; P8LE-NEXT: xxswapd v2, vs0 2632; P8LE-NEXT: vperm v2, v2, v2, v3 2633; P8LE-NEXT: blr 2634entry: 2635 %idxprom = sext i32 %elem to i64 2636 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2637 %0 = load i32, i32* %arrayidx, align 4 2638 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2639 %sub = add nsw i32 %elem, -1 2640 %idxprom1 = sext i32 %sub to i64 2641 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2642 %1 = load i32, i32* %arrayidx2, align 4 2643 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2644 %sub4 = add nsw i32 %elem, -2 2645 %idxprom5 = sext i32 %sub4 to i64 2646 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2647 %2 = load i32, i32* %arrayidx6, align 4 2648 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2649 %sub8 = add nsw i32 %elem, -3 2650 %idxprom9 = sext i32 %sub8 to i64 2651 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2652 %3 = load i32, i32* %arrayidx10, align 4 2653 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2654 ret <4 x i32> %vecinit11 2655} 2656 2657; Function Attrs: norecurse nounwind readonly 2658define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2659; P9BE-LABEL: fromRandMemConsui: 2660; P9BE: # %bb.0: # %entry 2661; P9BE-NEXT: lwz r4, 16(r3) 2662; P9BE-NEXT: lwz r5, 72(r3) 2663; P9BE-NEXT: lwz r6, 8(r3) 2664; P9BE-NEXT: lwz r3, 352(r3) 2665; P9BE-NEXT: rldimi r3, r6, 32, 0 2666; P9BE-NEXT: rldimi r5, r4, 32, 0 2667; P9BE-NEXT: mtvsrdd v2, r5, r3 2668; P9BE-NEXT: blr 2669; 2670; P9LE-LABEL: fromRandMemConsui: 2671; P9LE: # %bb.0: # %entry 2672; P9LE-NEXT: lwz r4, 16(r3) 2673; P9LE-NEXT: lwz r5, 72(r3) 2674; P9LE-NEXT: lwz r6, 8(r3) 2675; P9LE-NEXT: lwz r3, 352(r3) 2676; P9LE-NEXT: rldimi r4, r5, 32, 0 2677; P9LE-NEXT: rldimi r6, r3, 32, 0 2678; P9LE-NEXT: mtvsrdd v2, r6, r4 2679; P9LE-NEXT: blr 2680; 2681; P8BE-LABEL: fromRandMemConsui: 2682; P8BE: # %bb.0: # %entry 2683; P8BE-NEXT: lwz r4, 8(r3) 2684; P8BE-NEXT: lwz r5, 352(r3) 2685; P8BE-NEXT: lwz r6, 16(r3) 2686; P8BE-NEXT: lwz r3, 72(r3) 2687; P8BE-NEXT: rldimi r5, r4, 32, 0 2688; P8BE-NEXT: rldimi r3, r6, 32, 0 2689; P8BE-NEXT: mtvsrd f0, r5 2690; P8BE-NEXT: mtvsrd f1, r3 2691; P8BE-NEXT: xxmrghd v2, vs1, vs0 2692; P8BE-NEXT: blr 2693; 2694; P8LE-LABEL: fromRandMemConsui: 2695; P8LE: # %bb.0: # %entry 2696; P8LE-NEXT: lwz r4, 16(r3) 2697; P8LE-NEXT: lwz r5, 72(r3) 2698; P8LE-NEXT: lwz r6, 8(r3) 2699; P8LE-NEXT: lwz r3, 352(r3) 2700; P8LE-NEXT: rldimi r4, r5, 32, 0 2701; P8LE-NEXT: rldimi r6, r3, 32, 0 2702; P8LE-NEXT: mtvsrd f0, r4 2703; P8LE-NEXT: mtvsrd f1, r6 2704; P8LE-NEXT: xxmrghd v2, vs1, vs0 2705; P8LE-NEXT: blr 2706entry: 2707 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2708 %0 = load i32, i32* %arrayidx, align 4 2709 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2710 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2711 %1 = load i32, i32* %arrayidx1, align 4 2712 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2713 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2714 %2 = load i32, i32* %arrayidx3, align 4 2715 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2716 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2717 %3 = load i32, i32* %arrayidx5, align 4 2718 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2719 ret <4 x i32> %vecinit6 2720} 2721 2722; Function Attrs: norecurse nounwind readonly 2723define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2724; P9BE-LABEL: fromRandMemVarui: 2725; P9BE: # %bb.0: # %entry 2726; P9BE-NEXT: sldi r4, r4, 2 2727; P9BE-NEXT: add r3, r3, r4 2728; P9BE-NEXT: lwz r4, 16(r3) 2729; P9BE-NEXT: lwz r5, 4(r3) 2730; P9BE-NEXT: lwz r6, 8(r3) 2731; P9BE-NEXT: lwz r3, 32(r3) 2732; P9BE-NEXT: rldimi r3, r6, 32, 0 2733; P9BE-NEXT: rldimi r5, r4, 32, 0 2734; P9BE-NEXT: mtvsrdd v2, r5, r3 2735; P9BE-NEXT: blr 2736; 2737; P9LE-LABEL: fromRandMemVarui: 2738; P9LE: # %bb.0: # %entry 2739; P9LE-NEXT: sldi r4, r4, 2 2740; P9LE-NEXT: add r3, r3, r4 2741; P9LE-NEXT: lwz r4, 16(r3) 2742; P9LE-NEXT: lwz r5, 4(r3) 2743; P9LE-NEXT: lwz r6, 8(r3) 2744; P9LE-NEXT: lwz r3, 32(r3) 2745; P9LE-NEXT: rldimi r4, r5, 32, 0 2746; P9LE-NEXT: rldimi r6, r3, 32, 0 2747; P9LE-NEXT: mtvsrdd v2, r6, r4 2748; P9LE-NEXT: blr 2749; 2750; P8BE-LABEL: fromRandMemVarui: 2751; P8BE: # %bb.0: # %entry 2752; P8BE-NEXT: sldi r4, r4, 2 2753; P8BE-NEXT: add r3, r3, r4 2754; P8BE-NEXT: lwz r4, 8(r3) 2755; P8BE-NEXT: lwz r5, 32(r3) 2756; P8BE-NEXT: lwz r6, 16(r3) 2757; P8BE-NEXT: lwz r3, 4(r3) 2758; P8BE-NEXT: rldimi r5, r4, 32, 0 2759; P8BE-NEXT: rldimi r3, r6, 32, 0 2760; P8BE-NEXT: mtvsrd f0, r5 2761; P8BE-NEXT: mtvsrd f1, r3 2762; P8BE-NEXT: xxmrghd v2, vs1, vs0 2763; P8BE-NEXT: blr 2764; 2765; P8LE-LABEL: fromRandMemVarui: 2766; P8LE: # %bb.0: # %entry 2767; P8LE-NEXT: sldi r4, r4, 2 2768; P8LE-NEXT: add r3, r3, r4 2769; P8LE-NEXT: lwz r4, 16(r3) 2770; P8LE-NEXT: lwz r5, 4(r3) 2771; P8LE-NEXT: lwz r6, 8(r3) 2772; P8LE-NEXT: lwz r3, 32(r3) 2773; P8LE-NEXT: rldimi r4, r5, 32, 0 2774; P8LE-NEXT: rldimi r6, r3, 32, 0 2775; P8LE-NEXT: mtvsrd f0, r4 2776; P8LE-NEXT: mtvsrd f1, r6 2777; P8LE-NEXT: xxmrghd v2, vs1, vs0 2778; P8LE-NEXT: blr 2779entry: 2780 %add = add nsw i32 %elem, 4 2781 %idxprom = sext i32 %add to i64 2782 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2783 %0 = load i32, i32* %arrayidx, align 4 2784 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2785 %add1 = add nsw i32 %elem, 1 2786 %idxprom2 = sext i32 %add1 to i64 2787 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2788 %1 = load i32, i32* %arrayidx3, align 4 2789 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2790 %add5 = add nsw i32 %elem, 2 2791 %idxprom6 = sext i32 %add5 to i64 2792 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2793 %2 = load i32, i32* %arrayidx7, align 4 2794 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2795 %add9 = add nsw i32 %elem, 8 2796 %idxprom10 = sext i32 %add9 to i64 2797 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2798 %3 = load i32, i32* %arrayidx11, align 4 2799 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2800 ret <4 x i32> %vecinit12 2801} 2802 2803; Function Attrs: norecurse nounwind readnone 2804define <4 x i32> @spltRegValui(i32 zeroext %val) { 2805; P9BE-LABEL: spltRegValui: 2806; P9BE: # %bb.0: # %entry 2807; P9BE-NEXT: mtvsrws v2, r3 2808; P9BE-NEXT: blr 2809; 2810; P9LE-LABEL: spltRegValui: 2811; P9LE: # %bb.0: # %entry 2812; P9LE-NEXT: mtvsrws v2, r3 2813; P9LE-NEXT: blr 2814; 2815; P8BE-LABEL: spltRegValui: 2816; P8BE: # %bb.0: # %entry 2817; P8BE-NEXT: mtvsrwz f0, r3 2818; P8BE-NEXT: xxspltw v2, vs0, 1 2819; P8BE-NEXT: blr 2820; 2821; P8LE-LABEL: spltRegValui: 2822; P8LE: # %bb.0: # %entry 2823; P8LE-NEXT: mtvsrwz f0, r3 2824; P8LE-NEXT: xxspltw v2, vs0, 1 2825; P8LE-NEXT: blr 2826entry: 2827 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2828 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2829 ret <4 x i32> %splat.splat 2830} 2831 2832; Function Attrs: norecurse nounwind readonly 2833define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2834; P9BE-LABEL: spltMemValui: 2835; P9BE: # %bb.0: # %entry 2836; P9BE-NEXT: lfiwzx f0, 0, r3 2837; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 2838; P9BE-NEXT: xxspltw v2, vs0, 0 2839; P9BE-NEXT: blr 2840; 2841; P9LE-LABEL: spltMemValui: 2842; P9LE: # %bb.0: # %entry 2843; P9LE-NEXT: lfiwzx f0, 0, r3 2844; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 2845; P9LE-NEXT: xxspltw v2, vs0, 3 2846; P9LE-NEXT: blr 2847; 2848; P8BE-LABEL: spltMemValui: 2849; P8BE: # %bb.0: # %entry 2850; P8BE-NEXT: lfiwzx f0, 0, r3 2851; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 2852; P8BE-NEXT: xxspltw v2, vs0, 0 2853; P8BE-NEXT: blr 2854; 2855; P8LE-LABEL: spltMemValui: 2856; P8LE: # %bb.0: # %entry 2857; P8LE-NEXT: lfiwzx f0, 0, r3 2858; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 2859; P8LE-NEXT: xxspltw v2, vs0, 3 2860; P8LE-NEXT: blr 2861entry: 2862 %0 = load i32, i32* %ptr, align 4 2863 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2864 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2865 ret <4 x i32> %splat.splat 2866} 2867 2868; Function Attrs: norecurse nounwind readnone 2869define <4 x i32> @spltCnstConvftoui() { 2870; P9BE-LABEL: spltCnstConvftoui: 2871; P9BE: # %bb.0: # %entry 2872; P9BE-NEXT: vspltisw v2, 4 2873; P9BE-NEXT: blr 2874; 2875; P9LE-LABEL: spltCnstConvftoui: 2876; P9LE: # %bb.0: # %entry 2877; P9LE-NEXT: vspltisw v2, 4 2878; P9LE-NEXT: blr 2879; 2880; P8BE-LABEL: spltCnstConvftoui: 2881; P8BE: # %bb.0: # %entry 2882; P8BE-NEXT: vspltisw v2, 4 2883; P8BE-NEXT: blr 2884; 2885; P8LE-LABEL: spltCnstConvftoui: 2886; P8LE: # %bb.0: # %entry 2887; P8LE-NEXT: vspltisw v2, 4 2888; P8LE-NEXT: blr 2889entry: 2890 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2891} 2892 2893; Function Attrs: norecurse nounwind readnone 2894define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2895; P9BE-LABEL: fromRegsConvftoui: 2896; P9BE: # %bb.0: # %entry 2897; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2898; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2899; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2900; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2901; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2902; P9BE-NEXT: xvcvdpuxws v2, vs0 2903; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2904; P9BE-NEXT: xvcvdpuxws v3, vs0 2905; P9BE-NEXT: vmrgew v2, v3, v2 2906; P9BE-NEXT: blr 2907; 2908; P9LE-LABEL: fromRegsConvftoui: 2909; P9LE: # %bb.0: # %entry 2910; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2911; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2912; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2913; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2914; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2915; P9LE-NEXT: xvcvdpuxws v2, vs0 2916; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2917; P9LE-NEXT: xvcvdpuxws v3, vs0 2918; P9LE-NEXT: vmrgew v2, v3, v2 2919; P9LE-NEXT: blr 2920; 2921; P8BE-LABEL: fromRegsConvftoui: 2922; P8BE: # %bb.0: # %entry 2923; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2924; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2925; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2926; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2927; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2928; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2929; P8BE-NEXT: xvcvdpuxws v2, vs0 2930; P8BE-NEXT: xvcvdpuxws v3, vs1 2931; P8BE-NEXT: vmrgew v2, v3, v2 2932; P8BE-NEXT: blr 2933; 2934; P8LE-LABEL: fromRegsConvftoui: 2935; P8LE: # %bb.0: # %entry 2936; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2937; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2938; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2939; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2940; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2941; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2942; P8LE-NEXT: xvcvdpuxws v2, vs0 2943; P8LE-NEXT: xvcvdpuxws v3, vs1 2944; P8LE-NEXT: vmrgew v2, v3, v2 2945; P8LE-NEXT: blr 2946entry: 2947 %conv = fptoui float %a to i32 2948 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2949 %conv1 = fptoui float %b to i32 2950 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2951 %conv3 = fptoui float %c to i32 2952 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2953 %conv5 = fptoui float %d to i32 2954 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2955 ret <4 x i32> %vecinit6 2956} 2957 2958; Function Attrs: norecurse nounwind readnone 2959define <4 x i32> @fromDiffConstsConvftoui() { 2960; P9BE-LABEL: fromDiffConstsConvftoui: 2961; P9BE: # %bb.0: # %entry 2962; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2963; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2964; P9BE-NEXT: lxvx v2, 0, r3 2965; P9BE-NEXT: blr 2966; 2967; P9LE-LABEL: fromDiffConstsConvftoui: 2968; P9LE: # %bb.0: # %entry 2969; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2970; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2971; P9LE-NEXT: lxvx v2, 0, r3 2972; P9LE-NEXT: blr 2973; 2974; P8BE-LABEL: fromDiffConstsConvftoui: 2975; P8BE: # %bb.0: # %entry 2976; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2977; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2978; P8BE-NEXT: lxvw4x v2, 0, r3 2979; P8BE-NEXT: blr 2980; 2981; P8LE-LABEL: fromDiffConstsConvftoui: 2982; P8LE: # %bb.0: # %entry 2983; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2984; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2985; P8LE-NEXT: lvx v2, 0, r3 2986; P8LE-NEXT: blr 2987entry: 2988 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2989} 2990 2991; Function Attrs: norecurse nounwind readonly 2992define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2993; P9BE-LABEL: fromDiffMemConsAConvftoui: 2994; P9BE: # %bb.0: # %entry 2995; P9BE-NEXT: lxv vs0, 0(r3) 2996; P9BE-NEXT: xvcvspuxws v2, vs0 2997; P9BE-NEXT: blr 2998; 2999; P9LE-LABEL: fromDiffMemConsAConvftoui: 3000; P9LE: # %bb.0: # %entry 3001; P9LE-NEXT: lxv vs0, 0(r3) 3002; P9LE-NEXT: xvcvspuxws v2, vs0 3003; P9LE-NEXT: blr 3004; 3005; P8BE-LABEL: fromDiffMemConsAConvftoui: 3006; P8BE: # %bb.0: # %entry 3007; P8BE-NEXT: lxvw4x vs0, 0, r3 3008; P8BE-NEXT: xvcvspuxws v2, vs0 3009; P8BE-NEXT: blr 3010; 3011; P8LE-LABEL: fromDiffMemConsAConvftoui: 3012; P8LE: # %bb.0: # %entry 3013; P8LE-NEXT: lxvd2x vs0, 0, r3 3014; P8LE-NEXT: xxswapd v2, vs0 3015; P8LE-NEXT: xvcvspuxws v2, v2 3016; P8LE-NEXT: blr 3017entry: 3018 %0 = bitcast float* %ptr to <4 x float>* 3019 %1 = load <4 x float>, <4 x float>* %0, align 4 3020 %2 = fptoui <4 x float> %1 to <4 x i32> 3021 ret <4 x i32> %2 3022} 3023 3024; Function Attrs: norecurse nounwind readonly 3025define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 3026; P9BE-LABEL: fromDiffMemConsDConvftoui: 3027; P9BE: # %bb.0: # %entry 3028; P9BE-NEXT: lxv v2, 0(r3) 3029; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3030; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3031; P9BE-NEXT: lxvx v3, 0, r3 3032; P9BE-NEXT: vperm v2, v2, v2, v3 3033; P9BE-NEXT: xvcvspuxws v2, v2 3034; P9BE-NEXT: blr 3035; 3036; P9LE-LABEL: fromDiffMemConsDConvftoui: 3037; P9LE: # %bb.0: # %entry 3038; P9LE-NEXT: lxv v2, 0(r3) 3039; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3040; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3041; P9LE-NEXT: lxvx v3, 0, r3 3042; P9LE-NEXT: vperm v2, v2, v2, v3 3043; P9LE-NEXT: xvcvspuxws v2, v2 3044; P9LE-NEXT: blr 3045; 3046; P8BE-LABEL: fromDiffMemConsDConvftoui: 3047; P8BE: # %bb.0: # %entry 3048; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 3049; P8BE-NEXT: lxvw4x v2, 0, r3 3050; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l 3051; P8BE-NEXT: lxvw4x v3, 0, r4 3052; P8BE-NEXT: vperm v2, v2, v2, v3 3053; P8BE-NEXT: xvcvspuxws v2, v2 3054; P8BE-NEXT: blr 3055; 3056; P8LE-LABEL: fromDiffMemConsDConvftoui: 3057; P8LE: # %bb.0: # %entry 3058; P8LE-NEXT: lxvd2x vs0, 0, r3 3059; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 3060; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l 3061; P8LE-NEXT: lvx v2, 0, r3 3062; P8LE-NEXT: xxswapd v3, vs0 3063; P8LE-NEXT: vperm v2, v3, v3, v2 3064; P8LE-NEXT: xvcvspuxws v2, v2 3065; P8LE-NEXT: blr 3066entry: 3067 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3068 %0 = load float, float* %arrayidx, align 4 3069 %conv = fptoui float %0 to i32 3070 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3071 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3072 %1 = load float, float* %arrayidx1, align 4 3073 %conv2 = fptoui float %1 to i32 3074 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3075 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3076 %2 = load float, float* %arrayidx4, align 4 3077 %conv5 = fptoui float %2 to i32 3078 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3079 %3 = load float, float* %ptr, align 4 3080 %conv8 = fptoui float %3 to i32 3081 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3082 ret <4 x i32> %vecinit9 3083} 3084 3085; Function Attrs: norecurse nounwind readonly 3086define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3087; P9BE-LABEL: fromDiffMemVarAConvftoui: 3088; P9BE: # %bb.0: # %entry 3089; P9BE-NEXT: sldi r4, r4, 2 3090; P9BE-NEXT: lfsux f0, r3, r4 3091; P9BE-NEXT: lfs f1, 12(r3) 3092; P9BE-NEXT: lfs f2, 4(r3) 3093; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3094; P9BE-NEXT: xvcvdpsp v2, vs1 3095; P9BE-NEXT: lfs f1, 8(r3) 3096; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3097; P9BE-NEXT: xvcvdpsp v3, vs0 3098; P9BE-NEXT: vmrgew v2, v3, v2 3099; P9BE-NEXT: xvcvspuxws v2, v2 3100; P9BE-NEXT: blr 3101; 3102; P9LE-LABEL: fromDiffMemVarAConvftoui: 3103; P9LE: # %bb.0: # %entry 3104; P9LE-NEXT: sldi r4, r4, 2 3105; P9LE-NEXT: lfsux f0, r3, r4 3106; P9LE-NEXT: lfs f1, 8(r3) 3107; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3108; P9LE-NEXT: lfs f1, 12(r3) 3109; P9LE-NEXT: xvcvdpsp v2, vs0 3110; P9LE-NEXT: lfs f0, 4(r3) 3111; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3112; P9LE-NEXT: xvcvdpsp v3, vs0 3113; P9LE-NEXT: vmrgew v2, v3, v2 3114; P9LE-NEXT: xvcvspuxws v2, v2 3115; P9LE-NEXT: blr 3116; 3117; P8BE-LABEL: fromDiffMemVarAConvftoui: 3118; P8BE: # %bb.0: # %entry 3119; P8BE-NEXT: sldi r4, r4, 2 3120; P8BE-NEXT: lfsux f0, r3, r4 3121; P8BE-NEXT: lfs f1, 12(r3) 3122; P8BE-NEXT: lfs f2, 4(r3) 3123; P8BE-NEXT: lfs f3, 8(r3) 3124; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3125; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3126; P8BE-NEXT: xvcvdpsp v2, vs1 3127; P8BE-NEXT: xvcvdpsp v3, vs0 3128; P8BE-NEXT: vmrgew v2, v3, v2 3129; P8BE-NEXT: xvcvspuxws v2, v2 3130; P8BE-NEXT: blr 3131; 3132; P8LE-LABEL: fromDiffMemVarAConvftoui: 3133; P8LE: # %bb.0: # %entry 3134; P8LE-NEXT: sldi r4, r4, 2 3135; P8LE-NEXT: lfsux f0, r3, r4 3136; P8LE-NEXT: lfs f1, 8(r3) 3137; P8LE-NEXT: lfs f2, 4(r3) 3138; P8LE-NEXT: lfs f3, 12(r3) 3139; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3140; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3141; P8LE-NEXT: xvcvdpsp v2, vs0 3142; P8LE-NEXT: xvcvdpsp v3, vs1 3143; P8LE-NEXT: vmrgew v2, v3, v2 3144; P8LE-NEXT: xvcvspuxws v2, v2 3145; P8LE-NEXT: blr 3146entry: 3147 %idxprom = sext i32 %elem to i64 3148 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3149 %0 = load float, float* %arrayidx, align 4 3150 %conv = fptoui float %0 to i32 3151 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3152 %add = add nsw i32 %elem, 1 3153 %idxprom1 = sext i32 %add to i64 3154 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3155 %1 = load float, float* %arrayidx2, align 4 3156 %conv3 = fptoui float %1 to i32 3157 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3158 %add5 = add nsw i32 %elem, 2 3159 %idxprom6 = sext i32 %add5 to i64 3160 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3161 %2 = load float, float* %arrayidx7, align 4 3162 %conv8 = fptoui float %2 to i32 3163 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3164 %add10 = add nsw i32 %elem, 3 3165 %idxprom11 = sext i32 %add10 to i64 3166 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3167 %3 = load float, float* %arrayidx12, align 4 3168 %conv13 = fptoui float %3 to i32 3169 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3170 ret <4 x i32> %vecinit14 3171; FIXME: implement finding consecutive loads with pre-inc 3172} 3173 3174; Function Attrs: norecurse nounwind readonly 3175define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3176; P9BE-LABEL: fromDiffMemVarDConvftoui: 3177; P9BE: # %bb.0: # %entry 3178; P9BE-NEXT: sldi r4, r4, 2 3179; P9BE-NEXT: lfsux f0, r3, r4 3180; P9BE-NEXT: lfs f1, -12(r3) 3181; P9BE-NEXT: lfs f2, -4(r3) 3182; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3183; P9BE-NEXT: xvcvdpsp v2, vs1 3184; P9BE-NEXT: lfs f1, -8(r3) 3185; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3186; P9BE-NEXT: xvcvdpsp v3, vs0 3187; P9BE-NEXT: vmrgew v2, v3, v2 3188; P9BE-NEXT: xvcvspuxws v2, v2 3189; P9BE-NEXT: blr 3190; 3191; P9LE-LABEL: fromDiffMemVarDConvftoui: 3192; P9LE: # %bb.0: # %entry 3193; P9LE-NEXT: sldi r4, r4, 2 3194; P9LE-NEXT: lfsux f0, r3, r4 3195; P9LE-NEXT: lfs f1, -8(r3) 3196; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3197; P9LE-NEXT: lfs f1, -12(r3) 3198; P9LE-NEXT: xvcvdpsp v2, vs0 3199; P9LE-NEXT: lfs f0, -4(r3) 3200; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3201; P9LE-NEXT: xvcvdpsp v3, vs0 3202; P9LE-NEXT: vmrgew v2, v3, v2 3203; P9LE-NEXT: xvcvspuxws v2, v2 3204; P9LE-NEXT: blr 3205; 3206; P8BE-LABEL: fromDiffMemVarDConvftoui: 3207; P8BE: # %bb.0: # %entry 3208; P8BE-NEXT: sldi r4, r4, 2 3209; P8BE-NEXT: lfsux f0, r3, r4 3210; P8BE-NEXT: lfs f1, -12(r3) 3211; P8BE-NEXT: lfs f2, -4(r3) 3212; P8BE-NEXT: lfs f3, -8(r3) 3213; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3214; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3215; P8BE-NEXT: xvcvdpsp v2, vs1 3216; P8BE-NEXT: xvcvdpsp v3, vs0 3217; P8BE-NEXT: vmrgew v2, v3, v2 3218; P8BE-NEXT: xvcvspuxws v2, v2 3219; P8BE-NEXT: blr 3220; 3221; P8LE-LABEL: fromDiffMemVarDConvftoui: 3222; P8LE: # %bb.0: # %entry 3223; P8LE-NEXT: sldi r4, r4, 2 3224; P8LE-NEXT: lfsux f0, r3, r4 3225; P8LE-NEXT: lfs f1, -8(r3) 3226; P8LE-NEXT: lfs f2, -4(r3) 3227; P8LE-NEXT: lfs f3, -12(r3) 3228; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3229; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3230; P8LE-NEXT: xvcvdpsp v2, vs0 3231; P8LE-NEXT: xvcvdpsp v3, vs1 3232; P8LE-NEXT: vmrgew v2, v3, v2 3233; P8LE-NEXT: xvcvspuxws v2, v2 3234; P8LE-NEXT: blr 3235entry: 3236 %idxprom = sext i32 %elem to i64 3237 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3238 %0 = load float, float* %arrayidx, align 4 3239 %conv = fptoui float %0 to i32 3240 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3241 %sub = add nsw i32 %elem, -1 3242 %idxprom1 = sext i32 %sub to i64 3243 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3244 %1 = load float, float* %arrayidx2, align 4 3245 %conv3 = fptoui float %1 to i32 3246 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3247 %sub5 = add nsw i32 %elem, -2 3248 %idxprom6 = sext i32 %sub5 to i64 3249 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3250 %2 = load float, float* %arrayidx7, align 4 3251 %conv8 = fptoui float %2 to i32 3252 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3253 %sub10 = add nsw i32 %elem, -3 3254 %idxprom11 = sext i32 %sub10 to i64 3255 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3256 %3 = load float, float* %arrayidx12, align 4 3257 %conv13 = fptoui float %3 to i32 3258 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3259 ret <4 x i32> %vecinit14 3260; FIXME: implement finding consecutive loads with pre-inc 3261} 3262 3263; Function Attrs: norecurse nounwind readnone 3264define <4 x i32> @spltRegValConvftoui(float %val) { 3265; P9BE-LABEL: spltRegValConvftoui: 3266; P9BE: # %bb.0: # %entry 3267; P9BE-NEXT: xscvdpuxws f0, f1 3268; P9BE-NEXT: xxspltw v2, vs0, 1 3269; P9BE-NEXT: blr 3270; 3271; P9LE-LABEL: spltRegValConvftoui: 3272; P9LE: # %bb.0: # %entry 3273; P9LE-NEXT: xscvdpuxws f0, f1 3274; P9LE-NEXT: xxspltw v2, vs0, 1 3275; P9LE-NEXT: blr 3276; 3277; P8BE-LABEL: spltRegValConvftoui: 3278; P8BE: # %bb.0: # %entry 3279; P8BE-NEXT: xscvdpuxws f0, f1 3280; P8BE-NEXT: xxspltw v2, vs0, 1 3281; P8BE-NEXT: blr 3282; 3283; P8LE-LABEL: spltRegValConvftoui: 3284; P8LE: # %bb.0: # %entry 3285; P8LE-NEXT: xscvdpuxws f0, f1 3286; P8LE-NEXT: xxspltw v2, vs0, 1 3287; P8LE-NEXT: blr 3288entry: 3289 %conv = fptoui float %val to i32 3290 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3291 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3292 ret <4 x i32> %splat.splat 3293} 3294 3295; Function Attrs: norecurse nounwind readonly 3296define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3297; P9BE-LABEL: spltMemValConvftoui: 3298; P9BE: # %bb.0: # %entry 3299; P9BE-NEXT: lxvwsx vs0, 0, r3 3300; P9BE-NEXT: xvcvspuxws v2, vs0 3301; P9BE-NEXT: blr 3302; 3303; P9LE-LABEL: spltMemValConvftoui: 3304; P9LE: # %bb.0: # %entry 3305; P9LE-NEXT: lxvwsx vs0, 0, r3 3306; P9LE-NEXT: xvcvspuxws v2, vs0 3307; P9LE-NEXT: blr 3308; 3309; P8BE-LABEL: spltMemValConvftoui: 3310; P8BE: # %bb.0: # %entry 3311; P8BE-NEXT: lfsx f0, 0, r3 3312; P8BE-NEXT: xscvdpuxws f0, f0 3313; P8BE-NEXT: xxspltw v2, vs0, 1 3314; P8BE-NEXT: blr 3315; 3316; P8LE-LABEL: spltMemValConvftoui: 3317; P8LE: # %bb.0: # %entry 3318; P8LE-NEXT: lfsx f0, 0, r3 3319; P8LE-NEXT: xscvdpuxws f0, f0 3320; P8LE-NEXT: xxspltw v2, vs0, 1 3321; P8LE-NEXT: blr 3322entry: 3323 %0 = load float, float* %ptr, align 4 3324 %conv = fptoui float %0 to i32 3325 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3326 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3327 ret <4 x i32> %splat.splat 3328} 3329 3330; Function Attrs: norecurse nounwind readnone 3331define <4 x i32> @spltCnstConvdtoui() { 3332; P9BE-LABEL: spltCnstConvdtoui: 3333; P9BE: # %bb.0: # %entry 3334; P9BE-NEXT: vspltisw v2, 4 3335; P9BE-NEXT: blr 3336; 3337; P9LE-LABEL: spltCnstConvdtoui: 3338; P9LE: # %bb.0: # %entry 3339; P9LE-NEXT: vspltisw v2, 4 3340; P9LE-NEXT: blr 3341; 3342; P8BE-LABEL: spltCnstConvdtoui: 3343; P8BE: # %bb.0: # %entry 3344; P8BE-NEXT: vspltisw v2, 4 3345; P8BE-NEXT: blr 3346; 3347; P8LE-LABEL: spltCnstConvdtoui: 3348; P8LE: # %bb.0: # %entry 3349; P8LE-NEXT: vspltisw v2, 4 3350; P8LE-NEXT: blr 3351entry: 3352 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3353} 3354 3355; Function Attrs: norecurse nounwind readnone 3356define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3357; P9BE-LABEL: fromRegsConvdtoui: 3358; P9BE: # %bb.0: # %entry 3359; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3360; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3361; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3362; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3363; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3364; P9BE-NEXT: xvcvdpuxws v2, vs0 3365; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3366; P9BE-NEXT: xvcvdpuxws v3, vs0 3367; P9BE-NEXT: vmrgew v2, v3, v2 3368; P9BE-NEXT: blr 3369; 3370; P9LE-LABEL: fromRegsConvdtoui: 3371; P9LE: # %bb.0: # %entry 3372; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3373; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3374; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3375; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3376; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3377; P9LE-NEXT: xvcvdpuxws v2, vs0 3378; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3379; P9LE-NEXT: xvcvdpuxws v3, vs0 3380; P9LE-NEXT: vmrgew v2, v3, v2 3381; P9LE-NEXT: blr 3382; 3383; P8BE-LABEL: fromRegsConvdtoui: 3384; P8BE: # %bb.0: # %entry 3385; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3386; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3387; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3388; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3389; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3390; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3391; P8BE-NEXT: xvcvdpuxws v2, vs0 3392; P8BE-NEXT: xvcvdpuxws v3, vs1 3393; P8BE-NEXT: vmrgew v2, v3, v2 3394; P8BE-NEXT: blr 3395; 3396; P8LE-LABEL: fromRegsConvdtoui: 3397; P8LE: # %bb.0: # %entry 3398; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3399; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3400; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3401; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3402; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3403; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3404; P8LE-NEXT: xvcvdpuxws v2, vs0 3405; P8LE-NEXT: xvcvdpuxws v3, vs1 3406; P8LE-NEXT: vmrgew v2, v3, v2 3407; P8LE-NEXT: blr 3408entry: 3409 %conv = fptoui double %a to i32 3410 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3411 %conv1 = fptoui double %b to i32 3412 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3413 %conv3 = fptoui double %c to i32 3414 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3415 %conv5 = fptoui double %d to i32 3416 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3417 ret <4 x i32> %vecinit6 3418} 3419 3420; Function Attrs: norecurse nounwind readnone 3421define <4 x i32> @fromDiffConstsConvdtoui() { 3422; P9BE-LABEL: fromDiffConstsConvdtoui: 3423; P9BE: # %bb.0: # %entry 3424; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3425; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3426; P9BE-NEXT: lxvx v2, 0, r3 3427; P9BE-NEXT: blr 3428; 3429; P9LE-LABEL: fromDiffConstsConvdtoui: 3430; P9LE: # %bb.0: # %entry 3431; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3432; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3433; P9LE-NEXT: lxvx v2, 0, r3 3434; P9LE-NEXT: blr 3435; 3436; P8BE-LABEL: fromDiffConstsConvdtoui: 3437; P8BE: # %bb.0: # %entry 3438; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3439; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3440; P8BE-NEXT: lxvw4x v2, 0, r3 3441; P8BE-NEXT: blr 3442; 3443; P8LE-LABEL: fromDiffConstsConvdtoui: 3444; P8LE: # %bb.0: # %entry 3445; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3446; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3447; P8LE-NEXT: lvx v2, 0, r3 3448; P8LE-NEXT: blr 3449entry: 3450 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3451} 3452 3453; Function Attrs: norecurse nounwind readonly 3454define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3455; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3456; P9BE: # %bb.0: # %entry 3457; P9BE-NEXT: lxv vs0, 0(r3) 3458; P9BE-NEXT: lxv vs1, 16(r3) 3459; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3460; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3461; P9BE-NEXT: xvcvdpuxws v2, vs2 3462; P9BE-NEXT: xvcvdpuxws v3, vs0 3463; P9BE-NEXT: vmrgew v2, v3, v2 3464; P9BE-NEXT: blr 3465; 3466; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3467; P9LE: # %bb.0: # %entry 3468; P9LE-NEXT: lxv vs0, 0(r3) 3469; P9LE-NEXT: lxv vs1, 16(r3) 3470; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3471; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3472; P9LE-NEXT: xvcvdpuxws v2, vs2 3473; P9LE-NEXT: xvcvdpuxws v3, vs0 3474; P9LE-NEXT: vmrgew v2, v3, v2 3475; P9LE-NEXT: blr 3476; 3477; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3478; P8BE: # %bb.0: # %entry 3479; P8BE-NEXT: li r4, 16 3480; P8BE-NEXT: lxvd2x vs0, 0, r3 3481; P8BE-NEXT: lxvd2x vs1, r3, r4 3482; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3483; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3484; P8BE-NEXT: xvcvdpuxws v2, vs2 3485; P8BE-NEXT: xvcvdpuxws v3, vs0 3486; P8BE-NEXT: vmrgew v2, v3, v2 3487; P8BE-NEXT: blr 3488; 3489; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3490; P8LE: # %bb.0: # %entry 3491; P8LE-NEXT: li r4, 16 3492; P8LE-NEXT: lxvd2x vs0, 0, r3 3493; P8LE-NEXT: lxvd2x vs1, r3, r4 3494; P8LE-NEXT: xxswapd vs0, vs0 3495; P8LE-NEXT: xxswapd vs1, vs1 3496; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3497; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3498; P8LE-NEXT: xvcvdpuxws v2, vs2 3499; P8LE-NEXT: xvcvdpuxws v3, vs0 3500; P8LE-NEXT: vmrgew v2, v3, v2 3501; P8LE-NEXT: blr 3502entry: 3503 %0 = bitcast double* %ptr to <2 x double>* 3504 %1 = load <2 x double>, <2 x double>* %0, align 8 3505 %2 = fptoui <2 x double> %1 to <2 x i32> 3506 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3507 %3 = bitcast double* %arrayidx4 to <2 x double>* 3508 %4 = load <2 x double>, <2 x double>* %3, align 8 3509 %5 = fptoui <2 x double> %4 to <2 x i32> 3510 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3511 ret <4 x i32> %vecinit9 3512} 3513 3514; Function Attrs: norecurse nounwind readonly 3515define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3516; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3517; P9BE: # %bb.0: # %entry 3518; P9BE-NEXT: lfd f0, 24(r3) 3519; P9BE-NEXT: lfd f1, 16(r3) 3520; P9BE-NEXT: lfd f2, 8(r3) 3521; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3522; P9BE-NEXT: lfd f3, 0(r3) 3523; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3524; P9BE-NEXT: xvcvdpuxws v2, vs1 3525; P9BE-NEXT: xvcvdpuxws v3, vs0 3526; P9BE-NEXT: vmrgew v2, v3, v2 3527; P9BE-NEXT: blr 3528; 3529; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3530; P9LE: # %bb.0: # %entry 3531; P9LE-NEXT: lfd f0, 24(r3) 3532; P9LE-NEXT: lfd f2, 8(r3) 3533; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3534; P9LE-NEXT: lfd f1, 16(r3) 3535; P9LE-NEXT: lfd f3, 0(r3) 3536; P9LE-NEXT: xvcvdpuxws v2, vs0 3537; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3538; P9LE-NEXT: xvcvdpuxws v3, vs0 3539; P9LE-NEXT: vmrgew v2, v3, v2 3540; P9LE-NEXT: blr 3541; 3542; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3543; P8BE: # %bb.0: # %entry 3544; P8BE-NEXT: lfdx f3, 0, r3 3545; P8BE-NEXT: lfd f0, 24(r3) 3546; P8BE-NEXT: lfd f1, 8(r3) 3547; P8BE-NEXT: lfd f2, 16(r3) 3548; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3549; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3550; P8BE-NEXT: xvcvdpuxws v2, vs0 3551; P8BE-NEXT: xvcvdpuxws v3, vs1 3552; P8BE-NEXT: vmrgew v2, v2, v3 3553; P8BE-NEXT: blr 3554; 3555; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3556; P8LE: # %bb.0: # %entry 3557; P8LE-NEXT: lfdx f3, 0, r3 3558; P8LE-NEXT: lfd f0, 24(r3) 3559; P8LE-NEXT: lfd f1, 8(r3) 3560; P8LE-NEXT: lfd f2, 16(r3) 3561; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3562; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3563; P8LE-NEXT: xvcvdpuxws v2, vs0 3564; P8LE-NEXT: xvcvdpuxws v3, vs1 3565; P8LE-NEXT: vmrgew v2, v3, v2 3566; P8LE-NEXT: blr 3567entry: 3568 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3569 %0 = load double, double* %arrayidx, align 8 3570 %conv = fptoui double %0 to i32 3571 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3572 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3573 %1 = load double, double* %arrayidx1, align 8 3574 %conv2 = fptoui double %1 to i32 3575 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3576 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3577 %2 = load double, double* %arrayidx4, align 8 3578 %conv5 = fptoui double %2 to i32 3579 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3580 %3 = load double, double* %ptr, align 8 3581 %conv8 = fptoui double %3 to i32 3582 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3583 ret <4 x i32> %vecinit9 3584} 3585 3586; Function Attrs: norecurse nounwind readonly 3587define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3588; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3589; P9BE: # %bb.0: # %entry 3590; P9BE-NEXT: sldi r4, r4, 3 3591; P9BE-NEXT: lfdux f0, r3, r4 3592; P9BE-NEXT: lfd f1, 8(r3) 3593; P9BE-NEXT: lfd f2, 16(r3) 3594; P9BE-NEXT: lfd f3, 24(r3) 3595; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3596; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3597; P9BE-NEXT: xvcvdpuxws v2, vs1 3598; P9BE-NEXT: xvcvdpuxws v3, vs0 3599; P9BE-NEXT: vmrgew v2, v3, v2 3600; P9BE-NEXT: blr 3601; 3602; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3603; P9LE: # %bb.0: # %entry 3604; P9LE-NEXT: sldi r4, r4, 3 3605; P9LE-NEXT: lfdux f0, r3, r4 3606; P9LE-NEXT: lfd f2, 16(r3) 3607; P9LE-NEXT: lfd f1, 8(r3) 3608; P9LE-NEXT: lfd f3, 24(r3) 3609; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3610; P9LE-NEXT: xvcvdpuxws v2, vs0 3611; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3612; P9LE-NEXT: xvcvdpuxws v3, vs0 3613; P9LE-NEXT: vmrgew v2, v3, v2 3614; P9LE-NEXT: blr 3615; 3616; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3617; P8BE: # %bb.0: # %entry 3618; P8BE-NEXT: sldi r4, r4, 3 3619; P8BE-NEXT: lfdux f0, r3, r4 3620; P8BE-NEXT: lfd f1, 8(r3) 3621; P8BE-NEXT: lfd f2, 24(r3) 3622; P8BE-NEXT: lfd f3, 16(r3) 3623; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3624; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3625; P8BE-NEXT: xvcvdpuxws v2, vs1 3626; P8BE-NEXT: xvcvdpuxws v3, vs0 3627; P8BE-NEXT: vmrgew v2, v3, v2 3628; P8BE-NEXT: blr 3629; 3630; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3631; P8LE: # %bb.0: # %entry 3632; P8LE-NEXT: sldi r4, r4, 3 3633; P8LE-NEXT: lfdux f0, r3, r4 3634; P8LE-NEXT: lfd f1, 16(r3) 3635; P8LE-NEXT: lfd f2, 8(r3) 3636; P8LE-NEXT: lfd f3, 24(r3) 3637; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3638; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3639; P8LE-NEXT: xvcvdpuxws v2, vs0 3640; P8LE-NEXT: xvcvdpuxws v3, vs1 3641; P8LE-NEXT: vmrgew v2, v3, v2 3642; P8LE-NEXT: blr 3643entry: 3644 %idxprom = sext i32 %elem to i64 3645 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3646 %0 = load double, double* %arrayidx, align 8 3647 %conv = fptoui double %0 to i32 3648 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3649 %add = add nsw i32 %elem, 1 3650 %idxprom1 = sext i32 %add to i64 3651 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3652 %1 = load double, double* %arrayidx2, align 8 3653 %conv3 = fptoui double %1 to i32 3654 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3655 %add5 = add nsw i32 %elem, 2 3656 %idxprom6 = sext i32 %add5 to i64 3657 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3658 %2 = load double, double* %arrayidx7, align 8 3659 %conv8 = fptoui double %2 to i32 3660 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3661 %add10 = add nsw i32 %elem, 3 3662 %idxprom11 = sext i32 %add10 to i64 3663 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3664 %3 = load double, double* %arrayidx12, align 8 3665 %conv13 = fptoui double %3 to i32 3666 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3667 ret <4 x i32> %vecinit14 3668} 3669 3670; Function Attrs: norecurse nounwind readonly 3671define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3672; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3673; P9BE: # %bb.0: # %entry 3674; P9BE-NEXT: sldi r4, r4, 3 3675; P9BE-NEXT: lfdux f0, r3, r4 3676; P9BE-NEXT: lfd f1, -8(r3) 3677; P9BE-NEXT: lfd f2, -16(r3) 3678; P9BE-NEXT: lfd f3, -24(r3) 3679; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3680; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3681; P9BE-NEXT: xvcvdpuxws v2, vs1 3682; P9BE-NEXT: xvcvdpuxws v3, vs0 3683; P9BE-NEXT: vmrgew v2, v3, v2 3684; P9BE-NEXT: blr 3685; 3686; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3687; P9LE: # %bb.0: # %entry 3688; P9LE-NEXT: sldi r4, r4, 3 3689; P9LE-NEXT: lfdux f0, r3, r4 3690; P9LE-NEXT: lfd f2, -16(r3) 3691; P9LE-NEXT: lfd f1, -8(r3) 3692; P9LE-NEXT: lfd f3, -24(r3) 3693; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3694; P9LE-NEXT: xvcvdpuxws v2, vs0 3695; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3696; P9LE-NEXT: xvcvdpuxws v3, vs0 3697; P9LE-NEXT: vmrgew v2, v3, v2 3698; P9LE-NEXT: blr 3699; 3700; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3701; P8BE: # %bb.0: # %entry 3702; P8BE-NEXT: sldi r4, r4, 3 3703; P8BE-NEXT: lfdux f0, r3, r4 3704; P8BE-NEXT: lfd f1, -8(r3) 3705; P8BE-NEXT: lfd f2, -24(r3) 3706; P8BE-NEXT: lfd f3, -16(r3) 3707; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3708; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3709; P8BE-NEXT: xvcvdpuxws v2, vs1 3710; P8BE-NEXT: xvcvdpuxws v3, vs0 3711; P8BE-NEXT: vmrgew v2, v3, v2 3712; P8BE-NEXT: blr 3713; 3714; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3715; P8LE: # %bb.0: # %entry 3716; P8LE-NEXT: sldi r4, r4, 3 3717; P8LE-NEXT: lfdux f0, r3, r4 3718; P8LE-NEXT: lfd f1, -16(r3) 3719; P8LE-NEXT: lfd f2, -8(r3) 3720; P8LE-NEXT: lfd f3, -24(r3) 3721; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3722; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3723; P8LE-NEXT: xvcvdpuxws v2, vs0 3724; P8LE-NEXT: xvcvdpuxws v3, vs1 3725; P8LE-NEXT: vmrgew v2, v3, v2 3726; P8LE-NEXT: blr 3727entry: 3728 %idxprom = sext i32 %elem to i64 3729 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3730 %0 = load double, double* %arrayidx, align 8 3731 %conv = fptoui double %0 to i32 3732 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3733 %sub = add nsw i32 %elem, -1 3734 %idxprom1 = sext i32 %sub to i64 3735 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3736 %1 = load double, double* %arrayidx2, align 8 3737 %conv3 = fptoui double %1 to i32 3738 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3739 %sub5 = add nsw i32 %elem, -2 3740 %idxprom6 = sext i32 %sub5 to i64 3741 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3742 %2 = load double, double* %arrayidx7, align 8 3743 %conv8 = fptoui double %2 to i32 3744 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3745 %sub10 = add nsw i32 %elem, -3 3746 %idxprom11 = sext i32 %sub10 to i64 3747 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3748 %3 = load double, double* %arrayidx12, align 8 3749 %conv13 = fptoui double %3 to i32 3750 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3751 ret <4 x i32> %vecinit14 3752} 3753 3754; Function Attrs: norecurse nounwind readnone 3755define <4 x i32> @spltRegValConvdtoui(double %val) { 3756; P9BE-LABEL: spltRegValConvdtoui: 3757; P9BE: # %bb.0: # %entry 3758; P9BE-NEXT: xscvdpuxws f0, f1 3759; P9BE-NEXT: xxspltw v2, vs0, 1 3760; P9BE-NEXT: blr 3761; 3762; P9LE-LABEL: spltRegValConvdtoui: 3763; P9LE: # %bb.0: # %entry 3764; P9LE-NEXT: xscvdpuxws f0, f1 3765; P9LE-NEXT: xxspltw v2, vs0, 1 3766; P9LE-NEXT: blr 3767; 3768; P8BE-LABEL: spltRegValConvdtoui: 3769; P8BE: # %bb.0: # %entry 3770; P8BE-NEXT: xscvdpuxws f0, f1 3771; P8BE-NEXT: xxspltw v2, vs0, 1 3772; P8BE-NEXT: blr 3773; 3774; P8LE-LABEL: spltRegValConvdtoui: 3775; P8LE: # %bb.0: # %entry 3776; P8LE-NEXT: xscvdpuxws f0, f1 3777; P8LE-NEXT: xxspltw v2, vs0, 1 3778; P8LE-NEXT: blr 3779entry: 3780 %conv = fptoui double %val to i32 3781 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3782 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3783 ret <4 x i32> %splat.splat 3784} 3785 3786; Function Attrs: norecurse nounwind readonly 3787define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3788; P9BE-LABEL: spltMemValConvdtoui: 3789; P9BE: # %bb.0: # %entry 3790; P9BE-NEXT: lfd f0, 0(r3) 3791; P9BE-NEXT: xscvdpuxws f0, f0 3792; P9BE-NEXT: xxspltw v2, vs0, 1 3793; P9BE-NEXT: blr 3794; 3795; P9LE-LABEL: spltMemValConvdtoui: 3796; P9LE: # %bb.0: # %entry 3797; P9LE-NEXT: lfd f0, 0(r3) 3798; P9LE-NEXT: xscvdpuxws f0, f0 3799; P9LE-NEXT: xxspltw v2, vs0, 1 3800; P9LE-NEXT: blr 3801; 3802; P8BE-LABEL: spltMemValConvdtoui: 3803; P8BE: # %bb.0: # %entry 3804; P8BE-NEXT: lfdx f0, 0, r3 3805; P8BE-NEXT: xscvdpuxws f0, f0 3806; P8BE-NEXT: xxspltw v2, vs0, 1 3807; P8BE-NEXT: blr 3808; 3809; P8LE-LABEL: spltMemValConvdtoui: 3810; P8LE: # %bb.0: # %entry 3811; P8LE-NEXT: lfdx f0, 0, r3 3812; P8LE-NEXT: xscvdpuxws f0, f0 3813; P8LE-NEXT: xxspltw v2, vs0, 1 3814; P8LE-NEXT: blr 3815entry: 3816 %0 = load double, double* %ptr, align 8 3817 %conv = fptoui double %0 to i32 3818 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3819 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3820 ret <4 x i32> %splat.splat 3821} 3822; Function Attrs: norecurse nounwind readnone 3823define <2 x i64> @allZeroll() { 3824; P9BE-LABEL: allZeroll: 3825; P9BE: # %bb.0: # %entry 3826; P9BE-NEXT: xxlxor v2, v2, v2 3827; P9BE-NEXT: blr 3828; 3829; P9LE-LABEL: allZeroll: 3830; P9LE: # %bb.0: # %entry 3831; P9LE-NEXT: xxlxor v2, v2, v2 3832; P9LE-NEXT: blr 3833; 3834; P8BE-LABEL: allZeroll: 3835; P8BE: # %bb.0: # %entry 3836; P8BE-NEXT: xxlxor v2, v2, v2 3837; P8BE-NEXT: blr 3838; 3839; P8LE-LABEL: allZeroll: 3840; P8LE: # %bb.0: # %entry 3841; P8LE-NEXT: xxlxor v2, v2, v2 3842; P8LE-NEXT: blr 3843entry: 3844 ret <2 x i64> zeroinitializer 3845} 3846 3847; Function Attrs: norecurse nounwind readnone 3848define <2 x i64> @spltConst1ll() { 3849; P9BE-LABEL: spltConst1ll: 3850; P9BE: # %bb.0: # %entry 3851; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3852; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3853; P9BE-NEXT: lxvx v2, 0, r3 3854; P9BE-NEXT: blr 3855; 3856; P9LE-LABEL: spltConst1ll: 3857; P9LE: # %bb.0: # %entry 3858; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3859; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3860; P9LE-NEXT: lxvx v2, 0, r3 3861; P9LE-NEXT: blr 3862; 3863; P8BE-LABEL: spltConst1ll: 3864; P8BE: # %bb.0: # %entry 3865; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3866; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3867; P8BE-NEXT: lxvd2x v2, 0, r3 3868; P8BE-NEXT: blr 3869; 3870; P8LE-LABEL: spltConst1ll: 3871; P8LE: # %bb.0: # %entry 3872; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3873; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3874; P8LE-NEXT: lxvd2x vs0, 0, r3 3875; P8LE-NEXT: xxswapd v2, vs0 3876; P8LE-NEXT: blr 3877entry: 3878 ret <2 x i64> <i64 1, i64 1> 3879} 3880 3881; Function Attrs: norecurse nounwind readnone 3882define <2 x i64> @spltConst16kll() { 3883; P9BE-LABEL: spltConst16kll: 3884; P9BE: # %bb.0: # %entry 3885; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3886; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3887; P9BE-NEXT: lxvx v2, 0, r3 3888; P9BE-NEXT: blr 3889; 3890; P9LE-LABEL: spltConst16kll: 3891; P9LE: # %bb.0: # %entry 3892; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3893; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3894; P9LE-NEXT: lxvx v2, 0, r3 3895; P9LE-NEXT: blr 3896; 3897; P8BE-LABEL: spltConst16kll: 3898; P8BE: # %bb.0: # %entry 3899; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3900; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3901; P8BE-NEXT: lxvd2x v2, 0, r3 3902; P8BE-NEXT: blr 3903; 3904; P8LE-LABEL: spltConst16kll: 3905; P8LE: # %bb.0: # %entry 3906; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3907; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3908; P8LE-NEXT: lxvd2x vs0, 0, r3 3909; P8LE-NEXT: xxswapd v2, vs0 3910; P8LE-NEXT: blr 3911entry: 3912 ret <2 x i64> <i64 32767, i64 32767> 3913} 3914 3915; Function Attrs: norecurse nounwind readnone 3916define <2 x i64> @spltConst32kll() { 3917; P9BE-LABEL: spltConst32kll: 3918; P9BE: # %bb.0: # %entry 3919; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3920; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3921; P9BE-NEXT: lxvx v2, 0, r3 3922; P9BE-NEXT: blr 3923; 3924; P9LE-LABEL: spltConst32kll: 3925; P9LE: # %bb.0: # %entry 3926; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3927; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3928; P9LE-NEXT: lxvx v2, 0, r3 3929; P9LE-NEXT: blr 3930; 3931; P8BE-LABEL: spltConst32kll: 3932; P8BE: # %bb.0: # %entry 3933; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3934; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3935; P8BE-NEXT: lxvd2x v2, 0, r3 3936; P8BE-NEXT: blr 3937; 3938; P8LE-LABEL: spltConst32kll: 3939; P8LE: # %bb.0: # %entry 3940; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3941; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3942; P8LE-NEXT: lxvd2x vs0, 0, r3 3943; P8LE-NEXT: xxswapd v2, vs0 3944; P8LE-NEXT: blr 3945entry: 3946 ret <2 x i64> <i64 65535, i64 65535> 3947} 3948 3949; Function Attrs: norecurse nounwind readnone 3950define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3951; P9BE-LABEL: fromRegsll: 3952; P9BE: # %bb.0: # %entry 3953; P9BE-NEXT: mtvsrdd v2, r3, r4 3954; P9BE-NEXT: blr 3955; 3956; P9LE-LABEL: fromRegsll: 3957; P9LE: # %bb.0: # %entry 3958; P9LE-NEXT: mtvsrdd v2, r4, r3 3959; P9LE-NEXT: blr 3960; 3961; P8BE-LABEL: fromRegsll: 3962; P8BE: # %bb.0: # %entry 3963; P8BE-NEXT: mtvsrd f0, r4 3964; P8BE-NEXT: mtvsrd f1, r3 3965; P8BE-NEXT: xxmrghd v2, vs1, vs0 3966; P8BE-NEXT: blr 3967; 3968; P8LE-LABEL: fromRegsll: 3969; P8LE: # %bb.0: # %entry 3970; P8LE-NEXT: mtvsrd f0, r3 3971; P8LE-NEXT: mtvsrd f1, r4 3972; P8LE-NEXT: xxmrghd v2, vs1, vs0 3973; P8LE-NEXT: blr 3974entry: 3975 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3976 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3977 ret <2 x i64> %vecinit1 3978} 3979 3980; Function Attrs: norecurse nounwind readnone 3981define <2 x i64> @fromDiffConstsll() { 3982; P9BE-LABEL: fromDiffConstsll: 3983; P9BE: # %bb.0: # %entry 3984; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3985; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3986; P9BE-NEXT: lxvx v2, 0, r3 3987; P9BE-NEXT: blr 3988; 3989; P9LE-LABEL: fromDiffConstsll: 3990; P9LE: # %bb.0: # %entry 3991; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3992; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3993; P9LE-NEXT: lxvx v2, 0, r3 3994; P9LE-NEXT: blr 3995; 3996; P8BE-LABEL: fromDiffConstsll: 3997; P8BE: # %bb.0: # %entry 3998; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3999; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 4000; P8BE-NEXT: lxvd2x v2, 0, r3 4001; P8BE-NEXT: blr 4002; 4003; P8LE-LABEL: fromDiffConstsll: 4004; P8LE: # %bb.0: # %entry 4005; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 4006; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 4007; P8LE-NEXT: lxvd2x vs0, 0, r3 4008; P8LE-NEXT: xxswapd v2, vs0 4009; P8LE-NEXT: blr 4010entry: 4011 ret <2 x i64> <i64 242, i64 -113> 4012} 4013 4014; Function Attrs: norecurse nounwind readonly 4015define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 4016; P9BE-LABEL: fromDiffMemConsAll: 4017; P9BE: # %bb.0: # %entry 4018; P9BE-NEXT: lxv v2, 0(r3) 4019; P9BE-NEXT: blr 4020; 4021; P9LE-LABEL: fromDiffMemConsAll: 4022; P9LE: # %bb.0: # %entry 4023; P9LE-NEXT: lxv v2, 0(r3) 4024; P9LE-NEXT: blr 4025; 4026; P8BE-LABEL: fromDiffMemConsAll: 4027; P8BE: # %bb.0: # %entry 4028; P8BE-NEXT: lxvd2x v2, 0, r3 4029; P8BE-NEXT: blr 4030; 4031; P8LE-LABEL: fromDiffMemConsAll: 4032; P8LE: # %bb.0: # %entry 4033; P8LE-NEXT: lxvd2x vs0, 0, r3 4034; P8LE-NEXT: xxswapd v2, vs0 4035; P8LE-NEXT: blr 4036entry: 4037 %0 = load i64, i64* %arr, align 8 4038 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4039 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4040 %1 = load i64, i64* %arrayidx1, align 8 4041 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4042 ret <2 x i64> %vecinit2 4043} 4044 4045; Function Attrs: norecurse nounwind readonly 4046define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 4047; P9BE-LABEL: fromDiffMemConsDll: 4048; P9BE: # %bb.0: # %entry 4049; P9BE-NEXT: lxv v2, 16(r3) 4050; P9BE-NEXT: xxswapd v2, v2 4051; P9BE-NEXT: blr 4052; 4053; P9LE-LABEL: fromDiffMemConsDll: 4054; P9LE: # %bb.0: # %entry 4055; P9LE-NEXT: addi r3, r3, 16 4056; P9LE-NEXT: lxvd2x v2, 0, r3 4057; P9LE-NEXT: blr 4058; 4059; P8BE-LABEL: fromDiffMemConsDll: 4060; P8BE: # %bb.0: # %entry 4061; P8BE-NEXT: addi r3, r3, 16 4062; P8BE-NEXT: lxvd2x v2, 0, r3 4063; P8BE-NEXT: xxswapd v2, v2 4064; P8BE-NEXT: blr 4065; 4066; P8LE-LABEL: fromDiffMemConsDll: 4067; P8LE: # %bb.0: # %entry 4068; P8LE-NEXT: addi r3, r3, 16 4069; P8LE-NEXT: lxvd2x v2, 0, r3 4070; P8LE-NEXT: blr 4071entry: 4072 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4073 %0 = load i64, i64* %arrayidx, align 8 4074 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4075 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4076 %1 = load i64, i64* %arrayidx1, align 8 4077 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4078 ret <2 x i64> %vecinit2 4079} 4080 4081; Function Attrs: norecurse nounwind readonly 4082define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4083; P9BE-LABEL: fromDiffMemVarAll: 4084; P9BE: # %bb.0: # %entry 4085; P9BE-NEXT: sldi r4, r4, 3 4086; P9BE-NEXT: lxvx v2, r3, r4 4087; P9BE-NEXT: blr 4088; 4089; P9LE-LABEL: fromDiffMemVarAll: 4090; P9LE: # %bb.0: # %entry 4091; P9LE-NEXT: sldi r4, r4, 3 4092; P9LE-NEXT: lxvx v2, r3, r4 4093; P9LE-NEXT: blr 4094; 4095; P8BE-LABEL: fromDiffMemVarAll: 4096; P8BE: # %bb.0: # %entry 4097; P8BE-NEXT: sldi r4, r4, 3 4098; P8BE-NEXT: lxvd2x v2, r3, r4 4099; P8BE-NEXT: blr 4100; 4101; P8LE-LABEL: fromDiffMemVarAll: 4102; P8LE: # %bb.0: # %entry 4103; P8LE-NEXT: sldi r4, r4, 3 4104; P8LE-NEXT: lxvd2x vs0, r3, r4 4105; P8LE-NEXT: xxswapd v2, vs0 4106; P8LE-NEXT: blr 4107entry: 4108 %idxprom = sext i32 %elem to i64 4109 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4110 %0 = load i64, i64* %arrayidx, align 8 4111 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4112 %add = add nsw i32 %elem, 1 4113 %idxprom1 = sext i32 %add to i64 4114 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4115 %1 = load i64, i64* %arrayidx2, align 8 4116 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4117 ret <2 x i64> %vecinit3 4118} 4119 4120; Function Attrs: norecurse nounwind readonly 4121define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4122; P9BE-LABEL: fromDiffMemVarDll: 4123; P9BE: # %bb.0: # %entry 4124; P9BE-NEXT: sldi r4, r4, 3 4125; P9BE-NEXT: add r3, r3, r4 4126; P9BE-NEXT: li r4, -8 4127; P9BE-NEXT: lxvx v2, r3, r4 4128; P9BE-NEXT: xxswapd v2, v2 4129; P9BE-NEXT: blr 4130; 4131; P9LE-LABEL: fromDiffMemVarDll: 4132; P9LE: # %bb.0: # %entry 4133; P9LE-NEXT: sldi r4, r4, 3 4134; P9LE-NEXT: add r3, r3, r4 4135; P9LE-NEXT: addi r3, r3, -8 4136; P9LE-NEXT: lxvd2x v2, 0, r3 4137; P9LE-NEXT: blr 4138; 4139; P8BE-LABEL: fromDiffMemVarDll: 4140; P8BE: # %bb.0: # %entry 4141; P8BE-NEXT: sldi r4, r4, 3 4142; P8BE-NEXT: add r3, r3, r4 4143; P8BE-NEXT: addi r3, r3, -8 4144; P8BE-NEXT: lxvd2x v2, 0, r3 4145; P8BE-NEXT: xxswapd v2, v2 4146; P8BE-NEXT: blr 4147; 4148; P8LE-LABEL: fromDiffMemVarDll: 4149; P8LE: # %bb.0: # %entry 4150; P8LE-NEXT: sldi r4, r4, 3 4151; P8LE-NEXT: add r3, r3, r4 4152; P8LE-NEXT: addi r3, r3, -8 4153; P8LE-NEXT: lxvd2x v2, 0, r3 4154; P8LE-NEXT: blr 4155entry: 4156 %idxprom = sext i32 %elem to i64 4157 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4158 %0 = load i64, i64* %arrayidx, align 8 4159 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4160 %sub = add nsw i32 %elem, -1 4161 %idxprom1 = sext i32 %sub to i64 4162 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4163 %1 = load i64, i64* %arrayidx2, align 8 4164 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4165 ret <2 x i64> %vecinit3 4166} 4167 4168; Function Attrs: norecurse nounwind readonly 4169define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4170; P9BE-LABEL: fromRandMemConsll: 4171; P9BE: # %bb.0: # %entry 4172; P9BE-NEXT: ld r4, 32(r3) 4173; P9BE-NEXT: ld r3, 144(r3) 4174; P9BE-NEXT: mtvsrdd v2, r4, r3 4175; P9BE-NEXT: blr 4176; 4177; P9LE-LABEL: fromRandMemConsll: 4178; P9LE: # %bb.0: # %entry 4179; P9LE-NEXT: ld r4, 32(r3) 4180; P9LE-NEXT: ld r3, 144(r3) 4181; P9LE-NEXT: mtvsrdd v2, r3, r4 4182; P9LE-NEXT: blr 4183; 4184; P8BE-LABEL: fromRandMemConsll: 4185; P8BE: # %bb.0: # %entry 4186; P8BE-NEXT: ld r4, 144(r3) 4187; P8BE-NEXT: ld r3, 32(r3) 4188; P8BE-NEXT: mtvsrd f0, r4 4189; P8BE-NEXT: mtvsrd f1, r3 4190; P8BE-NEXT: xxmrghd v2, vs1, vs0 4191; P8BE-NEXT: blr 4192; 4193; P8LE-LABEL: fromRandMemConsll: 4194; P8LE: # %bb.0: # %entry 4195; P8LE-NEXT: ld r4, 32(r3) 4196; P8LE-NEXT: ld r3, 144(r3) 4197; P8LE-NEXT: mtvsrd f0, r4 4198; P8LE-NEXT: mtvsrd f1, r3 4199; P8LE-NEXT: xxmrghd v2, vs1, vs0 4200; P8LE-NEXT: blr 4201entry: 4202 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4203 %0 = load i64, i64* %arrayidx, align 8 4204 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4205 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4206 %1 = load i64, i64* %arrayidx1, align 8 4207 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4208 ret <2 x i64> %vecinit2 4209} 4210 4211; Function Attrs: norecurse nounwind readonly 4212define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4213; P9BE-LABEL: fromRandMemVarll: 4214; P9BE: # %bb.0: # %entry 4215; P9BE-NEXT: sldi r4, r4, 3 4216; P9BE-NEXT: add r3, r3, r4 4217; P9BE-NEXT: ld r4, 32(r3) 4218; P9BE-NEXT: ld r3, 8(r3) 4219; P9BE-NEXT: mtvsrdd v2, r4, r3 4220; P9BE-NEXT: blr 4221; 4222; P9LE-LABEL: fromRandMemVarll: 4223; P9LE: # %bb.0: # %entry 4224; P9LE-NEXT: sldi r4, r4, 3 4225; P9LE-NEXT: add r3, r3, r4 4226; P9LE-NEXT: ld r4, 32(r3) 4227; P9LE-NEXT: ld r3, 8(r3) 4228; P9LE-NEXT: mtvsrdd v2, r3, r4 4229; P9LE-NEXT: blr 4230; 4231; P8BE-LABEL: fromRandMemVarll: 4232; P8BE: # %bb.0: # %entry 4233; P8BE-NEXT: sldi r4, r4, 3 4234; P8BE-NEXT: add r3, r3, r4 4235; P8BE-NEXT: ld r4, 8(r3) 4236; P8BE-NEXT: ld r3, 32(r3) 4237; P8BE-NEXT: mtvsrd f0, r4 4238; P8BE-NEXT: mtvsrd f1, r3 4239; P8BE-NEXT: xxmrghd v2, vs1, vs0 4240; P8BE-NEXT: blr 4241; 4242; P8LE-LABEL: fromRandMemVarll: 4243; P8LE: # %bb.0: # %entry 4244; P8LE-NEXT: sldi r4, r4, 3 4245; P8LE-NEXT: add r3, r3, r4 4246; P8LE-NEXT: ld r4, 32(r3) 4247; P8LE-NEXT: ld r3, 8(r3) 4248; P8LE-NEXT: mtvsrd f0, r4 4249; P8LE-NEXT: mtvsrd f1, r3 4250; P8LE-NEXT: xxmrghd v2, vs1, vs0 4251; P8LE-NEXT: blr 4252entry: 4253 %add = add nsw i32 %elem, 4 4254 %idxprom = sext i32 %add to i64 4255 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4256 %0 = load i64, i64* %arrayidx, align 8 4257 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4258 %add1 = add nsw i32 %elem, 1 4259 %idxprom2 = sext i32 %add1 to i64 4260 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4261 %1 = load i64, i64* %arrayidx3, align 8 4262 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4263 ret <2 x i64> %vecinit4 4264} 4265 4266; Function Attrs: norecurse nounwind readnone 4267define <2 x i64> @spltRegValll(i64 %val) { 4268; P9BE-LABEL: spltRegValll: 4269; P9BE: # %bb.0: # %entry 4270; P9BE-NEXT: mtvsrdd v2, r3, r3 4271; P9BE-NEXT: blr 4272; 4273; P9LE-LABEL: spltRegValll: 4274; P9LE: # %bb.0: # %entry 4275; P9LE-NEXT: mtvsrdd v2, r3, r3 4276; P9LE-NEXT: blr 4277; 4278; P8BE-LABEL: spltRegValll: 4279; P8BE: # %bb.0: # %entry 4280; P8BE-NEXT: mtvsrd f0, r3 4281; P8BE-NEXT: xxspltd v2, vs0, 0 4282; P8BE-NEXT: blr 4283; 4284; P8LE-LABEL: spltRegValll: 4285; P8LE: # %bb.0: # %entry 4286; P8LE-NEXT: mtvsrd f0, r3 4287; P8LE-NEXT: xxspltd v2, vs0, 0 4288; P8LE-NEXT: blr 4289entry: 4290 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4291 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4292 ret <2 x i64> %splat.splat 4293} 4294 4295; Function Attrs: norecurse nounwind readonly 4296define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4297; P9BE-LABEL: spltMemValll: 4298; P9BE: # %bb.0: # %entry 4299; P9BE-NEXT: lxvdsx v2, 0, r3 4300; P9BE-NEXT: blr 4301; 4302; P9LE-LABEL: spltMemValll: 4303; P9LE: # %bb.0: # %entry 4304; P9LE-NEXT: lxvdsx v2, 0, r3 4305; P9LE-NEXT: blr 4306; 4307; P8BE-LABEL: spltMemValll: 4308; P8BE: # %bb.0: # %entry 4309; P8BE-NEXT: lxvdsx v2, 0, r3 4310; P8BE-NEXT: blr 4311; 4312; P8LE-LABEL: spltMemValll: 4313; P8LE: # %bb.0: # %entry 4314; P8LE-NEXT: lxvdsx v2, 0, r3 4315; P8LE-NEXT: blr 4316entry: 4317 %0 = load i64, i64* %ptr, align 8 4318 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4319 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4320 ret <2 x i64> %splat.splat 4321} 4322 4323; Function Attrs: norecurse nounwind readnone 4324define <2 x i64> @spltCnstConvftoll() { 4325; P9BE-LABEL: spltCnstConvftoll: 4326; P9BE: # %bb.0: # %entry 4327; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4328; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4329; P9BE-NEXT: lxvx v2, 0, r3 4330; P9BE-NEXT: blr 4331; 4332; P9LE-LABEL: spltCnstConvftoll: 4333; P9LE: # %bb.0: # %entry 4334; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4335; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4336; P9LE-NEXT: lxvx v2, 0, r3 4337; P9LE-NEXT: blr 4338; 4339; P8BE-LABEL: spltCnstConvftoll: 4340; P8BE: # %bb.0: # %entry 4341; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4342; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4343; P8BE-NEXT: lxvd2x v2, 0, r3 4344; P8BE-NEXT: blr 4345; 4346; P8LE-LABEL: spltCnstConvftoll: 4347; P8LE: # %bb.0: # %entry 4348; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4349; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4350; P8LE-NEXT: lxvd2x vs0, 0, r3 4351; P8LE-NEXT: xxswapd v2, vs0 4352; P8LE-NEXT: blr 4353entry: 4354 ret <2 x i64> <i64 4, i64 4> 4355} 4356 4357; Function Attrs: norecurse nounwind readnone 4358define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4359; P9BE-LABEL: fromRegsConvftoll: 4360; P9BE: # %bb.0: # %entry 4361; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4362; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4363; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4364; P9BE-NEXT: xvcvdpsxds v2, vs0 4365; P9BE-NEXT: blr 4366; 4367; P9LE-LABEL: fromRegsConvftoll: 4368; P9LE: # %bb.0: # %entry 4369; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4370; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4371; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4372; P9LE-NEXT: xvcvdpsxds v2, vs0 4373; P9LE-NEXT: blr 4374; 4375; P8BE-LABEL: fromRegsConvftoll: 4376; P8BE: # %bb.0: # %entry 4377; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4378; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4379; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4380; P8BE-NEXT: xvcvdpsxds v2, vs0 4381; P8BE-NEXT: blr 4382; 4383; P8LE-LABEL: fromRegsConvftoll: 4384; P8LE: # %bb.0: # %entry 4385; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4386; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4387; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4388; P8LE-NEXT: xvcvdpsxds v2, vs0 4389; P8LE-NEXT: blr 4390entry: 4391 %conv = fptosi float %a to i64 4392 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4393 %conv1 = fptosi float %b to i64 4394 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4395 ret <2 x i64> %vecinit2 4396} 4397 4398; Function Attrs: norecurse nounwind readnone 4399define <2 x i64> @fromDiffConstsConvftoll() { 4400; P9BE-LABEL: fromDiffConstsConvftoll: 4401; P9BE: # %bb.0: # %entry 4402; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4403; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4404; P9BE-NEXT: lxvx v2, 0, r3 4405; P9BE-NEXT: blr 4406; 4407; P9LE-LABEL: fromDiffConstsConvftoll: 4408; P9LE: # %bb.0: # %entry 4409; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4410; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4411; P9LE-NEXT: lxvx v2, 0, r3 4412; P9LE-NEXT: blr 4413; 4414; P8BE-LABEL: fromDiffConstsConvftoll: 4415; P8BE: # %bb.0: # %entry 4416; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4417; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4418; P8BE-NEXT: lxvd2x v2, 0, r3 4419; P8BE-NEXT: blr 4420; 4421; P8LE-LABEL: fromDiffConstsConvftoll: 4422; P8LE: # %bb.0: # %entry 4423; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4424; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4425; P8LE-NEXT: lxvd2x vs0, 0, r3 4426; P8LE-NEXT: xxswapd v2, vs0 4427; P8LE-NEXT: blr 4428entry: 4429 ret <2 x i64> <i64 24, i64 234> 4430} 4431 4432; Function Attrs: norecurse nounwind readonly 4433define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4434; P9BE-LABEL: fromDiffMemConsAConvftoll: 4435; P9BE: # %bb.0: # %entry 4436; P9BE-NEXT: lfs f0, 0(r3) 4437; P9BE-NEXT: lfs f1, 4(r3) 4438; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4439; P9BE-NEXT: xvcvdpsxds v2, vs0 4440; P9BE-NEXT: blr 4441; 4442; P9LE-LABEL: fromDiffMemConsAConvftoll: 4443; P9LE: # %bb.0: # %entry 4444; P9LE-NEXT: lfs f0, 0(r3) 4445; P9LE-NEXT: lfs f1, 4(r3) 4446; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4447; P9LE-NEXT: xvcvdpsxds v2, vs0 4448; P9LE-NEXT: blr 4449; 4450; P8BE-LABEL: fromDiffMemConsAConvftoll: 4451; P8BE: # %bb.0: # %entry 4452; P8BE-NEXT: lfsx f0, 0, r3 4453; P8BE-NEXT: lfs f1, 4(r3) 4454; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4455; P8BE-NEXT: xvcvdpsxds v2, vs0 4456; P8BE-NEXT: blr 4457; 4458; P8LE-LABEL: fromDiffMemConsAConvftoll: 4459; P8LE: # %bb.0: # %entry 4460; P8LE-NEXT: lfsx f0, 0, r3 4461; P8LE-NEXT: lfs f1, 4(r3) 4462; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4463; P8LE-NEXT: xvcvdpsxds v2, vs0 4464; P8LE-NEXT: blr 4465entry: 4466 %0 = load float, float* %ptr, align 4 4467 %conv = fptosi float %0 to i64 4468 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4469 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4470 %1 = load float, float* %arrayidx1, align 4 4471 %conv2 = fptosi float %1 to i64 4472 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4473 ret <2 x i64> %vecinit3 4474} 4475 4476; Function Attrs: norecurse nounwind readonly 4477define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4478; P9BE-LABEL: fromDiffMemConsDConvftoll: 4479; P9BE: # %bb.0: # %entry 4480; P9BE-NEXT: lfs f0, 12(r3) 4481; P9BE-NEXT: lfs f1, 8(r3) 4482; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4483; P9BE-NEXT: xvcvdpsxds v2, vs0 4484; P9BE-NEXT: blr 4485; 4486; P9LE-LABEL: fromDiffMemConsDConvftoll: 4487; P9LE: # %bb.0: # %entry 4488; P9LE-NEXT: lfs f0, 12(r3) 4489; P9LE-NEXT: lfs f1, 8(r3) 4490; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4491; P9LE-NEXT: xvcvdpsxds v2, vs0 4492; P9LE-NEXT: blr 4493; 4494; P8BE-LABEL: fromDiffMemConsDConvftoll: 4495; P8BE: # %bb.0: # %entry 4496; P8BE-NEXT: lfs f0, 12(r3) 4497; P8BE-NEXT: lfs f1, 8(r3) 4498; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4499; P8BE-NEXT: xvcvdpsxds v2, vs0 4500; P8BE-NEXT: blr 4501; 4502; P8LE-LABEL: fromDiffMemConsDConvftoll: 4503; P8LE: # %bb.0: # %entry 4504; P8LE-NEXT: lfs f0, 12(r3) 4505; P8LE-NEXT: lfs f1, 8(r3) 4506; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4507; P8LE-NEXT: xvcvdpsxds v2, vs0 4508; P8LE-NEXT: blr 4509entry: 4510 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4511 %0 = load float, float* %arrayidx, align 4 4512 %conv = fptosi float %0 to i64 4513 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4514 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4515 %1 = load float, float* %arrayidx1, align 4 4516 %conv2 = fptosi float %1 to i64 4517 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4518 ret <2 x i64> %vecinit3 4519} 4520 4521; Function Attrs: norecurse nounwind readonly 4522define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4523; P9BE-LABEL: fromDiffMemVarAConvftoll: 4524; P9BE: # %bb.0: # %entry 4525; P9BE-NEXT: sldi r4, r4, 2 4526; P9BE-NEXT: lfsux f0, r3, r4 4527; P9BE-NEXT: lfs f1, 4(r3) 4528; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4529; P9BE-NEXT: xvcvdpsxds v2, vs0 4530; P9BE-NEXT: blr 4531; 4532; P9LE-LABEL: fromDiffMemVarAConvftoll: 4533; P9LE: # %bb.0: # %entry 4534; P9LE-NEXT: sldi r4, r4, 2 4535; P9LE-NEXT: lfsux f0, r3, r4 4536; P9LE-NEXT: lfs f1, 4(r3) 4537; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4538; P9LE-NEXT: xvcvdpsxds v2, vs0 4539; P9LE-NEXT: blr 4540; 4541; P8BE-LABEL: fromDiffMemVarAConvftoll: 4542; P8BE: # %bb.0: # %entry 4543; P8BE-NEXT: sldi r4, r4, 2 4544; P8BE-NEXT: lfsux f0, r3, r4 4545; P8BE-NEXT: lfs f1, 4(r3) 4546; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4547; P8BE-NEXT: xvcvdpsxds v2, vs0 4548; P8BE-NEXT: blr 4549; 4550; P8LE-LABEL: fromDiffMemVarAConvftoll: 4551; P8LE: # %bb.0: # %entry 4552; P8LE-NEXT: sldi r4, r4, 2 4553; P8LE-NEXT: lfsux f0, r3, r4 4554; P8LE-NEXT: lfs f1, 4(r3) 4555; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4556; P8LE-NEXT: xvcvdpsxds v2, vs0 4557; P8LE-NEXT: blr 4558entry: 4559 %idxprom = sext i32 %elem to i64 4560 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4561 %0 = load float, float* %arrayidx, align 4 4562 %conv = fptosi float %0 to i64 4563 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4564 %add = add nsw i32 %elem, 1 4565 %idxprom1 = sext i32 %add to i64 4566 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4567 %1 = load float, float* %arrayidx2, align 4 4568 %conv3 = fptosi float %1 to i64 4569 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4570 ret <2 x i64> %vecinit4 4571} 4572 4573; Function Attrs: norecurse nounwind readonly 4574define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4575; P9BE-LABEL: fromDiffMemVarDConvftoll: 4576; P9BE: # %bb.0: # %entry 4577; P9BE-NEXT: sldi r4, r4, 2 4578; P9BE-NEXT: lfsux f0, r3, r4 4579; P9BE-NEXT: lfs f1, -4(r3) 4580; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4581; P9BE-NEXT: xvcvdpsxds v2, vs0 4582; P9BE-NEXT: blr 4583; 4584; P9LE-LABEL: fromDiffMemVarDConvftoll: 4585; P9LE: # %bb.0: # %entry 4586; P9LE-NEXT: sldi r4, r4, 2 4587; P9LE-NEXT: lfsux f0, r3, r4 4588; P9LE-NEXT: lfs f1, -4(r3) 4589; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4590; P9LE-NEXT: xvcvdpsxds v2, vs0 4591; P9LE-NEXT: blr 4592; 4593; P8BE-LABEL: fromDiffMemVarDConvftoll: 4594; P8BE: # %bb.0: # %entry 4595; P8BE-NEXT: sldi r4, r4, 2 4596; P8BE-NEXT: lfsux f0, r3, r4 4597; P8BE-NEXT: lfs f1, -4(r3) 4598; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4599; P8BE-NEXT: xvcvdpsxds v2, vs0 4600; P8BE-NEXT: blr 4601; 4602; P8LE-LABEL: fromDiffMemVarDConvftoll: 4603; P8LE: # %bb.0: # %entry 4604; P8LE-NEXT: sldi r4, r4, 2 4605; P8LE-NEXT: lfsux f0, r3, r4 4606; P8LE-NEXT: lfs f1, -4(r3) 4607; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4608; P8LE-NEXT: xvcvdpsxds v2, vs0 4609; P8LE-NEXT: blr 4610entry: 4611 %idxprom = sext i32 %elem to i64 4612 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4613 %0 = load float, float* %arrayidx, align 4 4614 %conv = fptosi float %0 to i64 4615 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4616 %sub = add nsw i32 %elem, -1 4617 %idxprom1 = sext i32 %sub to i64 4618 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4619 %1 = load float, float* %arrayidx2, align 4 4620 %conv3 = fptosi float %1 to i64 4621 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4622 ret <2 x i64> %vecinit4 4623} 4624 4625; Function Attrs: norecurse nounwind readnone 4626define <2 x i64> @spltRegValConvftoll(float %val) { 4627; P9BE-LABEL: spltRegValConvftoll: 4628; P9BE: # %bb.0: # %entry 4629; P9BE-NEXT: xscvdpsxds f0, f1 4630; P9BE-NEXT: xxspltd v2, f0, 0 4631; P9BE-NEXT: blr 4632; 4633; P9LE-LABEL: spltRegValConvftoll: 4634; P9LE: # %bb.0: # %entry 4635; P9LE-NEXT: xscvdpsxds f0, f1 4636; P9LE-NEXT: xxspltd v2, f0, 0 4637; P9LE-NEXT: blr 4638; 4639; P8BE-LABEL: spltRegValConvftoll: 4640; P8BE: # %bb.0: # %entry 4641; P8BE-NEXT: xscvdpsxds f0, f1 4642; P8BE-NEXT: xxspltd v2, f0, 0 4643; P8BE-NEXT: blr 4644; 4645; P8LE-LABEL: spltRegValConvftoll: 4646; P8LE: # %bb.0: # %entry 4647; P8LE-NEXT: xscvdpsxds f0, f1 4648; P8LE-NEXT: xxspltd v2, f0, 0 4649; P8LE-NEXT: blr 4650entry: 4651 %conv = fptosi float %val to i64 4652 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4653 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4654 ret <2 x i64> %splat.splat 4655} 4656 4657; Function Attrs: norecurse nounwind readonly 4658define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4659; P9BE-LABEL: spltMemValConvftoll: 4660; P9BE: # %bb.0: # %entry 4661; P9BE-NEXT: lfs f0, 0(r3) 4662; P9BE-NEXT: xscvdpsxds f0, f0 4663; P9BE-NEXT: xxspltd v2, f0, 0 4664; P9BE-NEXT: blr 4665; 4666; P9LE-LABEL: spltMemValConvftoll: 4667; P9LE: # %bb.0: # %entry 4668; P9LE-NEXT: lfs f0, 0(r3) 4669; P9LE-NEXT: xscvdpsxds f0, f0 4670; P9LE-NEXT: xxspltd v2, f0, 0 4671; P9LE-NEXT: blr 4672; 4673; P8BE-LABEL: spltMemValConvftoll: 4674; P8BE: # %bb.0: # %entry 4675; P8BE-NEXT: lfsx f0, 0, r3 4676; P8BE-NEXT: xscvdpsxds f0, f0 4677; P8BE-NEXT: xxspltd v2, f0, 0 4678; P8BE-NEXT: blr 4679; 4680; P8LE-LABEL: spltMemValConvftoll: 4681; P8LE: # %bb.0: # %entry 4682; P8LE-NEXT: lfsx f0, 0, r3 4683; P8LE-NEXT: xscvdpsxds f0, f0 4684; P8LE-NEXT: xxspltd v2, f0, 0 4685; P8LE-NEXT: blr 4686entry: 4687 %0 = load float, float* %ptr, align 4 4688 %conv = fptosi float %0 to i64 4689 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4690 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4691 ret <2 x i64> %splat.splat 4692} 4693 4694; Function Attrs: norecurse nounwind readnone 4695define <2 x i64> @spltCnstConvdtoll() { 4696; P9BE-LABEL: spltCnstConvdtoll: 4697; P9BE: # %bb.0: # %entry 4698; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4699; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4700; P9BE-NEXT: lxvx v2, 0, r3 4701; P9BE-NEXT: blr 4702; 4703; P9LE-LABEL: spltCnstConvdtoll: 4704; P9LE: # %bb.0: # %entry 4705; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4706; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4707; P9LE-NEXT: lxvx v2, 0, r3 4708; P9LE-NEXT: blr 4709; 4710; P8BE-LABEL: spltCnstConvdtoll: 4711; P8BE: # %bb.0: # %entry 4712; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4713; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4714; P8BE-NEXT: lxvd2x v2, 0, r3 4715; P8BE-NEXT: blr 4716; 4717; P8LE-LABEL: spltCnstConvdtoll: 4718; P8LE: # %bb.0: # %entry 4719; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4720; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4721; P8LE-NEXT: lxvd2x vs0, 0, r3 4722; P8LE-NEXT: xxswapd v2, vs0 4723; P8LE-NEXT: blr 4724entry: 4725 ret <2 x i64> <i64 4, i64 4> 4726} 4727 4728; Function Attrs: norecurse nounwind readnone 4729define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4730; P9BE-LABEL: fromRegsConvdtoll: 4731; P9BE: # %bb.0: # %entry 4732; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4733; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4734; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4735; P9BE-NEXT: xvcvdpsxds v2, vs0 4736; P9BE-NEXT: blr 4737; 4738; P9LE-LABEL: fromRegsConvdtoll: 4739; P9LE: # %bb.0: # %entry 4740; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4741; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4742; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4743; P9LE-NEXT: xvcvdpsxds v2, vs0 4744; P9LE-NEXT: blr 4745; 4746; P8BE-LABEL: fromRegsConvdtoll: 4747; P8BE: # %bb.0: # %entry 4748; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4749; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4750; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4751; P8BE-NEXT: xvcvdpsxds v2, vs0 4752; P8BE-NEXT: blr 4753; 4754; P8LE-LABEL: fromRegsConvdtoll: 4755; P8LE: # %bb.0: # %entry 4756; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4757; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4758; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4759; P8LE-NEXT: xvcvdpsxds v2, vs0 4760; P8LE-NEXT: blr 4761entry: 4762 %conv = fptosi double %a to i64 4763 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4764 %conv1 = fptosi double %b to i64 4765 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4766 ret <2 x i64> %vecinit2 4767} 4768 4769; Function Attrs: norecurse nounwind readnone 4770define <2 x i64> @fromDiffConstsConvdtoll() { 4771; P9BE-LABEL: fromDiffConstsConvdtoll: 4772; P9BE: # %bb.0: # %entry 4773; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4774; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4775; P9BE-NEXT: lxvx v2, 0, r3 4776; P9BE-NEXT: blr 4777; 4778; P9LE-LABEL: fromDiffConstsConvdtoll: 4779; P9LE: # %bb.0: # %entry 4780; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4781; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4782; P9LE-NEXT: lxvx v2, 0, r3 4783; P9LE-NEXT: blr 4784; 4785; P8BE-LABEL: fromDiffConstsConvdtoll: 4786; P8BE: # %bb.0: # %entry 4787; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4788; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4789; P8BE-NEXT: lxvd2x v2, 0, r3 4790; P8BE-NEXT: blr 4791; 4792; P8LE-LABEL: fromDiffConstsConvdtoll: 4793; P8LE: # %bb.0: # %entry 4794; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4795; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4796; P8LE-NEXT: lxvd2x vs0, 0, r3 4797; P8LE-NEXT: xxswapd v2, vs0 4798; P8LE-NEXT: blr 4799entry: 4800 ret <2 x i64> <i64 24, i64 234> 4801} 4802 4803; Function Attrs: norecurse nounwind readonly 4804define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4805; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4806; P9BE: # %bb.0: # %entry 4807; P9BE-NEXT: lxv vs0, 0(r3) 4808; P9BE-NEXT: xvcvdpsxds v2, vs0 4809; P9BE-NEXT: blr 4810; 4811; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4812; P9LE: # %bb.0: # %entry 4813; P9LE-NEXT: lxv vs0, 0(r3) 4814; P9LE-NEXT: xvcvdpsxds v2, vs0 4815; P9LE-NEXT: blr 4816; 4817; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4818; P8BE: # %bb.0: # %entry 4819; P8BE-NEXT: lxvd2x vs0, 0, r3 4820; P8BE-NEXT: xvcvdpsxds v2, vs0 4821; P8BE-NEXT: blr 4822; 4823; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4824; P8LE: # %bb.0: # %entry 4825; P8LE-NEXT: lxvd2x vs0, 0, r3 4826; P8LE-NEXT: xxswapd vs0, vs0 4827; P8LE-NEXT: xvcvdpsxds v2, vs0 4828; P8LE-NEXT: blr 4829entry: 4830 %0 = bitcast double* %ptr to <2 x double>* 4831 %1 = load <2 x double>, <2 x double>* %0, align 8 4832 %2 = fptosi <2 x double> %1 to <2 x i64> 4833 ret <2 x i64> %2 4834} 4835 4836; Function Attrs: norecurse nounwind readonly 4837define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4838; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4839; P9BE: # %bb.0: # %entry 4840; P9BE-NEXT: lxv vs0, 16(r3) 4841; P9BE-NEXT: xxswapd vs0, vs0 4842; P9BE-NEXT: xvcvdpsxds v2, vs0 4843; P9BE-NEXT: blr 4844; 4845; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4846; P9LE: # %bb.0: # %entry 4847; P9LE-NEXT: addi r3, r3, 16 4848; P9LE-NEXT: lxvd2x vs0, 0, r3 4849; P9LE-NEXT: xvcvdpsxds v2, vs0 4850; P9LE-NEXT: blr 4851; 4852; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4853; P8BE: # %bb.0: # %entry 4854; P8BE-NEXT: addi r3, r3, 16 4855; P8BE-NEXT: lxvd2x vs0, 0, r3 4856; P8BE-NEXT: xxswapd vs0, vs0 4857; P8BE-NEXT: xvcvdpsxds v2, vs0 4858; P8BE-NEXT: blr 4859; 4860; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4861; P8LE: # %bb.0: # %entry 4862; P8LE-NEXT: addi r3, r3, 16 4863; P8LE-NEXT: lxvd2x vs0, 0, r3 4864; P8LE-NEXT: xvcvdpsxds v2, vs0 4865; P8LE-NEXT: blr 4866entry: 4867 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4868 %0 = load double, double* %arrayidx, align 8 4869 %conv = fptosi double %0 to i64 4870 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4871 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4872 %1 = load double, double* %arrayidx1, align 8 4873 %conv2 = fptosi double %1 to i64 4874 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4875 ret <2 x i64> %vecinit3 4876} 4877 4878; Function Attrs: norecurse nounwind readonly 4879define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4880; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4881; P9BE: # %bb.0: # %entry 4882; P9BE-NEXT: sldi r4, r4, 3 4883; P9BE-NEXT: lxvx vs0, r3, r4 4884; P9BE-NEXT: xvcvdpsxds v2, vs0 4885; P9BE-NEXT: blr 4886; 4887; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4888; P9LE: # %bb.0: # %entry 4889; P9LE-NEXT: sldi r4, r4, 3 4890; P9LE-NEXT: lxvx vs0, r3, r4 4891; P9LE-NEXT: xvcvdpsxds v2, vs0 4892; P9LE-NEXT: blr 4893; 4894; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4895; P8BE: # %bb.0: # %entry 4896; P8BE-NEXT: sldi r4, r4, 3 4897; P8BE-NEXT: lxvd2x vs0, r3, r4 4898; P8BE-NEXT: xvcvdpsxds v2, vs0 4899; P8BE-NEXT: blr 4900; 4901; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4902; P8LE: # %bb.0: # %entry 4903; P8LE-NEXT: sldi r4, r4, 3 4904; P8LE-NEXT: lxvd2x vs0, r3, r4 4905; P8LE-NEXT: xxswapd vs0, vs0 4906; P8LE-NEXT: xvcvdpsxds v2, vs0 4907; P8LE-NEXT: blr 4908entry: 4909 %idxprom = sext i32 %elem to i64 4910 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4911 %0 = load double, double* %arrayidx, align 8 4912 %conv = fptosi double %0 to i64 4913 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4914 %add = add nsw i32 %elem, 1 4915 %idxprom1 = sext i32 %add to i64 4916 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4917 %1 = load double, double* %arrayidx2, align 8 4918 %conv3 = fptosi double %1 to i64 4919 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4920 ret <2 x i64> %vecinit4 4921} 4922 4923; Function Attrs: norecurse nounwind readonly 4924define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4925; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4926; P9BE: # %bb.0: # %entry 4927; P9BE-NEXT: sldi r4, r4, 3 4928; P9BE-NEXT: add r3, r3, r4 4929; P9BE-NEXT: li r4, -8 4930; P9BE-NEXT: lxvx vs0, r3, r4 4931; P9BE-NEXT: xxswapd vs0, vs0 4932; P9BE-NEXT: xvcvdpsxds v2, vs0 4933; P9BE-NEXT: blr 4934; 4935; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4936; P9LE: # %bb.0: # %entry 4937; P9LE-NEXT: sldi r4, r4, 3 4938; P9LE-NEXT: add r3, r3, r4 4939; P9LE-NEXT: addi r3, r3, -8 4940; P9LE-NEXT: lxvd2x vs0, 0, r3 4941; P9LE-NEXT: xvcvdpsxds v2, vs0 4942; P9LE-NEXT: blr 4943; 4944; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4945; P8BE: # %bb.0: # %entry 4946; P8BE-NEXT: sldi r4, r4, 3 4947; P8BE-NEXT: add r3, r3, r4 4948; P8BE-NEXT: addi r3, r3, -8 4949; P8BE-NEXT: lxvd2x vs0, 0, r3 4950; P8BE-NEXT: xxswapd vs0, vs0 4951; P8BE-NEXT: xvcvdpsxds v2, vs0 4952; P8BE-NEXT: blr 4953; 4954; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4955; P8LE: # %bb.0: # %entry 4956; P8LE-NEXT: sldi r4, r4, 3 4957; P8LE-NEXT: add r3, r3, r4 4958; P8LE-NEXT: addi r3, r3, -8 4959; P8LE-NEXT: lxvd2x vs0, 0, r3 4960; P8LE-NEXT: xvcvdpsxds v2, vs0 4961; P8LE-NEXT: blr 4962entry: 4963 %idxprom = sext i32 %elem to i64 4964 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4965 %0 = load double, double* %arrayidx, align 8 4966 %conv = fptosi double %0 to i64 4967 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4968 %sub = add nsw i32 %elem, -1 4969 %idxprom1 = sext i32 %sub to i64 4970 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4971 %1 = load double, double* %arrayidx2, align 8 4972 %conv3 = fptosi double %1 to i64 4973 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4974 ret <2 x i64> %vecinit4 4975} 4976 4977; Function Attrs: norecurse nounwind readnone 4978define <2 x i64> @spltRegValConvdtoll(double %val) { 4979; P9BE-LABEL: spltRegValConvdtoll: 4980; P9BE: # %bb.0: # %entry 4981; P9BE-NEXT: xscvdpsxds f0, f1 4982; P9BE-NEXT: xxspltd v2, vs0, 0 4983; P9BE-NEXT: blr 4984; 4985; P9LE-LABEL: spltRegValConvdtoll: 4986; P9LE: # %bb.0: # %entry 4987; P9LE-NEXT: xscvdpsxds f0, f1 4988; P9LE-NEXT: xxspltd v2, vs0, 0 4989; P9LE-NEXT: blr 4990; 4991; P8BE-LABEL: spltRegValConvdtoll: 4992; P8BE: # %bb.0: # %entry 4993; P8BE-NEXT: xscvdpsxds f0, f1 4994; P8BE-NEXT: xxspltd v2, vs0, 0 4995; P8BE-NEXT: blr 4996; 4997; P8LE-LABEL: spltRegValConvdtoll: 4998; P8LE: # %bb.0: # %entry 4999; P8LE-NEXT: xscvdpsxds f0, f1 5000; P8LE-NEXT: xxspltd v2, vs0, 0 5001; P8LE-NEXT: blr 5002entry: 5003 %conv = fptosi double %val to i64 5004 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5005 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5006 ret <2 x i64> %splat.splat 5007} 5008 5009; Function Attrs: norecurse nounwind readonly 5010define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 5011; P9BE-LABEL: spltMemValConvdtoll: 5012; P9BE: # %bb.0: # %entry 5013; P9BE-NEXT: lxvdsx vs0, 0, r3 5014; P9BE-NEXT: xvcvdpsxds v2, vs0 5015; P9BE-NEXT: blr 5016; 5017; P9LE-LABEL: spltMemValConvdtoll: 5018; P9LE: # %bb.0: # %entry 5019; P9LE-NEXT: lxvdsx vs0, 0, r3 5020; P9LE-NEXT: xvcvdpsxds v2, vs0 5021; P9LE-NEXT: blr 5022; 5023; P8BE-LABEL: spltMemValConvdtoll: 5024; P8BE: # %bb.0: # %entry 5025; P8BE-NEXT: lxvdsx vs0, 0, r3 5026; P8BE-NEXT: xvcvdpsxds v2, vs0 5027; P8BE-NEXT: blr 5028; 5029; P8LE-LABEL: spltMemValConvdtoll: 5030; P8LE: # %bb.0: # %entry 5031; P8LE-NEXT: lxvdsx vs0, 0, r3 5032; P8LE-NEXT: xvcvdpsxds v2, vs0 5033; P8LE-NEXT: blr 5034entry: 5035 %0 = load double, double* %ptr, align 8 5036 %conv = fptosi double %0 to i64 5037 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5038 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5039 ret <2 x i64> %splat.splat 5040} 5041 5042; Function Attrs: norecurse nounwind readnone 5043define <2 x i64> @allZeroull() { 5044; P9BE-LABEL: allZeroull: 5045; P9BE: # %bb.0: # %entry 5046; P9BE-NEXT: xxlxor v2, v2, v2 5047; P9BE-NEXT: blr 5048; 5049; P9LE-LABEL: allZeroull: 5050; P9LE: # %bb.0: # %entry 5051; P9LE-NEXT: xxlxor v2, v2, v2 5052; P9LE-NEXT: blr 5053; 5054; P8BE-LABEL: allZeroull: 5055; P8BE: # %bb.0: # %entry 5056; P8BE-NEXT: xxlxor v2, v2, v2 5057; P8BE-NEXT: blr 5058; 5059; P8LE-LABEL: allZeroull: 5060; P8LE: # %bb.0: # %entry 5061; P8LE-NEXT: xxlxor v2, v2, v2 5062; P8LE-NEXT: blr 5063entry: 5064 ret <2 x i64> zeroinitializer 5065} 5066 5067; Function Attrs: norecurse nounwind readnone 5068define <2 x i64> @spltConst1ull() { 5069; P9BE-LABEL: spltConst1ull: 5070; P9BE: # %bb.0: # %entry 5071; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5072; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5073; P9BE-NEXT: lxvx v2, 0, r3 5074; P9BE-NEXT: blr 5075; 5076; P9LE-LABEL: spltConst1ull: 5077; P9LE: # %bb.0: # %entry 5078; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5079; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5080; P9LE-NEXT: lxvx v2, 0, r3 5081; P9LE-NEXT: blr 5082; 5083; P8BE-LABEL: spltConst1ull: 5084; P8BE: # %bb.0: # %entry 5085; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5086; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5087; P8BE-NEXT: lxvd2x v2, 0, r3 5088; P8BE-NEXT: blr 5089; 5090; P8LE-LABEL: spltConst1ull: 5091; P8LE: # %bb.0: # %entry 5092; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5093; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5094; P8LE-NEXT: lxvd2x vs0, 0, r3 5095; P8LE-NEXT: xxswapd v2, vs0 5096; P8LE-NEXT: blr 5097entry: 5098 ret <2 x i64> <i64 1, i64 1> 5099} 5100 5101; Function Attrs: norecurse nounwind readnone 5102define <2 x i64> @spltConst16kull() { 5103; P9BE-LABEL: spltConst16kull: 5104; P9BE: # %bb.0: # %entry 5105; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5106; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5107; P9BE-NEXT: lxvx v2, 0, r3 5108; P9BE-NEXT: blr 5109; 5110; P9LE-LABEL: spltConst16kull: 5111; P9LE: # %bb.0: # %entry 5112; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5113; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5114; P9LE-NEXT: lxvx v2, 0, r3 5115; P9LE-NEXT: blr 5116; 5117; P8BE-LABEL: spltConst16kull: 5118; P8BE: # %bb.0: # %entry 5119; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5120; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5121; P8BE-NEXT: lxvd2x v2, 0, r3 5122; P8BE-NEXT: blr 5123; 5124; P8LE-LABEL: spltConst16kull: 5125; P8LE: # %bb.0: # %entry 5126; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5127; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5128; P8LE-NEXT: lxvd2x vs0, 0, r3 5129; P8LE-NEXT: xxswapd v2, vs0 5130; P8LE-NEXT: blr 5131entry: 5132 ret <2 x i64> <i64 32767, i64 32767> 5133} 5134 5135; Function Attrs: norecurse nounwind readnone 5136define <2 x i64> @spltConst32kull() { 5137; P9BE-LABEL: spltConst32kull: 5138; P9BE: # %bb.0: # %entry 5139; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5140; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5141; P9BE-NEXT: lxvx v2, 0, r3 5142; P9BE-NEXT: blr 5143; 5144; P9LE-LABEL: spltConst32kull: 5145; P9LE: # %bb.0: # %entry 5146; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5147; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5148; P9LE-NEXT: lxvx v2, 0, r3 5149; P9LE-NEXT: blr 5150; 5151; P8BE-LABEL: spltConst32kull: 5152; P8BE: # %bb.0: # %entry 5153; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5154; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5155; P8BE-NEXT: lxvd2x v2, 0, r3 5156; P8BE-NEXT: blr 5157; 5158; P8LE-LABEL: spltConst32kull: 5159; P8LE: # %bb.0: # %entry 5160; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5161; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5162; P8LE-NEXT: lxvd2x vs0, 0, r3 5163; P8LE-NEXT: xxswapd v2, vs0 5164; P8LE-NEXT: blr 5165entry: 5166 ret <2 x i64> <i64 65535, i64 65535> 5167} 5168 5169; Function Attrs: norecurse nounwind readnone 5170define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5171; P9BE-LABEL: fromRegsull: 5172; P9BE: # %bb.0: # %entry 5173; P9BE-NEXT: mtvsrdd v2, r3, r4 5174; P9BE-NEXT: blr 5175; 5176; P9LE-LABEL: fromRegsull: 5177; P9LE: # %bb.0: # %entry 5178; P9LE-NEXT: mtvsrdd v2, r4, r3 5179; P9LE-NEXT: blr 5180; 5181; P8BE-LABEL: fromRegsull: 5182; P8BE: # %bb.0: # %entry 5183; P8BE-NEXT: mtvsrd f0, r4 5184; P8BE-NEXT: mtvsrd f1, r3 5185; P8BE-NEXT: xxmrghd v2, vs1, vs0 5186; P8BE-NEXT: blr 5187; 5188; P8LE-LABEL: fromRegsull: 5189; P8LE: # %bb.0: # %entry 5190; P8LE-NEXT: mtvsrd f0, r3 5191; P8LE-NEXT: mtvsrd f1, r4 5192; P8LE-NEXT: xxmrghd v2, vs1, vs0 5193; P8LE-NEXT: blr 5194entry: 5195 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5196 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5197 ret <2 x i64> %vecinit1 5198} 5199 5200; Function Attrs: norecurse nounwind readnone 5201define <2 x i64> @fromDiffConstsull() { 5202; P9BE-LABEL: fromDiffConstsull: 5203; P9BE: # %bb.0: # %entry 5204; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5205; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5206; P9BE-NEXT: lxvx v2, 0, r3 5207; P9BE-NEXT: blr 5208; 5209; P9LE-LABEL: fromDiffConstsull: 5210; P9LE: # %bb.0: # %entry 5211; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5212; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5213; P9LE-NEXT: lxvx v2, 0, r3 5214; P9LE-NEXT: blr 5215; 5216; P8BE-LABEL: fromDiffConstsull: 5217; P8BE: # %bb.0: # %entry 5218; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5219; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5220; P8BE-NEXT: lxvd2x v2, 0, r3 5221; P8BE-NEXT: blr 5222; 5223; P8LE-LABEL: fromDiffConstsull: 5224; P8LE: # %bb.0: # %entry 5225; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5226; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5227; P8LE-NEXT: lxvd2x vs0, 0, r3 5228; P8LE-NEXT: xxswapd v2, vs0 5229; P8LE-NEXT: blr 5230entry: 5231 ret <2 x i64> <i64 242, i64 -113> 5232} 5233 5234; Function Attrs: norecurse nounwind readonly 5235define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5236; P9BE-LABEL: fromDiffMemConsAull: 5237; P9BE: # %bb.0: # %entry 5238; P9BE-NEXT: lxv v2, 0(r3) 5239; P9BE-NEXT: blr 5240; 5241; P9LE-LABEL: fromDiffMemConsAull: 5242; P9LE: # %bb.0: # %entry 5243; P9LE-NEXT: lxv v2, 0(r3) 5244; P9LE-NEXT: blr 5245; 5246; P8BE-LABEL: fromDiffMemConsAull: 5247; P8BE: # %bb.0: # %entry 5248; P8BE-NEXT: lxvd2x v2, 0, r3 5249; P8BE-NEXT: blr 5250; 5251; P8LE-LABEL: fromDiffMemConsAull: 5252; P8LE: # %bb.0: # %entry 5253; P8LE-NEXT: lxvd2x vs0, 0, r3 5254; P8LE-NEXT: xxswapd v2, vs0 5255; P8LE-NEXT: blr 5256entry: 5257 %0 = load i64, i64* %arr, align 8 5258 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5259 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5260 %1 = load i64, i64* %arrayidx1, align 8 5261 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5262 ret <2 x i64> %vecinit2 5263} 5264 5265; Function Attrs: norecurse nounwind readonly 5266define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5267; P9BE-LABEL: fromDiffMemConsDull: 5268; P9BE: # %bb.0: # %entry 5269; P9BE-NEXT: lxv v2, 16(r3) 5270; P9BE-NEXT: xxswapd v2, v2 5271; P9BE-NEXT: blr 5272; 5273; P9LE-LABEL: fromDiffMemConsDull: 5274; P9LE: # %bb.0: # %entry 5275; P9LE-NEXT: addi r3, r3, 16 5276; P9LE-NEXT: lxvd2x v2, 0, r3 5277; P9LE-NEXT: blr 5278; 5279; P8BE-LABEL: fromDiffMemConsDull: 5280; P8BE: # %bb.0: # %entry 5281; P8BE-NEXT: addi r3, r3, 16 5282; P8BE-NEXT: lxvd2x v2, 0, r3 5283; P8BE-NEXT: xxswapd v2, v2 5284; P8BE-NEXT: blr 5285; 5286; P8LE-LABEL: fromDiffMemConsDull: 5287; P8LE: # %bb.0: # %entry 5288; P8LE-NEXT: addi r3, r3, 16 5289; P8LE-NEXT: lxvd2x v2, 0, r3 5290; P8LE-NEXT: blr 5291entry: 5292 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5293 %0 = load i64, i64* %arrayidx, align 8 5294 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5295 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5296 %1 = load i64, i64* %arrayidx1, align 8 5297 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5298 ret <2 x i64> %vecinit2 5299} 5300 5301; Function Attrs: norecurse nounwind readonly 5302define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5303; P9BE-LABEL: fromDiffMemVarAull: 5304; P9BE: # %bb.0: # %entry 5305; P9BE-NEXT: sldi r4, r4, 3 5306; P9BE-NEXT: lxvx v2, r3, r4 5307; P9BE-NEXT: blr 5308; 5309; P9LE-LABEL: fromDiffMemVarAull: 5310; P9LE: # %bb.0: # %entry 5311; P9LE-NEXT: sldi r4, r4, 3 5312; P9LE-NEXT: lxvx v2, r3, r4 5313; P9LE-NEXT: blr 5314; 5315; P8BE-LABEL: fromDiffMemVarAull: 5316; P8BE: # %bb.0: # %entry 5317; P8BE-NEXT: sldi r4, r4, 3 5318; P8BE-NEXT: lxvd2x v2, r3, r4 5319; P8BE-NEXT: blr 5320; 5321; P8LE-LABEL: fromDiffMemVarAull: 5322; P8LE: # %bb.0: # %entry 5323; P8LE-NEXT: sldi r4, r4, 3 5324; P8LE-NEXT: lxvd2x vs0, r3, r4 5325; P8LE-NEXT: xxswapd v2, vs0 5326; P8LE-NEXT: blr 5327entry: 5328 %idxprom = sext i32 %elem to i64 5329 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5330 %0 = load i64, i64* %arrayidx, align 8 5331 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5332 %add = add nsw i32 %elem, 1 5333 %idxprom1 = sext i32 %add to i64 5334 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5335 %1 = load i64, i64* %arrayidx2, align 8 5336 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5337 ret <2 x i64> %vecinit3 5338} 5339 5340; Function Attrs: norecurse nounwind readonly 5341define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5342; P9BE-LABEL: fromDiffMemVarDull: 5343; P9BE: # %bb.0: # %entry 5344; P9BE-NEXT: sldi r4, r4, 3 5345; P9BE-NEXT: add r3, r3, r4 5346; P9BE-NEXT: li r4, -8 5347; P9BE-NEXT: lxvx v2, r3, r4 5348; P9BE-NEXT: xxswapd v2, v2 5349; P9BE-NEXT: blr 5350; 5351; P9LE-LABEL: fromDiffMemVarDull: 5352; P9LE: # %bb.0: # %entry 5353; P9LE-NEXT: sldi r4, r4, 3 5354; P9LE-NEXT: add r3, r3, r4 5355; P9LE-NEXT: addi r3, r3, -8 5356; P9LE-NEXT: lxvd2x v2, 0, r3 5357; P9LE-NEXT: blr 5358; 5359; P8BE-LABEL: fromDiffMemVarDull: 5360; P8BE: # %bb.0: # %entry 5361; P8BE-NEXT: sldi r4, r4, 3 5362; P8BE-NEXT: add r3, r3, r4 5363; P8BE-NEXT: addi r3, r3, -8 5364; P8BE-NEXT: lxvd2x v2, 0, r3 5365; P8BE-NEXT: xxswapd v2, v2 5366; P8BE-NEXT: blr 5367; 5368; P8LE-LABEL: fromDiffMemVarDull: 5369; P8LE: # %bb.0: # %entry 5370; P8LE-NEXT: sldi r4, r4, 3 5371; P8LE-NEXT: add r3, r3, r4 5372; P8LE-NEXT: addi r3, r3, -8 5373; P8LE-NEXT: lxvd2x v2, 0, r3 5374; P8LE-NEXT: blr 5375entry: 5376 %idxprom = sext i32 %elem to i64 5377 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5378 %0 = load i64, i64* %arrayidx, align 8 5379 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5380 %sub = add nsw i32 %elem, -1 5381 %idxprom1 = sext i32 %sub to i64 5382 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5383 %1 = load i64, i64* %arrayidx2, align 8 5384 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5385 ret <2 x i64> %vecinit3 5386} 5387 5388; Function Attrs: norecurse nounwind readonly 5389define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5390; P9BE-LABEL: fromRandMemConsull: 5391; P9BE: # %bb.0: # %entry 5392; P9BE-NEXT: ld r4, 32(r3) 5393; P9BE-NEXT: ld r3, 144(r3) 5394; P9BE-NEXT: mtvsrdd v2, r4, r3 5395; P9BE-NEXT: blr 5396; 5397; P9LE-LABEL: fromRandMemConsull: 5398; P9LE: # %bb.0: # %entry 5399; P9LE-NEXT: ld r4, 32(r3) 5400; P9LE-NEXT: ld r3, 144(r3) 5401; P9LE-NEXT: mtvsrdd v2, r3, r4 5402; P9LE-NEXT: blr 5403; 5404; P8BE-LABEL: fromRandMemConsull: 5405; P8BE: # %bb.0: # %entry 5406; P8BE-NEXT: ld r4, 144(r3) 5407; P8BE-NEXT: ld r3, 32(r3) 5408; P8BE-NEXT: mtvsrd f0, r4 5409; P8BE-NEXT: mtvsrd f1, r3 5410; P8BE-NEXT: xxmrghd v2, vs1, vs0 5411; P8BE-NEXT: blr 5412; 5413; P8LE-LABEL: fromRandMemConsull: 5414; P8LE: # %bb.0: # %entry 5415; P8LE-NEXT: ld r4, 32(r3) 5416; P8LE-NEXT: ld r3, 144(r3) 5417; P8LE-NEXT: mtvsrd f0, r4 5418; P8LE-NEXT: mtvsrd f1, r3 5419; P8LE-NEXT: xxmrghd v2, vs1, vs0 5420; P8LE-NEXT: blr 5421entry: 5422 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5423 %0 = load i64, i64* %arrayidx, align 8 5424 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5425 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5426 %1 = load i64, i64* %arrayidx1, align 8 5427 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5428 ret <2 x i64> %vecinit2 5429} 5430 5431; Function Attrs: norecurse nounwind readonly 5432define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5433; P9BE-LABEL: fromRandMemVarull: 5434; P9BE: # %bb.0: # %entry 5435; P9BE-NEXT: sldi r4, r4, 3 5436; P9BE-NEXT: add r3, r3, r4 5437; P9BE-NEXT: ld r4, 32(r3) 5438; P9BE-NEXT: ld r3, 8(r3) 5439; P9BE-NEXT: mtvsrdd v2, r4, r3 5440; P9BE-NEXT: blr 5441; 5442; P9LE-LABEL: fromRandMemVarull: 5443; P9LE: # %bb.0: # %entry 5444; P9LE-NEXT: sldi r4, r4, 3 5445; P9LE-NEXT: add r3, r3, r4 5446; P9LE-NEXT: ld r4, 32(r3) 5447; P9LE-NEXT: ld r3, 8(r3) 5448; P9LE-NEXT: mtvsrdd v2, r3, r4 5449; P9LE-NEXT: blr 5450; 5451; P8BE-LABEL: fromRandMemVarull: 5452; P8BE: # %bb.0: # %entry 5453; P8BE-NEXT: sldi r4, r4, 3 5454; P8BE-NEXT: add r3, r3, r4 5455; P8BE-NEXT: ld r4, 8(r3) 5456; P8BE-NEXT: ld r3, 32(r3) 5457; P8BE-NEXT: mtvsrd f0, r4 5458; P8BE-NEXT: mtvsrd f1, r3 5459; P8BE-NEXT: xxmrghd v2, vs1, vs0 5460; P8BE-NEXT: blr 5461; 5462; P8LE-LABEL: fromRandMemVarull: 5463; P8LE: # %bb.0: # %entry 5464; P8LE-NEXT: sldi r4, r4, 3 5465; P8LE-NEXT: add r3, r3, r4 5466; P8LE-NEXT: ld r4, 32(r3) 5467; P8LE-NEXT: ld r3, 8(r3) 5468; P8LE-NEXT: mtvsrd f0, r4 5469; P8LE-NEXT: mtvsrd f1, r3 5470; P8LE-NEXT: xxmrghd v2, vs1, vs0 5471; P8LE-NEXT: blr 5472entry: 5473 %add = add nsw i32 %elem, 4 5474 %idxprom = sext i32 %add to i64 5475 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5476 %0 = load i64, i64* %arrayidx, align 8 5477 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5478 %add1 = add nsw i32 %elem, 1 5479 %idxprom2 = sext i32 %add1 to i64 5480 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5481 %1 = load i64, i64* %arrayidx3, align 8 5482 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5483 ret <2 x i64> %vecinit4 5484} 5485 5486; Function Attrs: norecurse nounwind readnone 5487define <2 x i64> @spltRegValull(i64 %val) { 5488; P9BE-LABEL: spltRegValull: 5489; P9BE: # %bb.0: # %entry 5490; P9BE-NEXT: mtvsrdd v2, r3, r3 5491; P9BE-NEXT: blr 5492; 5493; P9LE-LABEL: spltRegValull: 5494; P9LE: # %bb.0: # %entry 5495; P9LE-NEXT: mtvsrdd v2, r3, r3 5496; P9LE-NEXT: blr 5497; 5498; P8BE-LABEL: spltRegValull: 5499; P8BE: # %bb.0: # %entry 5500; P8BE-NEXT: mtvsrd f0, r3 5501; P8BE-NEXT: xxspltd v2, vs0, 0 5502; P8BE-NEXT: blr 5503; 5504; P8LE-LABEL: spltRegValull: 5505; P8LE: # %bb.0: # %entry 5506; P8LE-NEXT: mtvsrd f0, r3 5507; P8LE-NEXT: xxspltd v2, vs0, 0 5508; P8LE-NEXT: blr 5509entry: 5510 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5511 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5512 ret <2 x i64> %splat.splat 5513} 5514 5515; Function Attrs: norecurse nounwind readonly 5516define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5517; P9BE-LABEL: spltMemValull: 5518; P9BE: # %bb.0: # %entry 5519; P9BE-NEXT: lxvdsx v2, 0, r3 5520; P9BE-NEXT: blr 5521; 5522; P9LE-LABEL: spltMemValull: 5523; P9LE: # %bb.0: # %entry 5524; P9LE-NEXT: lxvdsx v2, 0, r3 5525; P9LE-NEXT: blr 5526; 5527; P8BE-LABEL: spltMemValull: 5528; P8BE: # %bb.0: # %entry 5529; P8BE-NEXT: lxvdsx v2, 0, r3 5530; P8BE-NEXT: blr 5531; 5532; P8LE-LABEL: spltMemValull: 5533; P8LE: # %bb.0: # %entry 5534; P8LE-NEXT: lxvdsx v2, 0, r3 5535; P8LE-NEXT: blr 5536entry: 5537 %0 = load i64, i64* %ptr, align 8 5538 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5539 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5540 ret <2 x i64> %splat.splat 5541} 5542 5543; Function Attrs: norecurse nounwind readnone 5544define <2 x i64> @spltCnstConvftoull() { 5545; P9BE-LABEL: spltCnstConvftoull: 5546; P9BE: # %bb.0: # %entry 5547; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5548; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5549; P9BE-NEXT: lxvx v2, 0, r3 5550; P9BE-NEXT: blr 5551; 5552; P9LE-LABEL: spltCnstConvftoull: 5553; P9LE: # %bb.0: # %entry 5554; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5555; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5556; P9LE-NEXT: lxvx v2, 0, r3 5557; P9LE-NEXT: blr 5558; 5559; P8BE-LABEL: spltCnstConvftoull: 5560; P8BE: # %bb.0: # %entry 5561; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5562; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5563; P8BE-NEXT: lxvd2x v2, 0, r3 5564; P8BE-NEXT: blr 5565; 5566; P8LE-LABEL: spltCnstConvftoull: 5567; P8LE: # %bb.0: # %entry 5568; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5569; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5570; P8LE-NEXT: lxvd2x vs0, 0, r3 5571; P8LE-NEXT: xxswapd v2, vs0 5572; P8LE-NEXT: blr 5573entry: 5574 ret <2 x i64> <i64 4, i64 4> 5575} 5576 5577; Function Attrs: norecurse nounwind readnone 5578define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5579; P9BE-LABEL: fromRegsConvftoull: 5580; P9BE: # %bb.0: # %entry 5581; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5582; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5583; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5584; P9BE-NEXT: xvcvdpuxds v2, vs0 5585; P9BE-NEXT: blr 5586; 5587; P9LE-LABEL: fromRegsConvftoull: 5588; P9LE: # %bb.0: # %entry 5589; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5590; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5591; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5592; P9LE-NEXT: xvcvdpuxds v2, vs0 5593; P9LE-NEXT: blr 5594; 5595; P8BE-LABEL: fromRegsConvftoull: 5596; P8BE: # %bb.0: # %entry 5597; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5598; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5599; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5600; P8BE-NEXT: xvcvdpuxds v2, vs0 5601; P8BE-NEXT: blr 5602; 5603; P8LE-LABEL: fromRegsConvftoull: 5604; P8LE: # %bb.0: # %entry 5605; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5606; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5607; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5608; P8LE-NEXT: xvcvdpuxds v2, vs0 5609; P8LE-NEXT: blr 5610entry: 5611 %conv = fptoui float %a to i64 5612 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5613 %conv1 = fptoui float %b to i64 5614 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5615 ret <2 x i64> %vecinit2 5616} 5617 5618; Function Attrs: norecurse nounwind readnone 5619define <2 x i64> @fromDiffConstsConvftoull() { 5620; P9BE-LABEL: fromDiffConstsConvftoull: 5621; P9BE: # %bb.0: # %entry 5622; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5623; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5624; P9BE-NEXT: lxvx v2, 0, r3 5625; P9BE-NEXT: blr 5626; 5627; P9LE-LABEL: fromDiffConstsConvftoull: 5628; P9LE: # %bb.0: # %entry 5629; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5630; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5631; P9LE-NEXT: lxvx v2, 0, r3 5632; P9LE-NEXT: blr 5633; 5634; P8BE-LABEL: fromDiffConstsConvftoull: 5635; P8BE: # %bb.0: # %entry 5636; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5637; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5638; P8BE-NEXT: lxvd2x v2, 0, r3 5639; P8BE-NEXT: blr 5640; 5641; P8LE-LABEL: fromDiffConstsConvftoull: 5642; P8LE: # %bb.0: # %entry 5643; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5644; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5645; P8LE-NEXT: lxvd2x vs0, 0, r3 5646; P8LE-NEXT: xxswapd v2, vs0 5647; P8LE-NEXT: blr 5648entry: 5649 ret <2 x i64> <i64 24, i64 234> 5650} 5651 5652; Function Attrs: norecurse nounwind readonly 5653define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5654; P9BE-LABEL: fromDiffMemConsAConvftoull: 5655; P9BE: # %bb.0: # %entry 5656; P9BE-NEXT: lfs f0, 0(r3) 5657; P9BE-NEXT: lfs f1, 4(r3) 5658; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5659; P9BE-NEXT: xvcvdpuxds v2, vs0 5660; P9BE-NEXT: blr 5661; 5662; P9LE-LABEL: fromDiffMemConsAConvftoull: 5663; P9LE: # %bb.0: # %entry 5664; P9LE-NEXT: lfs f0, 0(r3) 5665; P9LE-NEXT: lfs f1, 4(r3) 5666; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5667; P9LE-NEXT: xvcvdpuxds v2, vs0 5668; P9LE-NEXT: blr 5669; 5670; P8BE-LABEL: fromDiffMemConsAConvftoull: 5671; P8BE: # %bb.0: # %entry 5672; P8BE-NEXT: lfsx f0, 0, r3 5673; P8BE-NEXT: lfs f1, 4(r3) 5674; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5675; P8BE-NEXT: xvcvdpuxds v2, vs0 5676; P8BE-NEXT: blr 5677; 5678; P8LE-LABEL: fromDiffMemConsAConvftoull: 5679; P8LE: # %bb.0: # %entry 5680; P8LE-NEXT: lfsx f0, 0, r3 5681; P8LE-NEXT: lfs f1, 4(r3) 5682; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5683; P8LE-NEXT: xvcvdpuxds v2, vs0 5684; P8LE-NEXT: blr 5685entry: 5686 %0 = load float, float* %ptr, align 4 5687 %conv = fptoui float %0 to i64 5688 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5689 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5690 %1 = load float, float* %arrayidx1, align 4 5691 %conv2 = fptoui float %1 to i64 5692 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5693 ret <2 x i64> %vecinit3 5694} 5695 5696; Function Attrs: norecurse nounwind readonly 5697define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5698; P9BE-LABEL: fromDiffMemConsDConvftoull: 5699; P9BE: # %bb.0: # %entry 5700; P9BE-NEXT: lfs f0, 12(r3) 5701; P9BE-NEXT: lfs f1, 8(r3) 5702; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5703; P9BE-NEXT: xvcvdpuxds v2, vs0 5704; P9BE-NEXT: blr 5705; 5706; P9LE-LABEL: fromDiffMemConsDConvftoull: 5707; P9LE: # %bb.0: # %entry 5708; P9LE-NEXT: lfs f0, 12(r3) 5709; P9LE-NEXT: lfs f1, 8(r3) 5710; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5711; P9LE-NEXT: xvcvdpuxds v2, vs0 5712; P9LE-NEXT: blr 5713; 5714; P8BE-LABEL: fromDiffMemConsDConvftoull: 5715; P8BE: # %bb.0: # %entry 5716; P8BE-NEXT: lfs f0, 12(r3) 5717; P8BE-NEXT: lfs f1, 8(r3) 5718; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5719; P8BE-NEXT: xvcvdpuxds v2, vs0 5720; P8BE-NEXT: blr 5721; 5722; P8LE-LABEL: fromDiffMemConsDConvftoull: 5723; P8LE: # %bb.0: # %entry 5724; P8LE-NEXT: lfs f0, 12(r3) 5725; P8LE-NEXT: lfs f1, 8(r3) 5726; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5727; P8LE-NEXT: xvcvdpuxds v2, vs0 5728; P8LE-NEXT: blr 5729entry: 5730 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5731 %0 = load float, float* %arrayidx, align 4 5732 %conv = fptoui float %0 to i64 5733 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5734 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5735 %1 = load float, float* %arrayidx1, align 4 5736 %conv2 = fptoui float %1 to i64 5737 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5738 ret <2 x i64> %vecinit3 5739} 5740 5741; Function Attrs: norecurse nounwind readonly 5742define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5743; P9BE-LABEL: fromDiffMemVarAConvftoull: 5744; P9BE: # %bb.0: # %entry 5745; P9BE-NEXT: sldi r4, r4, 2 5746; P9BE-NEXT: lfsux f0, r3, r4 5747; P9BE-NEXT: lfs f1, 4(r3) 5748; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5749; P9BE-NEXT: xvcvdpuxds v2, vs0 5750; P9BE-NEXT: blr 5751; 5752; P9LE-LABEL: fromDiffMemVarAConvftoull: 5753; P9LE: # %bb.0: # %entry 5754; P9LE-NEXT: sldi r4, r4, 2 5755; P9LE-NEXT: lfsux f0, r3, r4 5756; P9LE-NEXT: lfs f1, 4(r3) 5757; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5758; P9LE-NEXT: xvcvdpuxds v2, vs0 5759; P9LE-NEXT: blr 5760; 5761; P8BE-LABEL: fromDiffMemVarAConvftoull: 5762; P8BE: # %bb.0: # %entry 5763; P8BE-NEXT: sldi r4, r4, 2 5764; P8BE-NEXT: lfsux f0, r3, r4 5765; P8BE-NEXT: lfs f1, 4(r3) 5766; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5767; P8BE-NEXT: xvcvdpuxds v2, vs0 5768; P8BE-NEXT: blr 5769; 5770; P8LE-LABEL: fromDiffMemVarAConvftoull: 5771; P8LE: # %bb.0: # %entry 5772; P8LE-NEXT: sldi r4, r4, 2 5773; P8LE-NEXT: lfsux f0, r3, r4 5774; P8LE-NEXT: lfs f1, 4(r3) 5775; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5776; P8LE-NEXT: xvcvdpuxds v2, vs0 5777; P8LE-NEXT: blr 5778entry: 5779 %idxprom = sext i32 %elem to i64 5780 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5781 %0 = load float, float* %arrayidx, align 4 5782 %conv = fptoui float %0 to i64 5783 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5784 %add = add nsw i32 %elem, 1 5785 %idxprom1 = sext i32 %add to i64 5786 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5787 %1 = load float, float* %arrayidx2, align 4 5788 %conv3 = fptoui float %1 to i64 5789 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5790 ret <2 x i64> %vecinit4 5791} 5792 5793; Function Attrs: norecurse nounwind readonly 5794define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5795; P9BE-LABEL: fromDiffMemVarDConvftoull: 5796; P9BE: # %bb.0: # %entry 5797; P9BE-NEXT: sldi r4, r4, 2 5798; P9BE-NEXT: lfsux f0, r3, r4 5799; P9BE-NEXT: lfs f1, -4(r3) 5800; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5801; P9BE-NEXT: xvcvdpuxds v2, vs0 5802; P9BE-NEXT: blr 5803; 5804; P9LE-LABEL: fromDiffMemVarDConvftoull: 5805; P9LE: # %bb.0: # %entry 5806; P9LE-NEXT: sldi r4, r4, 2 5807; P9LE-NEXT: lfsux f0, r3, r4 5808; P9LE-NEXT: lfs f1, -4(r3) 5809; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5810; P9LE-NEXT: xvcvdpuxds v2, vs0 5811; P9LE-NEXT: blr 5812; 5813; P8BE-LABEL: fromDiffMemVarDConvftoull: 5814; P8BE: # %bb.0: # %entry 5815; P8BE-NEXT: sldi r4, r4, 2 5816; P8BE-NEXT: lfsux f0, r3, r4 5817; P8BE-NEXT: lfs f1, -4(r3) 5818; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5819; P8BE-NEXT: xvcvdpuxds v2, vs0 5820; P8BE-NEXT: blr 5821; 5822; P8LE-LABEL: fromDiffMemVarDConvftoull: 5823; P8LE: # %bb.0: # %entry 5824; P8LE-NEXT: sldi r4, r4, 2 5825; P8LE-NEXT: lfsux f0, r3, r4 5826; P8LE-NEXT: lfs f1, -4(r3) 5827; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5828; P8LE-NEXT: xvcvdpuxds v2, vs0 5829; P8LE-NEXT: blr 5830entry: 5831 %idxprom = sext i32 %elem to i64 5832 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5833 %0 = load float, float* %arrayidx, align 4 5834 %conv = fptoui float %0 to i64 5835 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5836 %sub = add nsw i32 %elem, -1 5837 %idxprom1 = sext i32 %sub to i64 5838 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5839 %1 = load float, float* %arrayidx2, align 4 5840 %conv3 = fptoui float %1 to i64 5841 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5842 ret <2 x i64> %vecinit4 5843} 5844 5845; Function Attrs: norecurse nounwind readnone 5846define <2 x i64> @spltRegValConvftoull(float %val) { 5847; P9BE-LABEL: spltRegValConvftoull: 5848; P9BE: # %bb.0: # %entry 5849; P9BE-NEXT: xscvdpuxds f0, f1 5850; P9BE-NEXT: xxspltd v2, f0, 0 5851; P9BE-NEXT: blr 5852; 5853; P9LE-LABEL: spltRegValConvftoull: 5854; P9LE: # %bb.0: # %entry 5855; P9LE-NEXT: xscvdpuxds f0, f1 5856; P9LE-NEXT: xxspltd v2, f0, 0 5857; P9LE-NEXT: blr 5858; 5859; P8BE-LABEL: spltRegValConvftoull: 5860; P8BE: # %bb.0: # %entry 5861; P8BE-NEXT: xscvdpuxds f0, f1 5862; P8BE-NEXT: xxspltd v2, f0, 0 5863; P8BE-NEXT: blr 5864; 5865; P8LE-LABEL: spltRegValConvftoull: 5866; P8LE: # %bb.0: # %entry 5867; P8LE-NEXT: xscvdpuxds f0, f1 5868; P8LE-NEXT: xxspltd v2, f0, 0 5869; P8LE-NEXT: blr 5870entry: 5871 %conv = fptoui float %val to i64 5872 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5873 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5874 ret <2 x i64> %splat.splat 5875} 5876 5877; Function Attrs: norecurse nounwind readonly 5878define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5879; P9BE-LABEL: spltMemValConvftoull: 5880; P9BE: # %bb.0: # %entry 5881; P9BE-NEXT: lfs f0, 0(r3) 5882; P9BE-NEXT: xscvdpuxds f0, f0 5883; P9BE-NEXT: xxspltd v2, f0, 0 5884; P9BE-NEXT: blr 5885; 5886; P9LE-LABEL: spltMemValConvftoull: 5887; P9LE: # %bb.0: # %entry 5888; P9LE-NEXT: lfs f0, 0(r3) 5889; P9LE-NEXT: xscvdpuxds f0, f0 5890; P9LE-NEXT: xxspltd v2, f0, 0 5891; P9LE-NEXT: blr 5892; 5893; P8BE-LABEL: spltMemValConvftoull: 5894; P8BE: # %bb.0: # %entry 5895; P8BE-NEXT: lfsx f0, 0, r3 5896; P8BE-NEXT: xscvdpuxds f0, f0 5897; P8BE-NEXT: xxspltd v2, f0, 0 5898; P8BE-NEXT: blr 5899; 5900; P8LE-LABEL: spltMemValConvftoull: 5901; P8LE: # %bb.0: # %entry 5902; P8LE-NEXT: lfsx f0, 0, r3 5903; P8LE-NEXT: xscvdpuxds f0, f0 5904; P8LE-NEXT: xxspltd v2, f0, 0 5905; P8LE-NEXT: blr 5906entry: 5907 %0 = load float, float* %ptr, align 4 5908 %conv = fptoui float %0 to i64 5909 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5910 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5911 ret <2 x i64> %splat.splat 5912} 5913 5914; Function Attrs: norecurse nounwind readnone 5915define <2 x i64> @spltCnstConvdtoull() { 5916; P9BE-LABEL: spltCnstConvdtoull: 5917; P9BE: # %bb.0: # %entry 5918; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5919; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5920; P9BE-NEXT: lxvx v2, 0, r3 5921; P9BE-NEXT: blr 5922; 5923; P9LE-LABEL: spltCnstConvdtoull: 5924; P9LE: # %bb.0: # %entry 5925; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5926; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5927; P9LE-NEXT: lxvx v2, 0, r3 5928; P9LE-NEXT: blr 5929; 5930; P8BE-LABEL: spltCnstConvdtoull: 5931; P8BE: # %bb.0: # %entry 5932; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5933; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5934; P8BE-NEXT: lxvd2x v2, 0, r3 5935; P8BE-NEXT: blr 5936; 5937; P8LE-LABEL: spltCnstConvdtoull: 5938; P8LE: # %bb.0: # %entry 5939; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5940; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5941; P8LE-NEXT: lxvd2x vs0, 0, r3 5942; P8LE-NEXT: xxswapd v2, vs0 5943; P8LE-NEXT: blr 5944entry: 5945 ret <2 x i64> <i64 4, i64 4> 5946} 5947 5948; Function Attrs: norecurse nounwind readnone 5949define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5950; P9BE-LABEL: fromRegsConvdtoull: 5951; P9BE: # %bb.0: # %entry 5952; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5953; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5954; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5955; P9BE-NEXT: xvcvdpuxds v2, vs0 5956; P9BE-NEXT: blr 5957; 5958; P9LE-LABEL: fromRegsConvdtoull: 5959; P9LE: # %bb.0: # %entry 5960; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5961; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5962; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5963; P9LE-NEXT: xvcvdpuxds v2, vs0 5964; P9LE-NEXT: blr 5965; 5966; P8BE-LABEL: fromRegsConvdtoull: 5967; P8BE: # %bb.0: # %entry 5968; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5969; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5970; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5971; P8BE-NEXT: xvcvdpuxds v2, vs0 5972; P8BE-NEXT: blr 5973; 5974; P8LE-LABEL: fromRegsConvdtoull: 5975; P8LE: # %bb.0: # %entry 5976; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5977; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5978; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5979; P8LE-NEXT: xvcvdpuxds v2, vs0 5980; P8LE-NEXT: blr 5981entry: 5982 %conv = fptoui double %a to i64 5983 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5984 %conv1 = fptoui double %b to i64 5985 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5986 ret <2 x i64> %vecinit2 5987} 5988 5989; Function Attrs: norecurse nounwind readnone 5990define <2 x i64> @fromDiffConstsConvdtoull() { 5991; P9BE-LABEL: fromDiffConstsConvdtoull: 5992; P9BE: # %bb.0: # %entry 5993; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5994; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5995; P9BE-NEXT: lxvx v2, 0, r3 5996; P9BE-NEXT: blr 5997; 5998; P9LE-LABEL: fromDiffConstsConvdtoull: 5999; P9LE: # %bb.0: # %entry 6000; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 6001; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 6002; P9LE-NEXT: lxvx v2, 0, r3 6003; P9LE-NEXT: blr 6004; 6005; P8BE-LABEL: fromDiffConstsConvdtoull: 6006; P8BE: # %bb.0: # %entry 6007; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 6008; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 6009; P8BE-NEXT: lxvd2x v2, 0, r3 6010; P8BE-NEXT: blr 6011; 6012; P8LE-LABEL: fromDiffConstsConvdtoull: 6013; P8LE: # %bb.0: # %entry 6014; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 6015; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 6016; P8LE-NEXT: lxvd2x vs0, 0, r3 6017; P8LE-NEXT: xxswapd v2, vs0 6018; P8LE-NEXT: blr 6019entry: 6020 ret <2 x i64> <i64 24, i64 234> 6021} 6022 6023; Function Attrs: norecurse nounwind readonly 6024define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 6025; P9BE-LABEL: fromDiffMemConsAConvdtoull: 6026; P9BE: # %bb.0: # %entry 6027; P9BE-NEXT: lxv vs0, 0(r3) 6028; P9BE-NEXT: xvcvdpuxds v2, vs0 6029; P9BE-NEXT: blr 6030; 6031; P9LE-LABEL: fromDiffMemConsAConvdtoull: 6032; P9LE: # %bb.0: # %entry 6033; P9LE-NEXT: lxv vs0, 0(r3) 6034; P9LE-NEXT: xvcvdpuxds v2, vs0 6035; P9LE-NEXT: blr 6036; 6037; P8BE-LABEL: fromDiffMemConsAConvdtoull: 6038; P8BE: # %bb.0: # %entry 6039; P8BE-NEXT: lxvd2x vs0, 0, r3 6040; P8BE-NEXT: xvcvdpuxds v2, vs0 6041; P8BE-NEXT: blr 6042; 6043; P8LE-LABEL: fromDiffMemConsAConvdtoull: 6044; P8LE: # %bb.0: # %entry 6045; P8LE-NEXT: lxvd2x vs0, 0, r3 6046; P8LE-NEXT: xxswapd vs0, vs0 6047; P8LE-NEXT: xvcvdpuxds v2, vs0 6048; P8LE-NEXT: blr 6049entry: 6050 %0 = bitcast double* %ptr to <2 x double>* 6051 %1 = load <2 x double>, <2 x double>* %0, align 8 6052 %2 = fptoui <2 x double> %1 to <2 x i64> 6053 ret <2 x i64> %2 6054} 6055 6056; Function Attrs: norecurse nounwind readonly 6057define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 6058; P9BE-LABEL: fromDiffMemConsDConvdtoull: 6059; P9BE: # %bb.0: # %entry 6060; P9BE-NEXT: lxv vs0, 16(r3) 6061; P9BE-NEXT: xxswapd vs0, vs0 6062; P9BE-NEXT: xvcvdpuxds v2, vs0 6063; P9BE-NEXT: blr 6064; 6065; P9LE-LABEL: fromDiffMemConsDConvdtoull: 6066; P9LE: # %bb.0: # %entry 6067; P9LE-NEXT: addi r3, r3, 16 6068; P9LE-NEXT: lxvd2x vs0, 0, r3 6069; P9LE-NEXT: xvcvdpuxds v2, vs0 6070; P9LE-NEXT: blr 6071; 6072; P8BE-LABEL: fromDiffMemConsDConvdtoull: 6073; P8BE: # %bb.0: # %entry 6074; P8BE-NEXT: addi r3, r3, 16 6075; P8BE-NEXT: lxvd2x vs0, 0, r3 6076; P8BE-NEXT: xxswapd vs0, vs0 6077; P8BE-NEXT: xvcvdpuxds v2, vs0 6078; P8BE-NEXT: blr 6079; 6080; P8LE-LABEL: fromDiffMemConsDConvdtoull: 6081; P8LE: # %bb.0: # %entry 6082; P8LE-NEXT: addi r3, r3, 16 6083; P8LE-NEXT: lxvd2x vs0, 0, r3 6084; P8LE-NEXT: xvcvdpuxds v2, vs0 6085; P8LE-NEXT: blr 6086entry: 6087 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 6088 %0 = load double, double* %arrayidx, align 8 6089 %conv = fptoui double %0 to i64 6090 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6091 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 6092 %1 = load double, double* %arrayidx1, align 8 6093 %conv2 = fptoui double %1 to i64 6094 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6095 ret <2 x i64> %vecinit3 6096} 6097 6098; Function Attrs: norecurse nounwind readonly 6099define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6100; P9BE-LABEL: fromDiffMemVarAConvdtoull: 6101; P9BE: # %bb.0: # %entry 6102; P9BE-NEXT: sldi r4, r4, 3 6103; P9BE-NEXT: lxvx vs0, r3, r4 6104; P9BE-NEXT: xvcvdpuxds v2, vs0 6105; P9BE-NEXT: blr 6106; 6107; P9LE-LABEL: fromDiffMemVarAConvdtoull: 6108; P9LE: # %bb.0: # %entry 6109; P9LE-NEXT: sldi r4, r4, 3 6110; P9LE-NEXT: lxvx vs0, r3, r4 6111; P9LE-NEXT: xvcvdpuxds v2, vs0 6112; P9LE-NEXT: blr 6113; 6114; P8BE-LABEL: fromDiffMemVarAConvdtoull: 6115; P8BE: # %bb.0: # %entry 6116; P8BE-NEXT: sldi r4, r4, 3 6117; P8BE-NEXT: lxvd2x vs0, r3, r4 6118; P8BE-NEXT: xvcvdpuxds v2, vs0 6119; P8BE-NEXT: blr 6120; 6121; P8LE-LABEL: fromDiffMemVarAConvdtoull: 6122; P8LE: # %bb.0: # %entry 6123; P8LE-NEXT: sldi r4, r4, 3 6124; P8LE-NEXT: lxvd2x vs0, r3, r4 6125; P8LE-NEXT: xxswapd vs0, vs0 6126; P8LE-NEXT: xvcvdpuxds v2, vs0 6127; P8LE-NEXT: blr 6128entry: 6129 %idxprom = sext i32 %elem to i64 6130 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6131 %0 = load double, double* %arrayidx, align 8 6132 %conv = fptoui double %0 to i64 6133 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6134 %add = add nsw i32 %elem, 1 6135 %idxprom1 = sext i32 %add to i64 6136 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6137 %1 = load double, double* %arrayidx2, align 8 6138 %conv3 = fptoui double %1 to i64 6139 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6140 ret <2 x i64> %vecinit4 6141} 6142 6143; Function Attrs: norecurse nounwind readonly 6144define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6145; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6146; P9BE: # %bb.0: # %entry 6147; P9BE-NEXT: sldi r4, r4, 3 6148; P9BE-NEXT: add r3, r3, r4 6149; P9BE-NEXT: li r4, -8 6150; P9BE-NEXT: lxvx vs0, r3, r4 6151; P9BE-NEXT: xxswapd vs0, vs0 6152; P9BE-NEXT: xvcvdpuxds v2, vs0 6153; P9BE-NEXT: blr 6154; 6155; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6156; P9LE: # %bb.0: # %entry 6157; P9LE-NEXT: sldi r4, r4, 3 6158; P9LE-NEXT: add r3, r3, r4 6159; P9LE-NEXT: addi r3, r3, -8 6160; P9LE-NEXT: lxvd2x vs0, 0, r3 6161; P9LE-NEXT: xvcvdpuxds v2, vs0 6162; P9LE-NEXT: blr 6163; 6164; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6165; P8BE: # %bb.0: # %entry 6166; P8BE-NEXT: sldi r4, r4, 3 6167; P8BE-NEXT: add r3, r3, r4 6168; P8BE-NEXT: addi r3, r3, -8 6169; P8BE-NEXT: lxvd2x vs0, 0, r3 6170; P8BE-NEXT: xxswapd vs0, vs0 6171; P8BE-NEXT: xvcvdpuxds v2, vs0 6172; P8BE-NEXT: blr 6173; 6174; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6175; P8LE: # %bb.0: # %entry 6176; P8LE-NEXT: sldi r4, r4, 3 6177; P8LE-NEXT: add r3, r3, r4 6178; P8LE-NEXT: addi r3, r3, -8 6179; P8LE-NEXT: lxvd2x vs0, 0, r3 6180; P8LE-NEXT: xvcvdpuxds v2, vs0 6181; P8LE-NEXT: blr 6182entry: 6183 %idxprom = sext i32 %elem to i64 6184 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6185 %0 = load double, double* %arrayidx, align 8 6186 %conv = fptoui double %0 to i64 6187 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6188 %sub = add nsw i32 %elem, -1 6189 %idxprom1 = sext i32 %sub to i64 6190 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6191 %1 = load double, double* %arrayidx2, align 8 6192 %conv3 = fptoui double %1 to i64 6193 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6194 ret <2 x i64> %vecinit4 6195} 6196 6197; Function Attrs: norecurse nounwind readnone 6198define <2 x i64> @spltRegValConvdtoull(double %val) { 6199; P9BE-LABEL: spltRegValConvdtoull: 6200; P9BE: # %bb.0: # %entry 6201; P9BE-NEXT: xscvdpuxds f0, f1 6202; P9BE-NEXT: xxspltd v2, vs0, 0 6203; P9BE-NEXT: blr 6204; 6205; P9LE-LABEL: spltRegValConvdtoull: 6206; P9LE: # %bb.0: # %entry 6207; P9LE-NEXT: xscvdpuxds f0, f1 6208; P9LE-NEXT: xxspltd v2, vs0, 0 6209; P9LE-NEXT: blr 6210; 6211; P8BE-LABEL: spltRegValConvdtoull: 6212; P8BE: # %bb.0: # %entry 6213; P8BE-NEXT: xscvdpuxds f0, f1 6214; P8BE-NEXT: xxspltd v2, vs0, 0 6215; P8BE-NEXT: blr 6216; 6217; P8LE-LABEL: spltRegValConvdtoull: 6218; P8LE: # %bb.0: # %entry 6219; P8LE-NEXT: xscvdpuxds f0, f1 6220; P8LE-NEXT: xxspltd v2, vs0, 0 6221; P8LE-NEXT: blr 6222entry: 6223 %conv = fptoui double %val to i64 6224 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6225 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6226 ret <2 x i64> %splat.splat 6227} 6228 6229; Function Attrs: norecurse nounwind readonly 6230define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6231; P9BE-LABEL: spltMemValConvdtoull: 6232; P9BE: # %bb.0: # %entry 6233; P9BE-NEXT: lxvdsx vs0, 0, r3 6234; P9BE-NEXT: xvcvdpuxds v2, vs0 6235; P9BE-NEXT: blr 6236; 6237; P9LE-LABEL: spltMemValConvdtoull: 6238; P9LE: # %bb.0: # %entry 6239; P9LE-NEXT: lxvdsx vs0, 0, r3 6240; P9LE-NEXT: xvcvdpuxds v2, vs0 6241; P9LE-NEXT: blr 6242; 6243; P8BE-LABEL: spltMemValConvdtoull: 6244; P8BE: # %bb.0: # %entry 6245; P8BE-NEXT: lxvdsx vs0, 0, r3 6246; P8BE-NEXT: xvcvdpuxds v2, vs0 6247; P8BE-NEXT: blr 6248; 6249; P8LE-LABEL: spltMemValConvdtoull: 6250; P8LE: # %bb.0: # %entry 6251; P8LE-NEXT: lxvdsx vs0, 0, r3 6252; P8LE-NEXT: xvcvdpuxds v2, vs0 6253; P8LE-NEXT: blr 6254entry: 6255 %0 = load double, double* %ptr, align 8 6256 %conv = fptoui double %0 to i64 6257 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6258 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6259 ret <2 x i64> %splat.splat 6260} 6261