1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(double *ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(float *ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(double *ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(float *ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(double *ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(float *ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712define <4 x i32> @allZeroi() { 713; P9BE-LABEL: allZeroi: 714; P9BE: # %bb.0: # %entry 715; P9BE-NEXT: xxlxor v2, v2, v2 716; P9BE-NEXT: blr 717; 718; P9LE-LABEL: allZeroi: 719; P9LE: # %bb.0: # %entry 720; P9LE-NEXT: xxlxor v2, v2, v2 721; P9LE-NEXT: blr 722; 723; P8BE-LABEL: allZeroi: 724; P8BE: # %bb.0: # %entry 725; P8BE-NEXT: xxlxor v2, v2, v2 726; P8BE-NEXT: blr 727; 728; P8LE-LABEL: allZeroi: 729; P8LE: # %bb.0: # %entry 730; P8LE-NEXT: xxlxor v2, v2, v2 731; P8LE-NEXT: blr 732entry: 733 ret <4 x i32> zeroinitializer 734} 735 736define <4 x i32> @spltConst1i() { 737; P9BE-LABEL: spltConst1i: 738; P9BE: # %bb.0: # %entry 739; P9BE-NEXT: vspltisw v2, 1 740; P9BE-NEXT: blr 741; 742; P9LE-LABEL: spltConst1i: 743; P9LE: # %bb.0: # %entry 744; P9LE-NEXT: vspltisw v2, 1 745; P9LE-NEXT: blr 746; 747; P8BE-LABEL: spltConst1i: 748; P8BE: # %bb.0: # %entry 749; P8BE-NEXT: vspltisw v2, 1 750; P8BE-NEXT: blr 751; 752; P8LE-LABEL: spltConst1i: 753; P8LE: # %bb.0: # %entry 754; P8LE-NEXT: vspltisw v2, 1 755; P8LE-NEXT: blr 756entry: 757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 758} 759 760define <4 x i32> @spltConst16ki() { 761; P9BE-LABEL: spltConst16ki: 762; P9BE: # %bb.0: # %entry 763; P9BE-NEXT: vspltisw v2, -15 764; P9BE-NEXT: vsrw v2, v2, v2 765; P9BE-NEXT: blr 766; 767; P9LE-LABEL: spltConst16ki: 768; P9LE: # %bb.0: # %entry 769; P9LE-NEXT: vspltisw v2, -15 770; P9LE-NEXT: vsrw v2, v2, v2 771; P9LE-NEXT: blr 772; 773; P8BE-LABEL: spltConst16ki: 774; P8BE: # %bb.0: # %entry 775; P8BE-NEXT: vspltisw v2, -15 776; P8BE-NEXT: vsrw v2, v2, v2 777; P8BE-NEXT: blr 778; 779; P8LE-LABEL: spltConst16ki: 780; P8LE: # %bb.0: # %entry 781; P8LE-NEXT: vspltisw v2, -15 782; P8LE-NEXT: vsrw v2, v2, v2 783; P8LE-NEXT: blr 784entry: 785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 786} 787 788define <4 x i32> @spltConst32ki() { 789; P9BE-LABEL: spltConst32ki: 790; P9BE: # %bb.0: # %entry 791; P9BE-NEXT: vspltisw v2, -16 792; P9BE-NEXT: vsrw v2, v2, v2 793; P9BE-NEXT: blr 794; 795; P9LE-LABEL: spltConst32ki: 796; P9LE: # %bb.0: # %entry 797; P9LE-NEXT: vspltisw v2, -16 798; P9LE-NEXT: vsrw v2, v2, v2 799; P9LE-NEXT: blr 800; 801; P8BE-LABEL: spltConst32ki: 802; P8BE: # %bb.0: # %entry 803; P8BE-NEXT: vspltisw v2, -16 804; P8BE-NEXT: vsrw v2, v2, v2 805; P8BE-NEXT: blr 806; 807; P8LE-LABEL: spltConst32ki: 808; P8LE: # %bb.0: # %entry 809; P8LE-NEXT: vspltisw v2, -16 810; P8LE-NEXT: vsrw v2, v2, v2 811; P8LE-NEXT: blr 812entry: 813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 814} 815 816define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 817; P9BE-LABEL: fromRegsi: 818; P9BE: # %bb.0: # %entry 819; P9BE-NEXT: rldimi r6, r5, 32, 0 820; P9BE-NEXT: rldimi r4, r3, 32, 0 821; P9BE-NEXT: mtvsrdd v2, r4, r6 822; P9BE-NEXT: blr 823; 824; P9LE-LABEL: fromRegsi: 825; P9LE: # %bb.0: # %entry 826; P9LE-NEXT: rldimi r3, r4, 32, 0 827; P9LE-NEXT: rldimi r5, r6, 32, 0 828; P9LE-NEXT: mtvsrdd v2, r5, r3 829; P9LE-NEXT: blr 830; 831; P8BE-LABEL: fromRegsi: 832; P8BE: # %bb.0: # %entry 833; P8BE-NEXT: rldimi r6, r5, 32, 0 834; P8BE-NEXT: rldimi r4, r3, 32, 0 835; P8BE-NEXT: mtfprd f0, r6 836; P8BE-NEXT: mtfprd f1, r4 837; P8BE-NEXT: xxmrghd v2, vs1, vs0 838; P8BE-NEXT: blr 839; 840; P8LE-LABEL: fromRegsi: 841; P8LE: # %bb.0: # %entry 842; P8LE-NEXT: rldimi r3, r4, 32, 0 843; P8LE-NEXT: rldimi r5, r6, 32, 0 844; P8LE-NEXT: mtfprd f0, r3 845; P8LE-NEXT: mtfprd f1, r5 846; P8LE-NEXT: xxmrghd v2, vs1, vs0 847; P8LE-NEXT: blr 848entry: 849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 853 ret <4 x i32> %vecinit3 854} 855 856define <4 x i32> @fromDiffConstsi() { 857; P9BE-LABEL: fromDiffConstsi: 858; P9BE: # %bb.0: # %entry 859; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 860; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 861; P9BE-NEXT: lxv v2, 0(r3) 862; P9BE-NEXT: blr 863; 864; P9LE-LABEL: fromDiffConstsi: 865; P9LE: # %bb.0: # %entry 866; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 867; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 868; P9LE-NEXT: lxv v2, 0(r3) 869; P9LE-NEXT: blr 870; 871; P8BE-LABEL: fromDiffConstsi: 872; P8BE: # %bb.0: # %entry 873; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 874; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 875; P8BE-NEXT: lxvw4x v2, 0, r3 876; P8BE-NEXT: blr 877; 878; P8LE-LABEL: fromDiffConstsi: 879; P8LE: # %bb.0: # %entry 880; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 881; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 882; P8LE-NEXT: lxvd2x vs0, 0, r3 883; P8LE-NEXT: xxswapd v2, vs0 884; P8LE-NEXT: blr 885entry: 886 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 887} 888 889define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 890; P9BE-LABEL: fromDiffMemConsAi: 891; P9BE: # %bb.0: # %entry 892; P9BE-NEXT: lxv v2, 0(r3) 893; P9BE-NEXT: blr 894; 895; P9LE-LABEL: fromDiffMemConsAi: 896; P9LE: # %bb.0: # %entry 897; P9LE-NEXT: lxv v2, 0(r3) 898; P9LE-NEXT: blr 899; 900; P8BE-LABEL: fromDiffMemConsAi: 901; P8BE: # %bb.0: # %entry 902; P8BE-NEXT: lxvw4x v2, 0, r3 903; P8BE-NEXT: blr 904; 905; P8LE-LABEL: fromDiffMemConsAi: 906; P8LE: # %bb.0: # %entry 907; P8LE-NEXT: lxvd2x vs0, 0, r3 908; P8LE-NEXT: xxswapd v2, vs0 909; P8LE-NEXT: blr 910entry: 911 %0 = load i32, i32* %arr, align 4 912 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 913 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 914 %1 = load i32, i32* %arrayidx1, align 4 915 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 916 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 917 %2 = load i32, i32* %arrayidx3, align 4 918 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 919 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 920 %3 = load i32, i32* %arrayidx5, align 4 921 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 922 ret <4 x i32> %vecinit6 923} 924 925define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 926; P9BE-LABEL: fromDiffMemConsDi: 927; P9BE: # %bb.0: # %entry 928; P9BE-NEXT: lxv v2, 0(r3) 929; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 930; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 931; P9BE-NEXT: lxv v3, 0(r3) 932; P9BE-NEXT: vperm v2, v2, v2, v3 933; P9BE-NEXT: blr 934; 935; P9LE-LABEL: fromDiffMemConsDi: 936; P9LE: # %bb.0: # %entry 937; P9LE-NEXT: lxvw4x v2, 0, r3 938; P9LE-NEXT: blr 939; 940; P8BE-LABEL: fromDiffMemConsDi: 941; P8BE: # %bb.0: # %entry 942; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 943; P8BE-NEXT: lxvw4x v2, 0, r3 944; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l 945; P8BE-NEXT: lxvw4x v3, 0, r4 946; P8BE-NEXT: vperm v2, v2, v2, v3 947; P8BE-NEXT: blr 948; 949; P8LE-LABEL: fromDiffMemConsDi: 950; P8LE: # %bb.0: # %entry 951; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 952; P8LE-NEXT: lxvd2x vs0, 0, r3 953; P8LE-NEXT: addi r4, r4, .LCPI7_0@toc@l 954; P8LE-NEXT: lxvd2x vs1, 0, r4 955; P8LE-NEXT: xxswapd v2, vs0 956; P8LE-NEXT: xxswapd v3, vs1 957; P8LE-NEXT: vperm v2, v2, v2, v3 958; P8LE-NEXT: blr 959entry: 960 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 961 %0 = load i32, i32* %arrayidx, align 4 962 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 963 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 964 %1 = load i32, i32* %arrayidx1, align 4 965 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 966 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 967 %2 = load i32, i32* %arrayidx3, align 4 968 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 969 %3 = load i32, i32* %arr, align 4 970 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 971 ret <4 x i32> %vecinit6 972} 973 974define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 975; P9BE-LABEL: fromDiffMemVarAi: 976; P9BE: # %bb.0: # %entry 977; P9BE-NEXT: sldi r4, r4, 2 978; P9BE-NEXT: lxvx v2, r3, r4 979; P9BE-NEXT: blr 980; 981; P9LE-LABEL: fromDiffMemVarAi: 982; P9LE: # %bb.0: # %entry 983; P9LE-NEXT: sldi r4, r4, 2 984; P9LE-NEXT: lxvx v2, r3, r4 985; P9LE-NEXT: blr 986; 987; P8BE-LABEL: fromDiffMemVarAi: 988; P8BE: # %bb.0: # %entry 989; P8BE-NEXT: sldi r4, r4, 2 990; P8BE-NEXT: lxvw4x v2, r3, r4 991; P8BE-NEXT: blr 992; 993; P8LE-LABEL: fromDiffMemVarAi: 994; P8LE: # %bb.0: # %entry 995; P8LE-NEXT: sldi r4, r4, 2 996; P8LE-NEXT: lxvd2x vs0, r3, r4 997; P8LE-NEXT: xxswapd v2, vs0 998; P8LE-NEXT: blr 999entry: 1000 %idxprom = sext i32 %elem to i64 1001 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1002 %0 = load i32, i32* %arrayidx, align 4 1003 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1004 %add = add nsw i32 %elem, 1 1005 %idxprom1 = sext i32 %add to i64 1006 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1007 %1 = load i32, i32* %arrayidx2, align 4 1008 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1009 %add4 = add nsw i32 %elem, 2 1010 %idxprom5 = sext i32 %add4 to i64 1011 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1012 %2 = load i32, i32* %arrayidx6, align 4 1013 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1014 %add8 = add nsw i32 %elem, 3 1015 %idxprom9 = sext i32 %add8 to i64 1016 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1017 %3 = load i32, i32* %arrayidx10, align 4 1018 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1019 ret <4 x i32> %vecinit11 1020} 1021 1022define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1023; P9BE-LABEL: fromDiffMemVarDi: 1024; P9BE: # %bb.0: # %entry 1025; P9BE-NEXT: sldi r4, r4, 2 1026; P9BE-NEXT: add r3, r3, r4 1027; P9BE-NEXT: li r4, -12 1028; P9BE-NEXT: lxvx v2, r3, r4 1029; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1030; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1031; P9BE-NEXT: lxv v3, 0(r3) 1032; P9BE-NEXT: vperm v2, v2, v2, v3 1033; P9BE-NEXT: blr 1034; 1035; P9LE-LABEL: fromDiffMemVarDi: 1036; P9LE: # %bb.0: # %entry 1037; P9LE-NEXT: sldi r4, r4, 2 1038; P9LE-NEXT: add r3, r3, r4 1039; P9LE-NEXT: li r4, -12 1040; P9LE-NEXT: lxvx v2, r3, r4 1041; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1042; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1043; P9LE-NEXT: lxv v3, 0(r3) 1044; P9LE-NEXT: vperm v2, v2, v2, v3 1045; P9LE-NEXT: blr 1046; 1047; P8BE-LABEL: fromDiffMemVarDi: 1048; P8BE: # %bb.0: # %entry 1049; P8BE-NEXT: sldi r4, r4, 2 1050; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1051; P8BE-NEXT: add r3, r3, r4 1052; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1053; P8BE-NEXT: addi r3, r3, -12 1054; P8BE-NEXT: lxvw4x v3, 0, r4 1055; P8BE-NEXT: lxvw4x v2, 0, r3 1056; P8BE-NEXT: vperm v2, v2, v2, v3 1057; P8BE-NEXT: blr 1058; 1059; P8LE-LABEL: fromDiffMemVarDi: 1060; P8LE: # %bb.0: # %entry 1061; P8LE-NEXT: sldi r4, r4, 2 1062; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1063; P8LE-NEXT: add r3, r3, r4 1064; P8LE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1065; P8LE-NEXT: addi r3, r3, -12 1066; P8LE-NEXT: lxvd2x vs1, 0, r4 1067; P8LE-NEXT: lxvd2x vs0, 0, r3 1068; P8LE-NEXT: xxswapd v3, vs1 1069; P8LE-NEXT: xxswapd v2, vs0 1070; P8LE-NEXT: vperm v2, v2, v2, v3 1071; P8LE-NEXT: blr 1072entry: 1073 %idxprom = sext i32 %elem to i64 1074 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1075 %0 = load i32, i32* %arrayidx, align 4 1076 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1077 %sub = add nsw i32 %elem, -1 1078 %idxprom1 = sext i32 %sub to i64 1079 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1080 %1 = load i32, i32* %arrayidx2, align 4 1081 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1082 %sub4 = add nsw i32 %elem, -2 1083 %idxprom5 = sext i32 %sub4 to i64 1084 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1085 %2 = load i32, i32* %arrayidx6, align 4 1086 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1087 %sub8 = add nsw i32 %elem, -3 1088 %idxprom9 = sext i32 %sub8 to i64 1089 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1090 %3 = load i32, i32* %arrayidx10, align 4 1091 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1092 ret <4 x i32> %vecinit11 1093} 1094 1095define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1096; P9BE-LABEL: fromRandMemConsi: 1097; P9BE: # %bb.0: # %entry 1098; P9BE-NEXT: lwz r4, 16(r3) 1099; P9BE-NEXT: lwz r5, 72(r3) 1100; P9BE-NEXT: lwz r6, 8(r3) 1101; P9BE-NEXT: lwz r3, 352(r3) 1102; P9BE-NEXT: rldimi r3, r6, 32, 0 1103; P9BE-NEXT: rldimi r5, r4, 32, 0 1104; P9BE-NEXT: mtvsrdd v2, r5, r3 1105; P9BE-NEXT: blr 1106; 1107; P9LE-LABEL: fromRandMemConsi: 1108; P9LE: # %bb.0: # %entry 1109; P9LE-NEXT: lwz r4, 16(r3) 1110; P9LE-NEXT: lwz r5, 72(r3) 1111; P9LE-NEXT: lwz r6, 8(r3) 1112; P9LE-NEXT: lwz r3, 352(r3) 1113; P9LE-NEXT: rldimi r4, r5, 32, 0 1114; P9LE-NEXT: rldimi r6, r3, 32, 0 1115; P9LE-NEXT: mtvsrdd v2, r6, r4 1116; P9LE-NEXT: blr 1117; 1118; P8BE-LABEL: fromRandMemConsi: 1119; P8BE: # %bb.0: # %entry 1120; P8BE-NEXT: lwz r4, 8(r3) 1121; P8BE-NEXT: lwz r5, 352(r3) 1122; P8BE-NEXT: lwz r6, 16(r3) 1123; P8BE-NEXT: lwz r3, 72(r3) 1124; P8BE-NEXT: rldimi r5, r4, 32, 0 1125; P8BE-NEXT: rldimi r3, r6, 32, 0 1126; P8BE-NEXT: mtfprd f0, r5 1127; P8BE-NEXT: mtfprd f1, r3 1128; P8BE-NEXT: xxmrghd v2, vs1, vs0 1129; P8BE-NEXT: blr 1130; 1131; P8LE-LABEL: fromRandMemConsi: 1132; P8LE: # %bb.0: # %entry 1133; P8LE-NEXT: lwz r4, 16(r3) 1134; P8LE-NEXT: lwz r5, 72(r3) 1135; P8LE-NEXT: lwz r6, 8(r3) 1136; P8LE-NEXT: lwz r3, 352(r3) 1137; P8LE-NEXT: rldimi r4, r5, 32, 0 1138; P8LE-NEXT: rldimi r6, r3, 32, 0 1139; P8LE-NEXT: mtfprd f0, r4 1140; P8LE-NEXT: mtfprd f1, r6 1141; P8LE-NEXT: xxmrghd v2, vs1, vs0 1142; P8LE-NEXT: blr 1143entry: 1144 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1145 %0 = load i32, i32* %arrayidx, align 4 1146 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1147 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1148 %1 = load i32, i32* %arrayidx1, align 4 1149 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1150 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1151 %2 = load i32, i32* %arrayidx3, align 4 1152 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1153 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1154 %3 = load i32, i32* %arrayidx5, align 4 1155 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1156 ret <4 x i32> %vecinit6 1157} 1158 1159define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1160; P9BE-LABEL: fromRandMemVari: 1161; P9BE: # %bb.0: # %entry 1162; P9BE-NEXT: sldi r4, r4, 2 1163; P9BE-NEXT: add r3, r3, r4 1164; P9BE-NEXT: lwz r4, 16(r3) 1165; P9BE-NEXT: lwz r5, 4(r3) 1166; P9BE-NEXT: lwz r6, 8(r3) 1167; P9BE-NEXT: lwz r3, 32(r3) 1168; P9BE-NEXT: rldimi r3, r6, 32, 0 1169; P9BE-NEXT: rldimi r5, r4, 32, 0 1170; P9BE-NEXT: mtvsrdd v2, r5, r3 1171; P9BE-NEXT: blr 1172; 1173; P9LE-LABEL: fromRandMemVari: 1174; P9LE: # %bb.0: # %entry 1175; P9LE-NEXT: sldi r4, r4, 2 1176; P9LE-NEXT: add r3, r3, r4 1177; P9LE-NEXT: lwz r4, 16(r3) 1178; P9LE-NEXT: lwz r5, 4(r3) 1179; P9LE-NEXT: lwz r6, 8(r3) 1180; P9LE-NEXT: lwz r3, 32(r3) 1181; P9LE-NEXT: rldimi r4, r5, 32, 0 1182; P9LE-NEXT: rldimi r6, r3, 32, 0 1183; P9LE-NEXT: mtvsrdd v2, r6, r4 1184; P9LE-NEXT: blr 1185; 1186; P8BE-LABEL: fromRandMemVari: 1187; P8BE: # %bb.0: # %entry 1188; P8BE-NEXT: sldi r4, r4, 2 1189; P8BE-NEXT: add r3, r3, r4 1190; P8BE-NEXT: lwz r4, 8(r3) 1191; P8BE-NEXT: lwz r5, 32(r3) 1192; P8BE-NEXT: lwz r6, 16(r3) 1193; P8BE-NEXT: lwz r3, 4(r3) 1194; P8BE-NEXT: rldimi r5, r4, 32, 0 1195; P8BE-NEXT: rldimi r3, r6, 32, 0 1196; P8BE-NEXT: mtfprd f0, r5 1197; P8BE-NEXT: mtfprd f1, r3 1198; P8BE-NEXT: xxmrghd v2, vs1, vs0 1199; P8BE-NEXT: blr 1200; 1201; P8LE-LABEL: fromRandMemVari: 1202; P8LE: # %bb.0: # %entry 1203; P8LE-NEXT: sldi r4, r4, 2 1204; P8LE-NEXT: add r3, r3, r4 1205; P8LE-NEXT: lwz r4, 16(r3) 1206; P8LE-NEXT: lwz r5, 4(r3) 1207; P8LE-NEXT: lwz r6, 8(r3) 1208; P8LE-NEXT: lwz r3, 32(r3) 1209; P8LE-NEXT: rldimi r4, r5, 32, 0 1210; P8LE-NEXT: rldimi r6, r3, 32, 0 1211; P8LE-NEXT: mtfprd f0, r4 1212; P8LE-NEXT: mtfprd f1, r6 1213; P8LE-NEXT: xxmrghd v2, vs1, vs0 1214; P8LE-NEXT: blr 1215entry: 1216 %add = add nsw i32 %elem, 4 1217 %idxprom = sext i32 %add to i64 1218 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1219 %0 = load i32, i32* %arrayidx, align 4 1220 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1221 %add1 = add nsw i32 %elem, 1 1222 %idxprom2 = sext i32 %add1 to i64 1223 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1224 %1 = load i32, i32* %arrayidx3, align 4 1225 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1226 %add5 = add nsw i32 %elem, 2 1227 %idxprom6 = sext i32 %add5 to i64 1228 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1229 %2 = load i32, i32* %arrayidx7, align 4 1230 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1231 %add9 = add nsw i32 %elem, 8 1232 %idxprom10 = sext i32 %add9 to i64 1233 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1234 %3 = load i32, i32* %arrayidx11, align 4 1235 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1236 ret <4 x i32> %vecinit12 1237} 1238 1239define <4 x i32> @spltRegVali(i32 signext %val) { 1240; P9BE-LABEL: spltRegVali: 1241; P9BE: # %bb.0: # %entry 1242; P9BE-NEXT: mtvsrws v2, r3 1243; P9BE-NEXT: blr 1244; 1245; P9LE-LABEL: spltRegVali: 1246; P9LE: # %bb.0: # %entry 1247; P9LE-NEXT: mtvsrws v2, r3 1248; P9LE-NEXT: blr 1249; 1250; P8BE-LABEL: spltRegVali: 1251; P8BE: # %bb.0: # %entry 1252; P8BE-NEXT: mtfprwz f0, r3 1253; P8BE-NEXT: xxspltw v2, vs0, 1 1254; P8BE-NEXT: blr 1255; 1256; P8LE-LABEL: spltRegVali: 1257; P8LE: # %bb.0: # %entry 1258; P8LE-NEXT: mtfprwz f0, r3 1259; P8LE-NEXT: xxspltw v2, vs0, 1 1260; P8LE-NEXT: blr 1261entry: 1262 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1263 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1264 ret <4 x i32> %splat.splat 1265} 1266 1267define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1268; P9BE-LABEL: spltMemVali: 1269; P9BE: # %bb.0: # %entry 1270; P9BE-NEXT: lxvwsx v2, 0, r3 1271; P9BE-NEXT: blr 1272; 1273; P9LE-LABEL: spltMemVali: 1274; P9LE: # %bb.0: # %entry 1275; P9LE-NEXT: lxvwsx v2, 0, r3 1276; P9LE-NEXT: blr 1277; 1278; P8BE-LABEL: spltMemVali: 1279; P8BE: # %bb.0: # %entry 1280; P8BE-NEXT: lfiwzx f0, 0, r3 1281; P8BE-NEXT: xxspltw v2, vs0, 1 1282; P8BE-NEXT: blr 1283; 1284; P8LE-LABEL: spltMemVali: 1285; P8LE: # %bb.0: # %entry 1286; P8LE-NEXT: lfiwzx f0, 0, r3 1287; P8LE-NEXT: xxspltw v2, vs0, 1 1288; P8LE-NEXT: blr 1289entry: 1290 %0 = load i32, i32* %ptr, align 4 1291 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1292 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1293 ret <4 x i32> %splat.splat 1294} 1295 1296define <4 x i32> @spltCnstConvftoi() { 1297; P9BE-LABEL: spltCnstConvftoi: 1298; P9BE: # %bb.0: # %entry 1299; P9BE-NEXT: vspltisw v2, 4 1300; P9BE-NEXT: blr 1301; 1302; P9LE-LABEL: spltCnstConvftoi: 1303; P9LE: # %bb.0: # %entry 1304; P9LE-NEXT: vspltisw v2, 4 1305; P9LE-NEXT: blr 1306; 1307; P8BE-LABEL: spltCnstConvftoi: 1308; P8BE: # %bb.0: # %entry 1309; P8BE-NEXT: vspltisw v2, 4 1310; P8BE-NEXT: blr 1311; 1312; P8LE-LABEL: spltCnstConvftoi: 1313; P8LE: # %bb.0: # %entry 1314; P8LE-NEXT: vspltisw v2, 4 1315; P8LE-NEXT: blr 1316entry: 1317 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1318} 1319 1320define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1321; P9BE-LABEL: fromRegsConvftoi: 1322; P9BE: # %bb.0: # %entry 1323; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1324; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1325; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1326; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1327; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1328; P9BE-NEXT: xvcvdpsxws v2, vs0 1329; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1330; P9BE-NEXT: xvcvdpsxws v3, vs0 1331; P9BE-NEXT: vmrgew v2, v3, v2 1332; P9BE-NEXT: blr 1333; 1334; P9LE-LABEL: fromRegsConvftoi: 1335; P9LE: # %bb.0: # %entry 1336; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1337; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1338; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1339; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1340; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1341; P9LE-NEXT: xvcvdpsxws v2, vs0 1342; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1343; P9LE-NEXT: xvcvdpsxws v3, vs0 1344; P9LE-NEXT: vmrgew v2, v3, v2 1345; P9LE-NEXT: blr 1346; 1347; P8BE-LABEL: fromRegsConvftoi: 1348; P8BE: # %bb.0: # %entry 1349; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1350; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1351; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1352; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1353; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1354; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1355; P8BE-NEXT: xvcvdpsxws v2, vs0 1356; P8BE-NEXT: xvcvdpsxws v3, vs1 1357; P8BE-NEXT: vmrgew v2, v3, v2 1358; P8BE-NEXT: blr 1359; 1360; P8LE-LABEL: fromRegsConvftoi: 1361; P8LE: # %bb.0: # %entry 1362; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1363; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1364; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1365; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1366; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1367; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1368; P8LE-NEXT: xvcvdpsxws v2, vs0 1369; P8LE-NEXT: xvcvdpsxws v3, vs1 1370; P8LE-NEXT: vmrgew v2, v3, v2 1371; P8LE-NEXT: blr 1372entry: 1373 %conv = fptosi float %a to i32 1374 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1375 %conv1 = fptosi float %b to i32 1376 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1377 %conv3 = fptosi float %c to i32 1378 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1379 %conv5 = fptosi float %d to i32 1380 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1381 ret <4 x i32> %vecinit6 1382} 1383 1384define <4 x i32> @fromDiffConstsConvftoi() { 1385; P9BE-LABEL: fromDiffConstsConvftoi: 1386; P9BE: # %bb.0: # %entry 1387; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1388; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1389; P9BE-NEXT: lxv v2, 0(r3) 1390; P9BE-NEXT: blr 1391; 1392; P9LE-LABEL: fromDiffConstsConvftoi: 1393; P9LE: # %bb.0: # %entry 1394; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1395; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1396; P9LE-NEXT: lxv v2, 0(r3) 1397; P9LE-NEXT: blr 1398; 1399; P8BE-LABEL: fromDiffConstsConvftoi: 1400; P8BE: # %bb.0: # %entry 1401; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1402; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1403; P8BE-NEXT: lxvw4x v2, 0, r3 1404; P8BE-NEXT: blr 1405; 1406; P8LE-LABEL: fromDiffConstsConvftoi: 1407; P8LE: # %bb.0: # %entry 1408; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1409; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1410; P8LE-NEXT: lxvd2x vs0, 0, r3 1411; P8LE-NEXT: xxswapd v2, vs0 1412; P8LE-NEXT: blr 1413entry: 1414 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1415} 1416 1417define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1418; P9BE-LABEL: fromDiffMemConsAConvftoi: 1419; P9BE: # %bb.0: # %entry 1420; P9BE-NEXT: lxv vs0, 0(r3) 1421; P9BE-NEXT: xvcvspsxws v2, vs0 1422; P9BE-NEXT: blr 1423; 1424; P9LE-LABEL: fromDiffMemConsAConvftoi: 1425; P9LE: # %bb.0: # %entry 1426; P9LE-NEXT: lxv vs0, 0(r3) 1427; P9LE-NEXT: xvcvspsxws v2, vs0 1428; P9LE-NEXT: blr 1429; 1430; P8BE-LABEL: fromDiffMemConsAConvftoi: 1431; P8BE: # %bb.0: # %entry 1432; P8BE-NEXT: lxvw4x vs0, 0, r3 1433; P8BE-NEXT: xvcvspsxws v2, vs0 1434; P8BE-NEXT: blr 1435; 1436; P8LE-LABEL: fromDiffMemConsAConvftoi: 1437; P8LE: # %bb.0: # %entry 1438; P8LE-NEXT: lxvd2x vs0, 0, r3 1439; P8LE-NEXT: xxswapd v2, vs0 1440; P8LE-NEXT: xvcvspsxws v2, v2 1441; P8LE-NEXT: blr 1442entry: 1443 %0 = bitcast float* %ptr to <4 x float>* 1444 %1 = load <4 x float>, <4 x float>* %0, align 4 1445 %2 = fptosi <4 x float> %1 to <4 x i32> 1446 ret <4 x i32> %2 1447} 1448 1449define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1450; P9BE-LABEL: fromDiffMemConsDConvftoi: 1451; P9BE: # %bb.0: # %entry 1452; P9BE-NEXT: lxv v2, 0(r3) 1453; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1454; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1455; P9BE-NEXT: lxv v3, 0(r3) 1456; P9BE-NEXT: vperm v2, v2, v2, v3 1457; P9BE-NEXT: xvcvspsxws v2, v2 1458; P9BE-NEXT: blr 1459; 1460; P9LE-LABEL: fromDiffMemConsDConvftoi: 1461; P9LE: # %bb.0: # %entry 1462; P9LE-NEXT: lxv v2, 0(r3) 1463; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1464; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1465; P9LE-NEXT: lxv v3, 0(r3) 1466; P9LE-NEXT: vperm v2, v2, v2, v3 1467; P9LE-NEXT: xvcvspsxws v2, v2 1468; P9LE-NEXT: blr 1469; 1470; P8BE-LABEL: fromDiffMemConsDConvftoi: 1471; P8BE: # %bb.0: # %entry 1472; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1473; P8BE-NEXT: lxvw4x v2, 0, r3 1474; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1475; P8BE-NEXT: lxvw4x v3, 0, r4 1476; P8BE-NEXT: vperm v2, v2, v2, v3 1477; P8BE-NEXT: xvcvspsxws v2, v2 1478; P8BE-NEXT: blr 1479; 1480; P8LE-LABEL: fromDiffMemConsDConvftoi: 1481; P8LE: # %bb.0: # %entry 1482; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1483; P8LE-NEXT: lxvd2x vs0, 0, r3 1484; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1485; P8LE-NEXT: lxvd2x vs1, 0, r4 1486; P8LE-NEXT: xxswapd v2, vs0 1487; P8LE-NEXT: xxswapd v3, vs1 1488; P8LE-NEXT: vperm v2, v2, v2, v3 1489; P8LE-NEXT: xvcvspsxws v2, v2 1490; P8LE-NEXT: blr 1491entry: 1492 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1493 %0 = load float, float* %arrayidx, align 4 1494 %conv = fptosi float %0 to i32 1495 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1496 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1497 %1 = load float, float* %arrayidx1, align 4 1498 %conv2 = fptosi float %1 to i32 1499 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1500 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1501 %2 = load float, float* %arrayidx4, align 4 1502 %conv5 = fptosi float %2 to i32 1503 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1504 %3 = load float, float* %ptr, align 4 1505 %conv8 = fptosi float %3 to i32 1506 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1507 ret <4 x i32> %vecinit9 1508} 1509 1510define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1511; P9BE-LABEL: fromDiffMemVarAConvftoi: 1512; P9BE: # %bb.0: # %entry 1513; P9BE-NEXT: sldi r4, r4, 2 1514; P9BE-NEXT: lfsux f0, r3, r4 1515; P9BE-NEXT: lfs f1, 12(r3) 1516; P9BE-NEXT: lfs f2, 4(r3) 1517; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1518; P9BE-NEXT: xvcvdpsp v2, vs1 1519; P9BE-NEXT: lfs f1, 8(r3) 1520; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1521; P9BE-NEXT: xvcvdpsp v3, vs0 1522; P9BE-NEXT: vmrgew v2, v3, v2 1523; P9BE-NEXT: xvcvspsxws v2, v2 1524; P9BE-NEXT: blr 1525; 1526; P9LE-LABEL: fromDiffMemVarAConvftoi: 1527; P9LE: # %bb.0: # %entry 1528; P9LE-NEXT: sldi r4, r4, 2 1529; P9LE-NEXT: lfsux f0, r3, r4 1530; P9LE-NEXT: lfs f1, 8(r3) 1531; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1532; P9LE-NEXT: lfs f1, 12(r3) 1533; P9LE-NEXT: xvcvdpsp v2, vs0 1534; P9LE-NEXT: lfs f0, 4(r3) 1535; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1536; P9LE-NEXT: xvcvdpsp v3, vs0 1537; P9LE-NEXT: vmrgew v2, v3, v2 1538; P9LE-NEXT: xvcvspsxws v2, v2 1539; P9LE-NEXT: blr 1540; 1541; P8BE-LABEL: fromDiffMemVarAConvftoi: 1542; P8BE: # %bb.0: # %entry 1543; P8BE-NEXT: sldi r4, r4, 2 1544; P8BE-NEXT: lfsux f0, r3, r4 1545; P8BE-NEXT: lfs f1, 12(r3) 1546; P8BE-NEXT: lfs f2, 4(r3) 1547; P8BE-NEXT: lfs f3, 8(r3) 1548; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1549; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1550; P8BE-NEXT: xvcvdpsp v2, vs1 1551; P8BE-NEXT: xvcvdpsp v3, vs0 1552; P8BE-NEXT: vmrgew v2, v3, v2 1553; P8BE-NEXT: xvcvspsxws v2, v2 1554; P8BE-NEXT: blr 1555; 1556; P8LE-LABEL: fromDiffMemVarAConvftoi: 1557; P8LE: # %bb.0: # %entry 1558; P8LE-NEXT: sldi r4, r4, 2 1559; P8LE-NEXT: lfsux f0, r3, r4 1560; P8LE-NEXT: lfs f1, 8(r3) 1561; P8LE-NEXT: lfs f2, 4(r3) 1562; P8LE-NEXT: lfs f3, 12(r3) 1563; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1564; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1565; P8LE-NEXT: xvcvdpsp v2, vs0 1566; P8LE-NEXT: xvcvdpsp v3, vs1 1567; P8LE-NEXT: vmrgew v2, v3, v2 1568; P8LE-NEXT: xvcvspsxws v2, v2 1569; P8LE-NEXT: blr 1570entry: 1571 %idxprom = sext i32 %elem to i64 1572 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1573 %0 = load float, float* %arrayidx, align 4 1574 %conv = fptosi float %0 to i32 1575 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1576 %add = add nsw i32 %elem, 1 1577 %idxprom1 = sext i32 %add to i64 1578 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1579 %1 = load float, float* %arrayidx2, align 4 1580 %conv3 = fptosi float %1 to i32 1581 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1582 %add5 = add nsw i32 %elem, 2 1583 %idxprom6 = sext i32 %add5 to i64 1584 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1585 %2 = load float, float* %arrayidx7, align 4 1586 %conv8 = fptosi float %2 to i32 1587 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1588 %add10 = add nsw i32 %elem, 3 1589 %idxprom11 = sext i32 %add10 to i64 1590 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1591 %3 = load float, float* %arrayidx12, align 4 1592 %conv13 = fptosi float %3 to i32 1593 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1594 ret <4 x i32> %vecinit14 1595} 1596 1597define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1598; P9BE-LABEL: fromDiffMemVarDConvftoi: 1599; P9BE: # %bb.0: # %entry 1600; P9BE-NEXT: sldi r4, r4, 2 1601; P9BE-NEXT: lfsux f0, r3, r4 1602; P9BE-NEXT: lfs f1, -12(r3) 1603; P9BE-NEXT: lfs f2, -4(r3) 1604; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1605; P9BE-NEXT: xvcvdpsp v2, vs1 1606; P9BE-NEXT: lfs f1, -8(r3) 1607; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1608; P9BE-NEXT: xvcvdpsp v3, vs0 1609; P9BE-NEXT: vmrgew v2, v3, v2 1610; P9BE-NEXT: xvcvspsxws v2, v2 1611; P9BE-NEXT: blr 1612; 1613; P9LE-LABEL: fromDiffMemVarDConvftoi: 1614; P9LE: # %bb.0: # %entry 1615; P9LE-NEXT: sldi r4, r4, 2 1616; P9LE-NEXT: lfsux f0, r3, r4 1617; P9LE-NEXT: lfs f1, -8(r3) 1618; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1619; P9LE-NEXT: lfs f1, -12(r3) 1620; P9LE-NEXT: xvcvdpsp v2, vs0 1621; P9LE-NEXT: lfs f0, -4(r3) 1622; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1623; P9LE-NEXT: xvcvdpsp v3, vs0 1624; P9LE-NEXT: vmrgew v2, v3, v2 1625; P9LE-NEXT: xvcvspsxws v2, v2 1626; P9LE-NEXT: blr 1627; 1628; P8BE-LABEL: fromDiffMemVarDConvftoi: 1629; P8BE: # %bb.0: # %entry 1630; P8BE-NEXT: sldi r4, r4, 2 1631; P8BE-NEXT: lfsux f0, r3, r4 1632; P8BE-NEXT: lfs f1, -12(r3) 1633; P8BE-NEXT: lfs f2, -4(r3) 1634; P8BE-NEXT: lfs f3, -8(r3) 1635; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1636; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1637; P8BE-NEXT: xvcvdpsp v2, vs1 1638; P8BE-NEXT: xvcvdpsp v3, vs0 1639; P8BE-NEXT: vmrgew v2, v3, v2 1640; P8BE-NEXT: xvcvspsxws v2, v2 1641; P8BE-NEXT: blr 1642; 1643; P8LE-LABEL: fromDiffMemVarDConvftoi: 1644; P8LE: # %bb.0: # %entry 1645; P8LE-NEXT: sldi r4, r4, 2 1646; P8LE-NEXT: lfsux f0, r3, r4 1647; P8LE-NEXT: lfs f1, -8(r3) 1648; P8LE-NEXT: lfs f2, -4(r3) 1649; P8LE-NEXT: lfs f3, -12(r3) 1650; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1651; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1652; P8LE-NEXT: xvcvdpsp v2, vs0 1653; P8LE-NEXT: xvcvdpsp v3, vs1 1654; P8LE-NEXT: vmrgew v2, v3, v2 1655; P8LE-NEXT: xvcvspsxws v2, v2 1656; P8LE-NEXT: blr 1657entry: 1658 %idxprom = sext i32 %elem to i64 1659 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1660 %0 = load float, float* %arrayidx, align 4 1661 %conv = fptosi float %0 to i32 1662 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1663 %sub = add nsw i32 %elem, -1 1664 %idxprom1 = sext i32 %sub to i64 1665 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1666 %1 = load float, float* %arrayidx2, align 4 1667 %conv3 = fptosi float %1 to i32 1668 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1669 %sub5 = add nsw i32 %elem, -2 1670 %idxprom6 = sext i32 %sub5 to i64 1671 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1672 %2 = load float, float* %arrayidx7, align 4 1673 %conv8 = fptosi float %2 to i32 1674 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1675 %sub10 = add nsw i32 %elem, -3 1676 %idxprom11 = sext i32 %sub10 to i64 1677 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1678 %3 = load float, float* %arrayidx12, align 4 1679 %conv13 = fptosi float %3 to i32 1680 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1681 ret <4 x i32> %vecinit14 1682; FIXME: implement finding consecutive loads with pre-inc 1683} 1684 1685define <4 x i32> @spltRegValConvftoi(float %val) { 1686; P9BE-LABEL: spltRegValConvftoi: 1687; P9BE: # %bb.0: # %entry 1688; P9BE-NEXT: xscvdpsxws f0, f1 1689; P9BE-NEXT: xxspltw v2, vs0, 1 1690; P9BE-NEXT: blr 1691; 1692; P9LE-LABEL: spltRegValConvftoi: 1693; P9LE: # %bb.0: # %entry 1694; P9LE-NEXT: xscvdpsxws f0, f1 1695; P9LE-NEXT: xxspltw v2, vs0, 1 1696; P9LE-NEXT: blr 1697; 1698; P8BE-LABEL: spltRegValConvftoi: 1699; P8BE: # %bb.0: # %entry 1700; P8BE-NEXT: xscvdpsxws f0, f1 1701; P8BE-NEXT: xxspltw v2, vs0, 1 1702; P8BE-NEXT: blr 1703; 1704; P8LE-LABEL: spltRegValConvftoi: 1705; P8LE: # %bb.0: # %entry 1706; P8LE-NEXT: xscvdpsxws f0, f1 1707; P8LE-NEXT: xxspltw v2, vs0, 1 1708; P8LE-NEXT: blr 1709entry: 1710 %conv = fptosi float %val to i32 1711 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1712 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1713 ret <4 x i32> %splat.splat 1714} 1715 1716define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1717; P9BE-LABEL: spltMemValConvftoi: 1718; P9BE: # %bb.0: # %entry 1719; P9BE-NEXT: lfiwzx f0, 0, r3 1720; P9BE-NEXT: xvcvspsxws vs0, vs0 1721; P9BE-NEXT: xxspltw v2, vs0, 1 1722; P9BE-NEXT: blr 1723; 1724; P9LE-LABEL: spltMemValConvftoi: 1725; P9LE: # %bb.0: # %entry 1726; P9LE-NEXT: lfiwzx f0, 0, r3 1727; P9LE-NEXT: xvcvspsxws vs0, vs0 1728; P9LE-NEXT: xxspltw v2, vs0, 1 1729; P9LE-NEXT: blr 1730; 1731; P8BE-LABEL: spltMemValConvftoi: 1732; P8BE: # %bb.0: # %entry 1733; P8BE-NEXT: lfsx f0, 0, r3 1734; P8BE-NEXT: xscvdpsxws f0, f0 1735; P8BE-NEXT: xxspltw v2, vs0, 1 1736; P8BE-NEXT: blr 1737; 1738; P8LE-LABEL: spltMemValConvftoi: 1739; P8LE: # %bb.0: # %entry 1740; P8LE-NEXT: lfsx f0, 0, r3 1741; P8LE-NEXT: xscvdpsxws f0, f0 1742; P8LE-NEXT: xxspltw v2, vs0, 1 1743; P8LE-NEXT: blr 1744entry: 1745 %0 = load float, float* %ptr, align 4 1746 %conv = fptosi float %0 to i32 1747 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1748 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1749 ret <4 x i32> %splat.splat 1750} 1751 1752define <4 x i32> @spltCnstConvdtoi() { 1753; P9BE-LABEL: spltCnstConvdtoi: 1754; P9BE: # %bb.0: # %entry 1755; P9BE-NEXT: vspltisw v2, 4 1756; P9BE-NEXT: blr 1757; 1758; P9LE-LABEL: spltCnstConvdtoi: 1759; P9LE: # %bb.0: # %entry 1760; P9LE-NEXT: vspltisw v2, 4 1761; P9LE-NEXT: blr 1762; 1763; P8BE-LABEL: spltCnstConvdtoi: 1764; P8BE: # %bb.0: # %entry 1765; P8BE-NEXT: vspltisw v2, 4 1766; P8BE-NEXT: blr 1767; 1768; P8LE-LABEL: spltCnstConvdtoi: 1769; P8LE: # %bb.0: # %entry 1770; P8LE-NEXT: vspltisw v2, 4 1771; P8LE-NEXT: blr 1772entry: 1773 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1774} 1775 1776define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1777; P9BE-LABEL: fromRegsConvdtoi: 1778; P9BE: # %bb.0: # %entry 1779; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1780; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1781; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1782; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1783; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1784; P9BE-NEXT: xvcvdpsxws v2, vs0 1785; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1786; P9BE-NEXT: xvcvdpsxws v3, vs0 1787; P9BE-NEXT: vmrgew v2, v3, v2 1788; P9BE-NEXT: blr 1789; 1790; P9LE-LABEL: fromRegsConvdtoi: 1791; P9LE: # %bb.0: # %entry 1792; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1793; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1794; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1795; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1796; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1797; P9LE-NEXT: xvcvdpsxws v2, vs0 1798; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1799; P9LE-NEXT: xvcvdpsxws v3, vs0 1800; P9LE-NEXT: vmrgew v2, v3, v2 1801; P9LE-NEXT: blr 1802; 1803; P8BE-LABEL: fromRegsConvdtoi: 1804; P8BE: # %bb.0: # %entry 1805; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1806; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1807; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1808; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1809; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1810; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1811; P8BE-NEXT: xvcvdpsxws v2, vs0 1812; P8BE-NEXT: xvcvdpsxws v3, vs1 1813; P8BE-NEXT: vmrgew v2, v3, v2 1814; P8BE-NEXT: blr 1815; 1816; P8LE-LABEL: fromRegsConvdtoi: 1817; P8LE: # %bb.0: # %entry 1818; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1819; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1820; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1821; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1822; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1823; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1824; P8LE-NEXT: xvcvdpsxws v2, vs0 1825; P8LE-NEXT: xvcvdpsxws v3, vs1 1826; P8LE-NEXT: vmrgew v2, v3, v2 1827; P8LE-NEXT: blr 1828entry: 1829 %conv = fptosi double %a to i32 1830 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1831 %conv1 = fptosi double %b to i32 1832 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1833 %conv3 = fptosi double %c to i32 1834 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1835 %conv5 = fptosi double %d to i32 1836 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1837 ret <4 x i32> %vecinit6 1838} 1839 1840define <4 x i32> @fromDiffConstsConvdtoi() { 1841; P9BE-LABEL: fromDiffConstsConvdtoi: 1842; P9BE: # %bb.0: # %entry 1843; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1844; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1845; P9BE-NEXT: lxv v2, 0(r3) 1846; P9BE-NEXT: blr 1847; 1848; P9LE-LABEL: fromDiffConstsConvdtoi: 1849; P9LE: # %bb.0: # %entry 1850; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1851; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1852; P9LE-NEXT: lxv v2, 0(r3) 1853; P9LE-NEXT: blr 1854; 1855; P8BE-LABEL: fromDiffConstsConvdtoi: 1856; P8BE: # %bb.0: # %entry 1857; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1858; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1859; P8BE-NEXT: lxvw4x v2, 0, r3 1860; P8BE-NEXT: blr 1861; 1862; P8LE-LABEL: fromDiffConstsConvdtoi: 1863; P8LE: # %bb.0: # %entry 1864; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1865; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1866; P8LE-NEXT: lxvd2x vs0, 0, r3 1867; P8LE-NEXT: xxswapd v2, vs0 1868; P8LE-NEXT: blr 1869entry: 1870 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1871} 1872 1873define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1874; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1875; P9BE: # %bb.0: # %entry 1876; P9BE-NEXT: lxv vs0, 0(r3) 1877; P9BE-NEXT: lxv vs1, 16(r3) 1878; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1879; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1880; P9BE-NEXT: xvcvdpsxws v2, vs2 1881; P9BE-NEXT: xvcvdpsxws v3, vs0 1882; P9BE-NEXT: vmrgew v2, v3, v2 1883; P9BE-NEXT: blr 1884; 1885; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1886; P9LE: # %bb.0: # %entry 1887; P9LE-NEXT: lxv vs0, 0(r3) 1888; P9LE-NEXT: lxv vs1, 16(r3) 1889; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1890; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1891; P9LE-NEXT: xvcvdpsxws v2, vs2 1892; P9LE-NEXT: xvcvdpsxws v3, vs0 1893; P9LE-NEXT: vmrgew v2, v3, v2 1894; P9LE-NEXT: blr 1895; 1896; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1897; P8BE: # %bb.0: # %entry 1898; P8BE-NEXT: li r4, 16 1899; P8BE-NEXT: lxvd2x vs0, 0, r3 1900; P8BE-NEXT: lxvd2x vs1, r3, r4 1901; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1902; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1903; P8BE-NEXT: xvcvdpsxws v2, vs2 1904; P8BE-NEXT: xvcvdpsxws v3, vs0 1905; P8BE-NEXT: vmrgew v2, v3, v2 1906; P8BE-NEXT: blr 1907; 1908; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1909; P8LE: # %bb.0: # %entry 1910; P8LE-NEXT: li r4, 16 1911; P8LE-NEXT: lxvd2x vs0, 0, r3 1912; P8LE-NEXT: lxvd2x vs1, r3, r4 1913; P8LE-NEXT: xxswapd vs0, vs0 1914; P8LE-NEXT: xxswapd vs1, vs1 1915; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1916; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1917; P8LE-NEXT: xvcvdpsxws v2, vs2 1918; P8LE-NEXT: xvcvdpsxws v3, vs0 1919; P8LE-NEXT: vmrgew v2, v3, v2 1920; P8LE-NEXT: blr 1921entry: 1922 %0 = bitcast double* %ptr to <2 x double>* 1923 %1 = load <2 x double>, <2 x double>* %0, align 8 1924 %2 = fptosi <2 x double> %1 to <2 x i32> 1925 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1926 %3 = bitcast double* %arrayidx4 to <2 x double>* 1927 %4 = load <2 x double>, <2 x double>* %3, align 8 1928 %5 = fptosi <2 x double> %4 to <2 x i32> 1929 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1930 ret <4 x i32> %vecinit9 1931} 1932 1933define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1934; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1935; P9BE: # %bb.0: # %entry 1936; P9BE-NEXT: lfd f0, 24(r3) 1937; P9BE-NEXT: lfd f1, 16(r3) 1938; P9BE-NEXT: lfd f2, 8(r3) 1939; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1940; P9BE-NEXT: lfd f3, 0(r3) 1941; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1942; P9BE-NEXT: xvcvdpsxws v2, vs1 1943; P9BE-NEXT: xvcvdpsxws v3, vs0 1944; P9BE-NEXT: vmrgew v2, v3, v2 1945; P9BE-NEXT: blr 1946; 1947; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1948; P9LE: # %bb.0: # %entry 1949; P9LE-NEXT: lfd f0, 24(r3) 1950; P9LE-NEXT: lfd f2, 8(r3) 1951; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1952; P9LE-NEXT: lfd f1, 16(r3) 1953; P9LE-NEXT: lfd f3, 0(r3) 1954; P9LE-NEXT: xvcvdpsxws v2, vs0 1955; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1956; P9LE-NEXT: xvcvdpsxws v3, vs0 1957; P9LE-NEXT: vmrgew v2, v3, v2 1958; P9LE-NEXT: blr 1959; 1960; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1961; P8BE: # %bb.0: # %entry 1962; P8BE-NEXT: lfd f0, 16(r3) 1963; P8BE-NEXT: lfd f1, 0(r3) 1964; P8BE-NEXT: lfd f2, 24(r3) 1965; P8BE-NEXT: lfd f3, 8(r3) 1966; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1967; P8BE-NEXT: xxmrghd vs1, vs2, vs3 1968; P8BE-NEXT: xvcvdpsxws v2, vs0 1969; P8BE-NEXT: xvcvdpsxws v3, vs1 1970; P8BE-NEXT: vmrgew v2, v3, v2 1971; P8BE-NEXT: blr 1972; 1973; P8LE-LABEL: fromDiffMemConsDConvdtoi: 1974; P8LE: # %bb.0: # %entry 1975; P8LE-NEXT: lfd f0, 24(r3) 1976; P8LE-NEXT: lfd f1, 8(r3) 1977; P8LE-NEXT: lfd f2, 16(r3) 1978; P8LE-NEXT: lfd f3, 0(r3) 1979; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1980; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1981; P8LE-NEXT: xvcvdpsxws v2, vs0 1982; P8LE-NEXT: xvcvdpsxws v3, vs1 1983; P8LE-NEXT: vmrgew v2, v3, v2 1984; P8LE-NEXT: blr 1985entry: 1986 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1987 %0 = load double, double* %arrayidx, align 8 1988 %conv = fptosi double %0 to i32 1989 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1990 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1991 %1 = load double, double* %arrayidx1, align 8 1992 %conv2 = fptosi double %1 to i32 1993 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1994 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1995 %2 = load double, double* %arrayidx4, align 8 1996 %conv5 = fptosi double %2 to i32 1997 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1998 %3 = load double, double* %ptr, align 8 1999 %conv8 = fptosi double %3 to i32 2000 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2001 ret <4 x i32> %vecinit9 2002} 2003 2004define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2005; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2006; P9BE: # %bb.0: # %entry 2007; P9BE-NEXT: sldi r4, r4, 3 2008; P9BE-NEXT: lfdux f0, r3, r4 2009; P9BE-NEXT: lfd f1, 8(r3) 2010; P9BE-NEXT: lfd f2, 16(r3) 2011; P9BE-NEXT: lfd f3, 24(r3) 2012; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2013; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2014; P9BE-NEXT: xvcvdpsxws v2, vs1 2015; P9BE-NEXT: xvcvdpsxws v3, vs0 2016; P9BE-NEXT: vmrgew v2, v3, v2 2017; P9BE-NEXT: blr 2018; 2019; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2020; P9LE: # %bb.0: # %entry 2021; P9LE-NEXT: sldi r4, r4, 3 2022; P9LE-NEXT: lfdux f0, r3, r4 2023; P9LE-NEXT: lfd f2, 16(r3) 2024; P9LE-NEXT: lfd f1, 8(r3) 2025; P9LE-NEXT: lfd f3, 24(r3) 2026; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2027; P9LE-NEXT: xvcvdpsxws v2, vs0 2028; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2029; P9LE-NEXT: xvcvdpsxws v3, vs0 2030; P9LE-NEXT: vmrgew v2, v3, v2 2031; P9LE-NEXT: blr 2032; 2033; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2034; P8BE: # %bb.0: # %entry 2035; P8BE-NEXT: sldi r4, r4, 3 2036; P8BE-NEXT: lfdux f0, r3, r4 2037; P8BE-NEXT: lfd f1, 8(r3) 2038; P8BE-NEXT: lfd f2, 24(r3) 2039; P8BE-NEXT: lfd f3, 16(r3) 2040; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2041; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2042; P8BE-NEXT: xvcvdpsxws v2, vs1 2043; P8BE-NEXT: xvcvdpsxws v3, vs0 2044; P8BE-NEXT: vmrgew v2, v3, v2 2045; P8BE-NEXT: blr 2046; 2047; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2048; P8LE: # %bb.0: # %entry 2049; P8LE-NEXT: sldi r4, r4, 3 2050; P8LE-NEXT: lfdux f0, r3, r4 2051; P8LE-NEXT: lfd f1, 16(r3) 2052; P8LE-NEXT: lfd f2, 8(r3) 2053; P8LE-NEXT: lfd f3, 24(r3) 2054; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2055; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2056; P8LE-NEXT: xvcvdpsxws v2, vs0 2057; P8LE-NEXT: xvcvdpsxws v3, vs1 2058; P8LE-NEXT: vmrgew v2, v3, v2 2059; P8LE-NEXT: blr 2060entry: 2061 %idxprom = sext i32 %elem to i64 2062 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2063 %0 = load double, double* %arrayidx, align 8 2064 %conv = fptosi double %0 to i32 2065 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2066 %add = add nsw i32 %elem, 1 2067 %idxprom1 = sext i32 %add to i64 2068 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2069 %1 = load double, double* %arrayidx2, align 8 2070 %conv3 = fptosi double %1 to i32 2071 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2072 %add5 = add nsw i32 %elem, 2 2073 %idxprom6 = sext i32 %add5 to i64 2074 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2075 %2 = load double, double* %arrayidx7, align 8 2076 %conv8 = fptosi double %2 to i32 2077 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2078 %add10 = add nsw i32 %elem, 3 2079 %idxprom11 = sext i32 %add10 to i64 2080 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2081 %3 = load double, double* %arrayidx12, align 8 2082 %conv13 = fptosi double %3 to i32 2083 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2084 ret <4 x i32> %vecinit14 2085} 2086 2087define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2088; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2089; P9BE: # %bb.0: # %entry 2090; P9BE-NEXT: sldi r4, r4, 3 2091; P9BE-NEXT: lfdux f0, r3, r4 2092; P9BE-NEXT: lfd f1, -8(r3) 2093; P9BE-NEXT: lfd f2, -16(r3) 2094; P9BE-NEXT: lfd f3, -24(r3) 2095; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2096; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2097; P9BE-NEXT: xvcvdpsxws v2, vs1 2098; P9BE-NEXT: xvcvdpsxws v3, vs0 2099; P9BE-NEXT: vmrgew v2, v3, v2 2100; P9BE-NEXT: blr 2101; 2102; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2103; P9LE: # %bb.0: # %entry 2104; P9LE-NEXT: sldi r4, r4, 3 2105; P9LE-NEXT: lfdux f0, r3, r4 2106; P9LE-NEXT: lfd f2, -16(r3) 2107; P9LE-NEXT: lfd f1, -8(r3) 2108; P9LE-NEXT: lfd f3, -24(r3) 2109; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2110; P9LE-NEXT: xvcvdpsxws v2, vs0 2111; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2112; P9LE-NEXT: xvcvdpsxws v3, vs0 2113; P9LE-NEXT: vmrgew v2, v3, v2 2114; P9LE-NEXT: blr 2115; 2116; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2117; P8BE: # %bb.0: # %entry 2118; P8BE-NEXT: sldi r4, r4, 3 2119; P8BE-NEXT: lfdux f0, r3, r4 2120; P8BE-NEXT: lfd f1, -8(r3) 2121; P8BE-NEXT: lfd f2, -24(r3) 2122; P8BE-NEXT: lfd f3, -16(r3) 2123; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2124; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2125; P8BE-NEXT: xvcvdpsxws v2, vs1 2126; P8BE-NEXT: xvcvdpsxws v3, vs0 2127; P8BE-NEXT: vmrgew v2, v3, v2 2128; P8BE-NEXT: blr 2129; 2130; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2131; P8LE: # %bb.0: # %entry 2132; P8LE-NEXT: sldi r4, r4, 3 2133; P8LE-NEXT: lfdux f0, r3, r4 2134; P8LE-NEXT: lfd f1, -16(r3) 2135; P8LE-NEXT: lfd f2, -8(r3) 2136; P8LE-NEXT: lfd f3, -24(r3) 2137; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2138; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2139; P8LE-NEXT: xvcvdpsxws v2, vs0 2140; P8LE-NEXT: xvcvdpsxws v3, vs1 2141; P8LE-NEXT: vmrgew v2, v3, v2 2142; P8LE-NEXT: blr 2143entry: 2144 %idxprom = sext i32 %elem to i64 2145 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2146 %0 = load double, double* %arrayidx, align 8 2147 %conv = fptosi double %0 to i32 2148 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2149 %sub = add nsw i32 %elem, -1 2150 %idxprom1 = sext i32 %sub to i64 2151 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2152 %1 = load double, double* %arrayidx2, align 8 2153 %conv3 = fptosi double %1 to i32 2154 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2155 %sub5 = add nsw i32 %elem, -2 2156 %idxprom6 = sext i32 %sub5 to i64 2157 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2158 %2 = load double, double* %arrayidx7, align 8 2159 %conv8 = fptosi double %2 to i32 2160 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2161 %sub10 = add nsw i32 %elem, -3 2162 %idxprom11 = sext i32 %sub10 to i64 2163 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2164 %3 = load double, double* %arrayidx12, align 8 2165 %conv13 = fptosi double %3 to i32 2166 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2167 ret <4 x i32> %vecinit14 2168} 2169 2170define <4 x i32> @spltRegValConvdtoi(double %val) { 2171; P9BE-LABEL: spltRegValConvdtoi: 2172; P9BE: # %bb.0: # %entry 2173; P9BE-NEXT: xscvdpsxws f0, f1 2174; P9BE-NEXT: xxspltw v2, vs0, 1 2175; P9BE-NEXT: blr 2176; 2177; P9LE-LABEL: spltRegValConvdtoi: 2178; P9LE: # %bb.0: # %entry 2179; P9LE-NEXT: xscvdpsxws f0, f1 2180; P9LE-NEXT: xxspltw v2, vs0, 1 2181; P9LE-NEXT: blr 2182; 2183; P8BE-LABEL: spltRegValConvdtoi: 2184; P8BE: # %bb.0: # %entry 2185; P8BE-NEXT: xscvdpsxws f0, f1 2186; P8BE-NEXT: xxspltw v2, vs0, 1 2187; P8BE-NEXT: blr 2188; 2189; P8LE-LABEL: spltRegValConvdtoi: 2190; P8LE: # %bb.0: # %entry 2191; P8LE-NEXT: xscvdpsxws f0, f1 2192; P8LE-NEXT: xxspltw v2, vs0, 1 2193; P8LE-NEXT: blr 2194entry: 2195 %conv = fptosi double %val to i32 2196 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2197 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2198 ret <4 x i32> %splat.splat 2199} 2200 2201define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2202; P9BE-LABEL: spltMemValConvdtoi: 2203; P9BE: # %bb.0: # %entry 2204; P9BE-NEXT: lfd f0, 0(r3) 2205; P9BE-NEXT: xscvdpsxws f0, f0 2206; P9BE-NEXT: xxspltw v2, vs0, 1 2207; P9BE-NEXT: blr 2208; 2209; P9LE-LABEL: spltMemValConvdtoi: 2210; P9LE: # %bb.0: # %entry 2211; P9LE-NEXT: lfd f0, 0(r3) 2212; P9LE-NEXT: xscvdpsxws f0, f0 2213; P9LE-NEXT: xxspltw v2, vs0, 1 2214; P9LE-NEXT: blr 2215; 2216; P8BE-LABEL: spltMemValConvdtoi: 2217; P8BE: # %bb.0: # %entry 2218; P8BE-NEXT: lfdx f0, 0, r3 2219; P8BE-NEXT: xscvdpsxws f0, f0 2220; P8BE-NEXT: xxspltw v2, vs0, 1 2221; P8BE-NEXT: blr 2222; 2223; P8LE-LABEL: spltMemValConvdtoi: 2224; P8LE: # %bb.0: # %entry 2225; P8LE-NEXT: lfdx f0, 0, r3 2226; P8LE-NEXT: xscvdpsxws f0, f0 2227; P8LE-NEXT: xxspltw v2, vs0, 1 2228; P8LE-NEXT: blr 2229entry: 2230 %0 = load double, double* %ptr, align 8 2231 %conv = fptosi double %0 to i32 2232 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2233 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2234 ret <4 x i32> %splat.splat 2235} 2236 2237define <4 x i32> @allZeroui() { 2238; P9BE-LABEL: allZeroui: 2239; P9BE: # %bb.0: # %entry 2240; P9BE-NEXT: xxlxor v2, v2, v2 2241; P9BE-NEXT: blr 2242; 2243; P9LE-LABEL: allZeroui: 2244; P9LE: # %bb.0: # %entry 2245; P9LE-NEXT: xxlxor v2, v2, v2 2246; P9LE-NEXT: blr 2247; 2248; P8BE-LABEL: allZeroui: 2249; P8BE: # %bb.0: # %entry 2250; P8BE-NEXT: xxlxor v2, v2, v2 2251; P8BE-NEXT: blr 2252; 2253; P8LE-LABEL: allZeroui: 2254; P8LE: # %bb.0: # %entry 2255; P8LE-NEXT: xxlxor v2, v2, v2 2256; P8LE-NEXT: blr 2257entry: 2258 ret <4 x i32> zeroinitializer 2259} 2260 2261define <4 x i32> @spltConst1ui() { 2262; P9BE-LABEL: spltConst1ui: 2263; P9BE: # %bb.0: # %entry 2264; P9BE-NEXT: vspltisw v2, 1 2265; P9BE-NEXT: blr 2266; 2267; P9LE-LABEL: spltConst1ui: 2268; P9LE: # %bb.0: # %entry 2269; P9LE-NEXT: vspltisw v2, 1 2270; P9LE-NEXT: blr 2271; 2272; P8BE-LABEL: spltConst1ui: 2273; P8BE: # %bb.0: # %entry 2274; P8BE-NEXT: vspltisw v2, 1 2275; P8BE-NEXT: blr 2276; 2277; P8LE-LABEL: spltConst1ui: 2278; P8LE: # %bb.0: # %entry 2279; P8LE-NEXT: vspltisw v2, 1 2280; P8LE-NEXT: blr 2281entry: 2282 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2283} 2284 2285define <4 x i32> @spltConst16kui() { 2286; P9BE-LABEL: spltConst16kui: 2287; P9BE: # %bb.0: # %entry 2288; P9BE-NEXT: vspltisw v2, -15 2289; P9BE-NEXT: vsrw v2, v2, v2 2290; P9BE-NEXT: blr 2291; 2292; P9LE-LABEL: spltConst16kui: 2293; P9LE: # %bb.0: # %entry 2294; P9LE-NEXT: vspltisw v2, -15 2295; P9LE-NEXT: vsrw v2, v2, v2 2296; P9LE-NEXT: blr 2297; 2298; P8BE-LABEL: spltConst16kui: 2299; P8BE: # %bb.0: # %entry 2300; P8BE-NEXT: vspltisw v2, -15 2301; P8BE-NEXT: vsrw v2, v2, v2 2302; P8BE-NEXT: blr 2303; 2304; P8LE-LABEL: spltConst16kui: 2305; P8LE: # %bb.0: # %entry 2306; P8LE-NEXT: vspltisw v2, -15 2307; P8LE-NEXT: vsrw v2, v2, v2 2308; P8LE-NEXT: blr 2309entry: 2310 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2311} 2312 2313define <4 x i32> @spltConst32kui() { 2314; P9BE-LABEL: spltConst32kui: 2315; P9BE: # %bb.0: # %entry 2316; P9BE-NEXT: vspltisw v2, -16 2317; P9BE-NEXT: vsrw v2, v2, v2 2318; P9BE-NEXT: blr 2319; 2320; P9LE-LABEL: spltConst32kui: 2321; P9LE: # %bb.0: # %entry 2322; P9LE-NEXT: vspltisw v2, -16 2323; P9LE-NEXT: vsrw v2, v2, v2 2324; P9LE-NEXT: blr 2325; 2326; P8BE-LABEL: spltConst32kui: 2327; P8BE: # %bb.0: # %entry 2328; P8BE-NEXT: vspltisw v2, -16 2329; P8BE-NEXT: vsrw v2, v2, v2 2330; P8BE-NEXT: blr 2331; 2332; P8LE-LABEL: spltConst32kui: 2333; P8LE: # %bb.0: # %entry 2334; P8LE-NEXT: vspltisw v2, -16 2335; P8LE-NEXT: vsrw v2, v2, v2 2336; P8LE-NEXT: blr 2337entry: 2338 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2339} 2340 2341define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2342; P9BE-LABEL: fromRegsui: 2343; P9BE: # %bb.0: # %entry 2344; P9BE-NEXT: rldimi r6, r5, 32, 0 2345; P9BE-NEXT: rldimi r4, r3, 32, 0 2346; P9BE-NEXT: mtvsrdd v2, r4, r6 2347; P9BE-NEXT: blr 2348; 2349; P9LE-LABEL: fromRegsui: 2350; P9LE: # %bb.0: # %entry 2351; P9LE-NEXT: rldimi r3, r4, 32, 0 2352; P9LE-NEXT: rldimi r5, r6, 32, 0 2353; P9LE-NEXT: mtvsrdd v2, r5, r3 2354; P9LE-NEXT: blr 2355; 2356; P8BE-LABEL: fromRegsui: 2357; P8BE: # %bb.0: # %entry 2358; P8BE-NEXT: rldimi r6, r5, 32, 0 2359; P8BE-NEXT: rldimi r4, r3, 32, 0 2360; P8BE-NEXT: mtfprd f0, r6 2361; P8BE-NEXT: mtfprd f1, r4 2362; P8BE-NEXT: xxmrghd v2, vs1, vs0 2363; P8BE-NEXT: blr 2364; 2365; P8LE-LABEL: fromRegsui: 2366; P8LE: # %bb.0: # %entry 2367; P8LE-NEXT: rldimi r3, r4, 32, 0 2368; P8LE-NEXT: rldimi r5, r6, 32, 0 2369; P8LE-NEXT: mtfprd f0, r3 2370; P8LE-NEXT: mtfprd f1, r5 2371; P8LE-NEXT: xxmrghd v2, vs1, vs0 2372; P8LE-NEXT: blr 2373entry: 2374 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2375 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2376 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2377 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2378 ret <4 x i32> %vecinit3 2379} 2380 2381define <4 x i32> @fromDiffConstsui() { 2382; P9BE-LABEL: fromDiffConstsui: 2383; P9BE: # %bb.0: # %entry 2384; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2385; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2386; P9BE-NEXT: lxv v2, 0(r3) 2387; P9BE-NEXT: blr 2388; 2389; P9LE-LABEL: fromDiffConstsui: 2390; P9LE: # %bb.0: # %entry 2391; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2392; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2393; P9LE-NEXT: lxv v2, 0(r3) 2394; P9LE-NEXT: blr 2395; 2396; P8BE-LABEL: fromDiffConstsui: 2397; P8BE: # %bb.0: # %entry 2398; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2399; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2400; P8BE-NEXT: lxvw4x v2, 0, r3 2401; P8BE-NEXT: blr 2402; 2403; P8LE-LABEL: fromDiffConstsui: 2404; P8LE: # %bb.0: # %entry 2405; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2406; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2407; P8LE-NEXT: lxvd2x vs0, 0, r3 2408; P8LE-NEXT: xxswapd v2, vs0 2409; P8LE-NEXT: blr 2410entry: 2411 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2412} 2413 2414define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2415; P9BE-LABEL: fromDiffMemConsAui: 2416; P9BE: # %bb.0: # %entry 2417; P9BE-NEXT: lxv v2, 0(r3) 2418; P9BE-NEXT: blr 2419; 2420; P9LE-LABEL: fromDiffMemConsAui: 2421; P9LE: # %bb.0: # %entry 2422; P9LE-NEXT: lxv v2, 0(r3) 2423; P9LE-NEXT: blr 2424; 2425; P8BE-LABEL: fromDiffMemConsAui: 2426; P8BE: # %bb.0: # %entry 2427; P8BE-NEXT: lxvw4x v2, 0, r3 2428; P8BE-NEXT: blr 2429; 2430; P8LE-LABEL: fromDiffMemConsAui: 2431; P8LE: # %bb.0: # %entry 2432; P8LE-NEXT: lxvd2x vs0, 0, r3 2433; P8LE-NEXT: xxswapd v2, vs0 2434; P8LE-NEXT: blr 2435entry: 2436 %0 = load i32, i32* %arr, align 4 2437 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2438 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2439 %1 = load i32, i32* %arrayidx1, align 4 2440 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2441 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2442 %2 = load i32, i32* %arrayidx3, align 4 2443 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2444 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2445 %3 = load i32, i32* %arrayidx5, align 4 2446 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2447 ret <4 x i32> %vecinit6 2448} 2449 2450define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2451; P9BE-LABEL: fromDiffMemConsDui: 2452; P9BE: # %bb.0: # %entry 2453; P9BE-NEXT: lxv v2, 0(r3) 2454; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2455; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2456; P9BE-NEXT: lxv v3, 0(r3) 2457; P9BE-NEXT: vperm v2, v2, v2, v3 2458; P9BE-NEXT: blr 2459; 2460; P9LE-LABEL: fromDiffMemConsDui: 2461; P9LE: # %bb.0: # %entry 2462; P9LE-NEXT: lxvw4x v2, 0, r3 2463; P9LE-NEXT: blr 2464; 2465; P8BE-LABEL: fromDiffMemConsDui: 2466; P8BE: # %bb.0: # %entry 2467; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2468; P8BE-NEXT: lxvw4x v2, 0, r3 2469; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2470; P8BE-NEXT: lxvw4x v3, 0, r4 2471; P8BE-NEXT: vperm v2, v2, v2, v3 2472; P8BE-NEXT: blr 2473; 2474; P8LE-LABEL: fromDiffMemConsDui: 2475; P8LE: # %bb.0: # %entry 2476; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2477; P8LE-NEXT: lxvd2x vs0, 0, r3 2478; P8LE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2479; P8LE-NEXT: lxvd2x vs1, 0, r4 2480; P8LE-NEXT: xxswapd v2, vs0 2481; P8LE-NEXT: xxswapd v3, vs1 2482; P8LE-NEXT: vperm v2, v2, v2, v3 2483; P8LE-NEXT: blr 2484entry: 2485 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2486 %0 = load i32, i32* %arrayidx, align 4 2487 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2488 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2489 %1 = load i32, i32* %arrayidx1, align 4 2490 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2491 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2492 %2 = load i32, i32* %arrayidx3, align 4 2493 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2494 %3 = load i32, i32* %arr, align 4 2495 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2496 ret <4 x i32> %vecinit6 2497} 2498 2499define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2500; P9BE-LABEL: fromDiffMemVarAui: 2501; P9BE: # %bb.0: # %entry 2502; P9BE-NEXT: sldi r4, r4, 2 2503; P9BE-NEXT: lxvx v2, r3, r4 2504; P9BE-NEXT: blr 2505; 2506; P9LE-LABEL: fromDiffMemVarAui: 2507; P9LE: # %bb.0: # %entry 2508; P9LE-NEXT: sldi r4, r4, 2 2509; P9LE-NEXT: lxvx v2, r3, r4 2510; P9LE-NEXT: blr 2511; 2512; P8BE-LABEL: fromDiffMemVarAui: 2513; P8BE: # %bb.0: # %entry 2514; P8BE-NEXT: sldi r4, r4, 2 2515; P8BE-NEXT: lxvw4x v2, r3, r4 2516; P8BE-NEXT: blr 2517; 2518; P8LE-LABEL: fromDiffMemVarAui: 2519; P8LE: # %bb.0: # %entry 2520; P8LE-NEXT: sldi r4, r4, 2 2521; P8LE-NEXT: lxvd2x vs0, r3, r4 2522; P8LE-NEXT: xxswapd v2, vs0 2523; P8LE-NEXT: blr 2524entry: 2525 %idxprom = sext i32 %elem to i64 2526 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2527 %0 = load i32, i32* %arrayidx, align 4 2528 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2529 %add = add nsw i32 %elem, 1 2530 %idxprom1 = sext i32 %add to i64 2531 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2532 %1 = load i32, i32* %arrayidx2, align 4 2533 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2534 %add4 = add nsw i32 %elem, 2 2535 %idxprom5 = sext i32 %add4 to i64 2536 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2537 %2 = load i32, i32* %arrayidx6, align 4 2538 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2539 %add8 = add nsw i32 %elem, 3 2540 %idxprom9 = sext i32 %add8 to i64 2541 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2542 %3 = load i32, i32* %arrayidx10, align 4 2543 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2544 ret <4 x i32> %vecinit11 2545} 2546 2547define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2548; P9BE-LABEL: fromDiffMemVarDui: 2549; P9BE: # %bb.0: # %entry 2550; P9BE-NEXT: sldi r4, r4, 2 2551; P9BE-NEXT: add r3, r3, r4 2552; P9BE-NEXT: li r4, -12 2553; P9BE-NEXT: lxvx v2, r3, r4 2554; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2555; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2556; P9BE-NEXT: lxv v3, 0(r3) 2557; P9BE-NEXT: vperm v2, v2, v2, v3 2558; P9BE-NEXT: blr 2559; 2560; P9LE-LABEL: fromDiffMemVarDui: 2561; P9LE: # %bb.0: # %entry 2562; P9LE-NEXT: sldi r4, r4, 2 2563; P9LE-NEXT: add r3, r3, r4 2564; P9LE-NEXT: li r4, -12 2565; P9LE-NEXT: lxvx v2, r3, r4 2566; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2567; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2568; P9LE-NEXT: lxv v3, 0(r3) 2569; P9LE-NEXT: vperm v2, v2, v2, v3 2570; P9LE-NEXT: blr 2571; 2572; P8BE-LABEL: fromDiffMemVarDui: 2573; P8BE: # %bb.0: # %entry 2574; P8BE-NEXT: sldi r4, r4, 2 2575; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2576; P8BE-NEXT: add r3, r3, r4 2577; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2578; P8BE-NEXT: addi r3, r3, -12 2579; P8BE-NEXT: lxvw4x v3, 0, r4 2580; P8BE-NEXT: lxvw4x v2, 0, r3 2581; P8BE-NEXT: vperm v2, v2, v2, v3 2582; P8BE-NEXT: blr 2583; 2584; P8LE-LABEL: fromDiffMemVarDui: 2585; P8LE: # %bb.0: # %entry 2586; P8LE-NEXT: sldi r4, r4, 2 2587; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2588; P8LE-NEXT: add r3, r3, r4 2589; P8LE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2590; P8LE-NEXT: addi r3, r3, -12 2591; P8LE-NEXT: lxvd2x vs1, 0, r4 2592; P8LE-NEXT: lxvd2x vs0, 0, r3 2593; P8LE-NEXT: xxswapd v3, vs1 2594; P8LE-NEXT: xxswapd v2, vs0 2595; P8LE-NEXT: vperm v2, v2, v2, v3 2596; P8LE-NEXT: blr 2597entry: 2598 %idxprom = sext i32 %elem to i64 2599 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2600 %0 = load i32, i32* %arrayidx, align 4 2601 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2602 %sub = add nsw i32 %elem, -1 2603 %idxprom1 = sext i32 %sub to i64 2604 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2605 %1 = load i32, i32* %arrayidx2, align 4 2606 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2607 %sub4 = add nsw i32 %elem, -2 2608 %idxprom5 = sext i32 %sub4 to i64 2609 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2610 %2 = load i32, i32* %arrayidx6, align 4 2611 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2612 %sub8 = add nsw i32 %elem, -3 2613 %idxprom9 = sext i32 %sub8 to i64 2614 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2615 %3 = load i32, i32* %arrayidx10, align 4 2616 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2617 ret <4 x i32> %vecinit11 2618} 2619 2620define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2621; P9BE-LABEL: fromRandMemConsui: 2622; P9BE: # %bb.0: # %entry 2623; P9BE-NEXT: lwz r4, 16(r3) 2624; P9BE-NEXT: lwz r5, 72(r3) 2625; P9BE-NEXT: lwz r6, 8(r3) 2626; P9BE-NEXT: lwz r3, 352(r3) 2627; P9BE-NEXT: rldimi r3, r6, 32, 0 2628; P9BE-NEXT: rldimi r5, r4, 32, 0 2629; P9BE-NEXT: mtvsrdd v2, r5, r3 2630; P9BE-NEXT: blr 2631; 2632; P9LE-LABEL: fromRandMemConsui: 2633; P9LE: # %bb.0: # %entry 2634; P9LE-NEXT: lwz r4, 16(r3) 2635; P9LE-NEXT: lwz r5, 72(r3) 2636; P9LE-NEXT: lwz r6, 8(r3) 2637; P9LE-NEXT: lwz r3, 352(r3) 2638; P9LE-NEXT: rldimi r4, r5, 32, 0 2639; P9LE-NEXT: rldimi r6, r3, 32, 0 2640; P9LE-NEXT: mtvsrdd v2, r6, r4 2641; P9LE-NEXT: blr 2642; 2643; P8BE-LABEL: fromRandMemConsui: 2644; P8BE: # %bb.0: # %entry 2645; P8BE-NEXT: lwz r4, 8(r3) 2646; P8BE-NEXT: lwz r5, 352(r3) 2647; P8BE-NEXT: lwz r6, 16(r3) 2648; P8BE-NEXT: lwz r3, 72(r3) 2649; P8BE-NEXT: rldimi r5, r4, 32, 0 2650; P8BE-NEXT: rldimi r3, r6, 32, 0 2651; P8BE-NEXT: mtfprd f0, r5 2652; P8BE-NEXT: mtfprd f1, r3 2653; P8BE-NEXT: xxmrghd v2, vs1, vs0 2654; P8BE-NEXT: blr 2655; 2656; P8LE-LABEL: fromRandMemConsui: 2657; P8LE: # %bb.0: # %entry 2658; P8LE-NEXT: lwz r4, 16(r3) 2659; P8LE-NEXT: lwz r5, 72(r3) 2660; P8LE-NEXT: lwz r6, 8(r3) 2661; P8LE-NEXT: lwz r3, 352(r3) 2662; P8LE-NEXT: rldimi r4, r5, 32, 0 2663; P8LE-NEXT: rldimi r6, r3, 32, 0 2664; P8LE-NEXT: mtfprd f0, r4 2665; P8LE-NEXT: mtfprd f1, r6 2666; P8LE-NEXT: xxmrghd v2, vs1, vs0 2667; P8LE-NEXT: blr 2668entry: 2669 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2670 %0 = load i32, i32* %arrayidx, align 4 2671 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2672 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2673 %1 = load i32, i32* %arrayidx1, align 4 2674 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2675 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2676 %2 = load i32, i32* %arrayidx3, align 4 2677 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2678 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2679 %3 = load i32, i32* %arrayidx5, align 4 2680 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2681 ret <4 x i32> %vecinit6 2682} 2683 2684define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2685; P9BE-LABEL: fromRandMemVarui: 2686; P9BE: # %bb.0: # %entry 2687; P9BE-NEXT: sldi r4, r4, 2 2688; P9BE-NEXT: add r3, r3, r4 2689; P9BE-NEXT: lwz r4, 16(r3) 2690; P9BE-NEXT: lwz r5, 4(r3) 2691; P9BE-NEXT: lwz r6, 8(r3) 2692; P9BE-NEXT: lwz r3, 32(r3) 2693; P9BE-NEXT: rldimi r3, r6, 32, 0 2694; P9BE-NEXT: rldimi r5, r4, 32, 0 2695; P9BE-NEXT: mtvsrdd v2, r5, r3 2696; P9BE-NEXT: blr 2697; 2698; P9LE-LABEL: fromRandMemVarui: 2699; P9LE: # %bb.0: # %entry 2700; P9LE-NEXT: sldi r4, r4, 2 2701; P9LE-NEXT: add r3, r3, r4 2702; P9LE-NEXT: lwz r4, 16(r3) 2703; P9LE-NEXT: lwz r5, 4(r3) 2704; P9LE-NEXT: lwz r6, 8(r3) 2705; P9LE-NEXT: lwz r3, 32(r3) 2706; P9LE-NEXT: rldimi r4, r5, 32, 0 2707; P9LE-NEXT: rldimi r6, r3, 32, 0 2708; P9LE-NEXT: mtvsrdd v2, r6, r4 2709; P9LE-NEXT: blr 2710; 2711; P8BE-LABEL: fromRandMemVarui: 2712; P8BE: # %bb.0: # %entry 2713; P8BE-NEXT: sldi r4, r4, 2 2714; P8BE-NEXT: add r3, r3, r4 2715; P8BE-NEXT: lwz r4, 8(r3) 2716; P8BE-NEXT: lwz r5, 32(r3) 2717; P8BE-NEXT: lwz r6, 16(r3) 2718; P8BE-NEXT: lwz r3, 4(r3) 2719; P8BE-NEXT: rldimi r5, r4, 32, 0 2720; P8BE-NEXT: rldimi r3, r6, 32, 0 2721; P8BE-NEXT: mtfprd f0, r5 2722; P8BE-NEXT: mtfprd f1, r3 2723; P8BE-NEXT: xxmrghd v2, vs1, vs0 2724; P8BE-NEXT: blr 2725; 2726; P8LE-LABEL: fromRandMemVarui: 2727; P8LE: # %bb.0: # %entry 2728; P8LE-NEXT: sldi r4, r4, 2 2729; P8LE-NEXT: add r3, r3, r4 2730; P8LE-NEXT: lwz r4, 16(r3) 2731; P8LE-NEXT: lwz r5, 4(r3) 2732; P8LE-NEXT: lwz r6, 8(r3) 2733; P8LE-NEXT: lwz r3, 32(r3) 2734; P8LE-NEXT: rldimi r4, r5, 32, 0 2735; P8LE-NEXT: rldimi r6, r3, 32, 0 2736; P8LE-NEXT: mtfprd f0, r4 2737; P8LE-NEXT: mtfprd f1, r6 2738; P8LE-NEXT: xxmrghd v2, vs1, vs0 2739; P8LE-NEXT: blr 2740entry: 2741 %add = add nsw i32 %elem, 4 2742 %idxprom = sext i32 %add to i64 2743 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2744 %0 = load i32, i32* %arrayidx, align 4 2745 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2746 %add1 = add nsw i32 %elem, 1 2747 %idxprom2 = sext i32 %add1 to i64 2748 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2749 %1 = load i32, i32* %arrayidx3, align 4 2750 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2751 %add5 = add nsw i32 %elem, 2 2752 %idxprom6 = sext i32 %add5 to i64 2753 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2754 %2 = load i32, i32* %arrayidx7, align 4 2755 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2756 %add9 = add nsw i32 %elem, 8 2757 %idxprom10 = sext i32 %add9 to i64 2758 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2759 %3 = load i32, i32* %arrayidx11, align 4 2760 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2761 ret <4 x i32> %vecinit12 2762} 2763 2764define <4 x i32> @spltRegValui(i32 zeroext %val) { 2765; P9BE-LABEL: spltRegValui: 2766; P9BE: # %bb.0: # %entry 2767; P9BE-NEXT: mtvsrws v2, r3 2768; P9BE-NEXT: blr 2769; 2770; P9LE-LABEL: spltRegValui: 2771; P9LE: # %bb.0: # %entry 2772; P9LE-NEXT: mtvsrws v2, r3 2773; P9LE-NEXT: blr 2774; 2775; P8BE-LABEL: spltRegValui: 2776; P8BE: # %bb.0: # %entry 2777; P8BE-NEXT: mtfprwz f0, r3 2778; P8BE-NEXT: xxspltw v2, vs0, 1 2779; P8BE-NEXT: blr 2780; 2781; P8LE-LABEL: spltRegValui: 2782; P8LE: # %bb.0: # %entry 2783; P8LE-NEXT: mtfprwz f0, r3 2784; P8LE-NEXT: xxspltw v2, vs0, 1 2785; P8LE-NEXT: blr 2786entry: 2787 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2788 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2789 ret <4 x i32> %splat.splat 2790} 2791 2792define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2793; P9BE-LABEL: spltMemValui: 2794; P9BE: # %bb.0: # %entry 2795; P9BE-NEXT: lxvwsx v2, 0, r3 2796; P9BE-NEXT: blr 2797; 2798; P9LE-LABEL: spltMemValui: 2799; P9LE: # %bb.0: # %entry 2800; P9LE-NEXT: lxvwsx v2, 0, r3 2801; P9LE-NEXT: blr 2802; 2803; P8BE-LABEL: spltMemValui: 2804; P8BE: # %bb.0: # %entry 2805; P8BE-NEXT: lfiwzx f0, 0, r3 2806; P8BE-NEXT: xxspltw v2, vs0, 1 2807; P8BE-NEXT: blr 2808; 2809; P8LE-LABEL: spltMemValui: 2810; P8LE: # %bb.0: # %entry 2811; P8LE-NEXT: lfiwzx f0, 0, r3 2812; P8LE-NEXT: xxspltw v2, vs0, 1 2813; P8LE-NEXT: blr 2814entry: 2815 %0 = load i32, i32* %ptr, align 4 2816 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2817 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2818 ret <4 x i32> %splat.splat 2819} 2820 2821define <4 x i32> @spltCnstConvftoui() { 2822; P9BE-LABEL: spltCnstConvftoui: 2823; P9BE: # %bb.0: # %entry 2824; P9BE-NEXT: vspltisw v2, 4 2825; P9BE-NEXT: blr 2826; 2827; P9LE-LABEL: spltCnstConvftoui: 2828; P9LE: # %bb.0: # %entry 2829; P9LE-NEXT: vspltisw v2, 4 2830; P9LE-NEXT: blr 2831; 2832; P8BE-LABEL: spltCnstConvftoui: 2833; P8BE: # %bb.0: # %entry 2834; P8BE-NEXT: vspltisw v2, 4 2835; P8BE-NEXT: blr 2836; 2837; P8LE-LABEL: spltCnstConvftoui: 2838; P8LE: # %bb.0: # %entry 2839; P8LE-NEXT: vspltisw v2, 4 2840; P8LE-NEXT: blr 2841entry: 2842 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2843} 2844 2845define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2846; P9BE-LABEL: fromRegsConvftoui: 2847; P9BE: # %bb.0: # %entry 2848; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2849; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2850; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2851; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2852; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2853; P9BE-NEXT: xvcvdpuxws v2, vs0 2854; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2855; P9BE-NEXT: xvcvdpuxws v3, vs0 2856; P9BE-NEXT: vmrgew v2, v3, v2 2857; P9BE-NEXT: blr 2858; 2859; P9LE-LABEL: fromRegsConvftoui: 2860; P9LE: # %bb.0: # %entry 2861; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2862; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2863; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2864; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2865; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2866; P9LE-NEXT: xvcvdpuxws v2, vs0 2867; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2868; P9LE-NEXT: xvcvdpuxws v3, vs0 2869; P9LE-NEXT: vmrgew v2, v3, v2 2870; P9LE-NEXT: blr 2871; 2872; P8BE-LABEL: fromRegsConvftoui: 2873; P8BE: # %bb.0: # %entry 2874; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2875; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2876; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2877; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2878; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2879; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2880; P8BE-NEXT: xvcvdpuxws v2, vs0 2881; P8BE-NEXT: xvcvdpuxws v3, vs1 2882; P8BE-NEXT: vmrgew v2, v3, v2 2883; P8BE-NEXT: blr 2884; 2885; P8LE-LABEL: fromRegsConvftoui: 2886; P8LE: # %bb.0: # %entry 2887; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2888; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2889; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2890; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2891; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2892; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2893; P8LE-NEXT: xvcvdpuxws v2, vs0 2894; P8LE-NEXT: xvcvdpuxws v3, vs1 2895; P8LE-NEXT: vmrgew v2, v3, v2 2896; P8LE-NEXT: blr 2897entry: 2898 %conv = fptoui float %a to i32 2899 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2900 %conv1 = fptoui float %b to i32 2901 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2902 %conv3 = fptoui float %c to i32 2903 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2904 %conv5 = fptoui float %d to i32 2905 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2906 ret <4 x i32> %vecinit6 2907} 2908 2909define <4 x i32> @fromDiffConstsConvftoui() { 2910; P9BE-LABEL: fromDiffConstsConvftoui: 2911; P9BE: # %bb.0: # %entry 2912; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2913; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2914; P9BE-NEXT: lxv v2, 0(r3) 2915; P9BE-NEXT: blr 2916; 2917; P9LE-LABEL: fromDiffConstsConvftoui: 2918; P9LE: # %bb.0: # %entry 2919; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2920; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2921; P9LE-NEXT: lxv v2, 0(r3) 2922; P9LE-NEXT: blr 2923; 2924; P8BE-LABEL: fromDiffConstsConvftoui: 2925; P8BE: # %bb.0: # %entry 2926; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2927; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2928; P8BE-NEXT: lxvw4x v2, 0, r3 2929; P8BE-NEXT: blr 2930; 2931; P8LE-LABEL: fromDiffConstsConvftoui: 2932; P8LE: # %bb.0: # %entry 2933; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2934; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2935; P8LE-NEXT: lxvd2x vs0, 0, r3 2936; P8LE-NEXT: xxswapd v2, vs0 2937; P8LE-NEXT: blr 2938entry: 2939 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2940} 2941 2942define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2943; P9BE-LABEL: fromDiffMemConsAConvftoui: 2944; P9BE: # %bb.0: # %entry 2945; P9BE-NEXT: lxv vs0, 0(r3) 2946; P9BE-NEXT: xvcvspuxws v2, vs0 2947; P9BE-NEXT: blr 2948; 2949; P9LE-LABEL: fromDiffMemConsAConvftoui: 2950; P9LE: # %bb.0: # %entry 2951; P9LE-NEXT: lxv vs0, 0(r3) 2952; P9LE-NEXT: xvcvspuxws v2, vs0 2953; P9LE-NEXT: blr 2954; 2955; P8BE-LABEL: fromDiffMemConsAConvftoui: 2956; P8BE: # %bb.0: # %entry 2957; P8BE-NEXT: lxvw4x vs0, 0, r3 2958; P8BE-NEXT: xvcvspuxws v2, vs0 2959; P8BE-NEXT: blr 2960; 2961; P8LE-LABEL: fromDiffMemConsAConvftoui: 2962; P8LE: # %bb.0: # %entry 2963; P8LE-NEXT: lxvd2x vs0, 0, r3 2964; P8LE-NEXT: xxswapd v2, vs0 2965; P8LE-NEXT: xvcvspuxws v2, v2 2966; P8LE-NEXT: blr 2967entry: 2968 %0 = bitcast float* %ptr to <4 x float>* 2969 %1 = load <4 x float>, <4 x float>* %0, align 4 2970 %2 = fptoui <4 x float> %1 to <4 x i32> 2971 ret <4 x i32> %2 2972} 2973 2974define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2975; P9BE-LABEL: fromDiffMemConsDConvftoui: 2976; P9BE: # %bb.0: # %entry 2977; P9BE-NEXT: lxv v2, 0(r3) 2978; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2979; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2980; P9BE-NEXT: lxv v3, 0(r3) 2981; P9BE-NEXT: vperm v2, v2, v2, v3 2982; P9BE-NEXT: xvcvspuxws v2, v2 2983; P9BE-NEXT: blr 2984; 2985; P9LE-LABEL: fromDiffMemConsDConvftoui: 2986; P9LE: # %bb.0: # %entry 2987; P9LE-NEXT: lxv v2, 0(r3) 2988; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2989; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2990; P9LE-NEXT: lxv v3, 0(r3) 2991; P9LE-NEXT: vperm v2, v2, v2, v3 2992; P9LE-NEXT: xvcvspuxws v2, v2 2993; P9LE-NEXT: blr 2994; 2995; P8BE-LABEL: fromDiffMemConsDConvftoui: 2996; P8BE: # %bb.0: # %entry 2997; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2998; P8BE-NEXT: lxvw4x v2, 0, r3 2999; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l 3000; P8BE-NEXT: lxvw4x v3, 0, r4 3001; P8BE-NEXT: vperm v2, v2, v2, v3 3002; P8BE-NEXT: xvcvspuxws v2, v2 3003; P8BE-NEXT: blr 3004; 3005; P8LE-LABEL: fromDiffMemConsDConvftoui: 3006; P8LE: # %bb.0: # %entry 3007; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 3008; P8LE-NEXT: lxvd2x vs0, 0, r3 3009; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l 3010; P8LE-NEXT: lxvd2x vs1, 0, r4 3011; P8LE-NEXT: xxswapd v2, vs0 3012; P8LE-NEXT: xxswapd v3, vs1 3013; P8LE-NEXT: vperm v2, v2, v2, v3 3014; P8LE-NEXT: xvcvspuxws v2, v2 3015; P8LE-NEXT: blr 3016entry: 3017 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3018 %0 = load float, float* %arrayidx, align 4 3019 %conv = fptoui float %0 to i32 3020 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3021 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3022 %1 = load float, float* %arrayidx1, align 4 3023 %conv2 = fptoui float %1 to i32 3024 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3025 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3026 %2 = load float, float* %arrayidx4, align 4 3027 %conv5 = fptoui float %2 to i32 3028 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3029 %3 = load float, float* %ptr, align 4 3030 %conv8 = fptoui float %3 to i32 3031 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3032 ret <4 x i32> %vecinit9 3033} 3034 3035define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3036; P9BE-LABEL: fromDiffMemVarAConvftoui: 3037; P9BE: # %bb.0: # %entry 3038; P9BE-NEXT: sldi r4, r4, 2 3039; P9BE-NEXT: lfsux f0, r3, r4 3040; P9BE-NEXT: lfs f1, 12(r3) 3041; P9BE-NEXT: lfs f2, 4(r3) 3042; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3043; P9BE-NEXT: xvcvdpsp v2, vs1 3044; P9BE-NEXT: lfs f1, 8(r3) 3045; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3046; P9BE-NEXT: xvcvdpsp v3, vs0 3047; P9BE-NEXT: vmrgew v2, v3, v2 3048; P9BE-NEXT: xvcvspuxws v2, v2 3049; P9BE-NEXT: blr 3050; 3051; P9LE-LABEL: fromDiffMemVarAConvftoui: 3052; P9LE: # %bb.0: # %entry 3053; P9LE-NEXT: sldi r4, r4, 2 3054; P9LE-NEXT: lfsux f0, r3, r4 3055; P9LE-NEXT: lfs f1, 8(r3) 3056; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3057; P9LE-NEXT: lfs f1, 12(r3) 3058; P9LE-NEXT: xvcvdpsp v2, vs0 3059; P9LE-NEXT: lfs f0, 4(r3) 3060; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3061; P9LE-NEXT: xvcvdpsp v3, vs0 3062; P9LE-NEXT: vmrgew v2, v3, v2 3063; P9LE-NEXT: xvcvspuxws v2, v2 3064; P9LE-NEXT: blr 3065; 3066; P8BE-LABEL: fromDiffMemVarAConvftoui: 3067; P8BE: # %bb.0: # %entry 3068; P8BE-NEXT: sldi r4, r4, 2 3069; P8BE-NEXT: lfsux f0, r3, r4 3070; P8BE-NEXT: lfs f1, 12(r3) 3071; P8BE-NEXT: lfs f2, 4(r3) 3072; P8BE-NEXT: lfs f3, 8(r3) 3073; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3074; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3075; P8BE-NEXT: xvcvdpsp v2, vs1 3076; P8BE-NEXT: xvcvdpsp v3, vs0 3077; P8BE-NEXT: vmrgew v2, v3, v2 3078; P8BE-NEXT: xvcvspuxws v2, v2 3079; P8BE-NEXT: blr 3080; 3081; P8LE-LABEL: fromDiffMemVarAConvftoui: 3082; P8LE: # %bb.0: # %entry 3083; P8LE-NEXT: sldi r4, r4, 2 3084; P8LE-NEXT: lfsux f0, r3, r4 3085; P8LE-NEXT: lfs f1, 8(r3) 3086; P8LE-NEXT: lfs f2, 4(r3) 3087; P8LE-NEXT: lfs f3, 12(r3) 3088; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3089; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3090; P8LE-NEXT: xvcvdpsp v2, vs0 3091; P8LE-NEXT: xvcvdpsp v3, vs1 3092; P8LE-NEXT: vmrgew v2, v3, v2 3093; P8LE-NEXT: xvcvspuxws v2, v2 3094; P8LE-NEXT: blr 3095entry: 3096 %idxprom = sext i32 %elem to i64 3097 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3098 %0 = load float, float* %arrayidx, align 4 3099 %conv = fptoui float %0 to i32 3100 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3101 %add = add nsw i32 %elem, 1 3102 %idxprom1 = sext i32 %add to i64 3103 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3104 %1 = load float, float* %arrayidx2, align 4 3105 %conv3 = fptoui float %1 to i32 3106 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3107 %add5 = add nsw i32 %elem, 2 3108 %idxprom6 = sext i32 %add5 to i64 3109 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3110 %2 = load float, float* %arrayidx7, align 4 3111 %conv8 = fptoui float %2 to i32 3112 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3113 %add10 = add nsw i32 %elem, 3 3114 %idxprom11 = sext i32 %add10 to i64 3115 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3116 %3 = load float, float* %arrayidx12, align 4 3117 %conv13 = fptoui float %3 to i32 3118 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3119 ret <4 x i32> %vecinit14 3120; FIXME: implement finding consecutive loads with pre-inc 3121} 3122 3123define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3124; P9BE-LABEL: fromDiffMemVarDConvftoui: 3125; P9BE: # %bb.0: # %entry 3126; P9BE-NEXT: sldi r4, r4, 2 3127; P9BE-NEXT: lfsux f0, r3, r4 3128; P9BE-NEXT: lfs f1, -12(r3) 3129; P9BE-NEXT: lfs f2, -4(r3) 3130; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3131; P9BE-NEXT: xvcvdpsp v2, vs1 3132; P9BE-NEXT: lfs f1, -8(r3) 3133; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3134; P9BE-NEXT: xvcvdpsp v3, vs0 3135; P9BE-NEXT: vmrgew v2, v3, v2 3136; P9BE-NEXT: xvcvspuxws v2, v2 3137; P9BE-NEXT: blr 3138; 3139; P9LE-LABEL: fromDiffMemVarDConvftoui: 3140; P9LE: # %bb.0: # %entry 3141; P9LE-NEXT: sldi r4, r4, 2 3142; P9LE-NEXT: lfsux f0, r3, r4 3143; P9LE-NEXT: lfs f1, -8(r3) 3144; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3145; P9LE-NEXT: lfs f1, -12(r3) 3146; P9LE-NEXT: xvcvdpsp v2, vs0 3147; P9LE-NEXT: lfs f0, -4(r3) 3148; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3149; P9LE-NEXT: xvcvdpsp v3, vs0 3150; P9LE-NEXT: vmrgew v2, v3, v2 3151; P9LE-NEXT: xvcvspuxws v2, v2 3152; P9LE-NEXT: blr 3153; 3154; P8BE-LABEL: fromDiffMemVarDConvftoui: 3155; P8BE: # %bb.0: # %entry 3156; P8BE-NEXT: sldi r4, r4, 2 3157; P8BE-NEXT: lfsux f0, r3, r4 3158; P8BE-NEXT: lfs f1, -12(r3) 3159; P8BE-NEXT: lfs f2, -4(r3) 3160; P8BE-NEXT: lfs f3, -8(r3) 3161; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3162; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3163; P8BE-NEXT: xvcvdpsp v2, vs1 3164; P8BE-NEXT: xvcvdpsp v3, vs0 3165; P8BE-NEXT: vmrgew v2, v3, v2 3166; P8BE-NEXT: xvcvspuxws v2, v2 3167; P8BE-NEXT: blr 3168; 3169; P8LE-LABEL: fromDiffMemVarDConvftoui: 3170; P8LE: # %bb.0: # %entry 3171; P8LE-NEXT: sldi r4, r4, 2 3172; P8LE-NEXT: lfsux f0, r3, r4 3173; P8LE-NEXT: lfs f1, -8(r3) 3174; P8LE-NEXT: lfs f2, -4(r3) 3175; P8LE-NEXT: lfs f3, -12(r3) 3176; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3177; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3178; P8LE-NEXT: xvcvdpsp v2, vs0 3179; P8LE-NEXT: xvcvdpsp v3, vs1 3180; P8LE-NEXT: vmrgew v2, v3, v2 3181; P8LE-NEXT: xvcvspuxws v2, v2 3182; P8LE-NEXT: blr 3183entry: 3184 %idxprom = sext i32 %elem to i64 3185 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3186 %0 = load float, float* %arrayidx, align 4 3187 %conv = fptoui float %0 to i32 3188 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3189 %sub = add nsw i32 %elem, -1 3190 %idxprom1 = sext i32 %sub to i64 3191 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3192 %1 = load float, float* %arrayidx2, align 4 3193 %conv3 = fptoui float %1 to i32 3194 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3195 %sub5 = add nsw i32 %elem, -2 3196 %idxprom6 = sext i32 %sub5 to i64 3197 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3198 %2 = load float, float* %arrayidx7, align 4 3199 %conv8 = fptoui float %2 to i32 3200 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3201 %sub10 = add nsw i32 %elem, -3 3202 %idxprom11 = sext i32 %sub10 to i64 3203 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3204 %3 = load float, float* %arrayidx12, align 4 3205 %conv13 = fptoui float %3 to i32 3206 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3207 ret <4 x i32> %vecinit14 3208; FIXME: implement finding consecutive loads with pre-inc 3209} 3210 3211define <4 x i32> @spltRegValConvftoui(float %val) { 3212; P9BE-LABEL: spltRegValConvftoui: 3213; P9BE: # %bb.0: # %entry 3214; P9BE-NEXT: xscvdpuxws f0, f1 3215; P9BE-NEXT: xxspltw v2, vs0, 1 3216; P9BE-NEXT: blr 3217; 3218; P9LE-LABEL: spltRegValConvftoui: 3219; P9LE: # %bb.0: # %entry 3220; P9LE-NEXT: xscvdpuxws f0, f1 3221; P9LE-NEXT: xxspltw v2, vs0, 1 3222; P9LE-NEXT: blr 3223; 3224; P8BE-LABEL: spltRegValConvftoui: 3225; P8BE: # %bb.0: # %entry 3226; P8BE-NEXT: xscvdpuxws f0, f1 3227; P8BE-NEXT: xxspltw v2, vs0, 1 3228; P8BE-NEXT: blr 3229; 3230; P8LE-LABEL: spltRegValConvftoui: 3231; P8LE: # %bb.0: # %entry 3232; P8LE-NEXT: xscvdpuxws f0, f1 3233; P8LE-NEXT: xxspltw v2, vs0, 1 3234; P8LE-NEXT: blr 3235entry: 3236 %conv = fptoui float %val to i32 3237 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3238 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3239 ret <4 x i32> %splat.splat 3240} 3241 3242define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3243; P9BE-LABEL: spltMemValConvftoui: 3244; P9BE: # %bb.0: # %entry 3245; P9BE-NEXT: lfiwzx f0, 0, r3 3246; P9BE-NEXT: xvcvspuxws vs0, vs0 3247; P9BE-NEXT: xxspltw v2, vs0, 1 3248; P9BE-NEXT: blr 3249; 3250; P9LE-LABEL: spltMemValConvftoui: 3251; P9LE: # %bb.0: # %entry 3252; P9LE-NEXT: lfiwzx f0, 0, r3 3253; P9LE-NEXT: xvcvspuxws vs0, vs0 3254; P9LE-NEXT: xxspltw v2, vs0, 1 3255; P9LE-NEXT: blr 3256; 3257; P8BE-LABEL: spltMemValConvftoui: 3258; P8BE: # %bb.0: # %entry 3259; P8BE-NEXT: lfsx f0, 0, r3 3260; P8BE-NEXT: xscvdpuxws f0, f0 3261; P8BE-NEXT: xxspltw v2, vs0, 1 3262; P8BE-NEXT: blr 3263; 3264; P8LE-LABEL: spltMemValConvftoui: 3265; P8LE: # %bb.0: # %entry 3266; P8LE-NEXT: lfsx f0, 0, r3 3267; P8LE-NEXT: xscvdpuxws f0, f0 3268; P8LE-NEXT: xxspltw v2, vs0, 1 3269; P8LE-NEXT: blr 3270entry: 3271 %0 = load float, float* %ptr, align 4 3272 %conv = fptoui float %0 to i32 3273 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3274 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3275 ret <4 x i32> %splat.splat 3276} 3277 3278define <4 x i32> @spltCnstConvdtoui() { 3279; P9BE-LABEL: spltCnstConvdtoui: 3280; P9BE: # %bb.0: # %entry 3281; P9BE-NEXT: vspltisw v2, 4 3282; P9BE-NEXT: blr 3283; 3284; P9LE-LABEL: spltCnstConvdtoui: 3285; P9LE: # %bb.0: # %entry 3286; P9LE-NEXT: vspltisw v2, 4 3287; P9LE-NEXT: blr 3288; 3289; P8BE-LABEL: spltCnstConvdtoui: 3290; P8BE: # %bb.0: # %entry 3291; P8BE-NEXT: vspltisw v2, 4 3292; P8BE-NEXT: blr 3293; 3294; P8LE-LABEL: spltCnstConvdtoui: 3295; P8LE: # %bb.0: # %entry 3296; P8LE-NEXT: vspltisw v2, 4 3297; P8LE-NEXT: blr 3298entry: 3299 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3300} 3301 3302define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3303; P9BE-LABEL: fromRegsConvdtoui: 3304; P9BE: # %bb.0: # %entry 3305; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3306; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3307; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3308; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3309; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3310; P9BE-NEXT: xvcvdpuxws v2, vs0 3311; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3312; P9BE-NEXT: xvcvdpuxws v3, vs0 3313; P9BE-NEXT: vmrgew v2, v3, v2 3314; P9BE-NEXT: blr 3315; 3316; P9LE-LABEL: fromRegsConvdtoui: 3317; P9LE: # %bb.0: # %entry 3318; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3319; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3320; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3321; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3322; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3323; P9LE-NEXT: xvcvdpuxws v2, vs0 3324; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3325; P9LE-NEXT: xvcvdpuxws v3, vs0 3326; P9LE-NEXT: vmrgew v2, v3, v2 3327; P9LE-NEXT: blr 3328; 3329; P8BE-LABEL: fromRegsConvdtoui: 3330; P8BE: # %bb.0: # %entry 3331; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3332; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3333; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3334; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3335; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3336; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3337; P8BE-NEXT: xvcvdpuxws v2, vs0 3338; P8BE-NEXT: xvcvdpuxws v3, vs1 3339; P8BE-NEXT: vmrgew v2, v3, v2 3340; P8BE-NEXT: blr 3341; 3342; P8LE-LABEL: fromRegsConvdtoui: 3343; P8LE: # %bb.0: # %entry 3344; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3345; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3346; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3347; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3348; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3349; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3350; P8LE-NEXT: xvcvdpuxws v2, vs0 3351; P8LE-NEXT: xvcvdpuxws v3, vs1 3352; P8LE-NEXT: vmrgew v2, v3, v2 3353; P8LE-NEXT: blr 3354entry: 3355 %conv = fptoui double %a to i32 3356 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3357 %conv1 = fptoui double %b to i32 3358 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3359 %conv3 = fptoui double %c to i32 3360 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3361 %conv5 = fptoui double %d to i32 3362 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3363 ret <4 x i32> %vecinit6 3364} 3365 3366define <4 x i32> @fromDiffConstsConvdtoui() { 3367; P9BE-LABEL: fromDiffConstsConvdtoui: 3368; P9BE: # %bb.0: # %entry 3369; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3370; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3371; P9BE-NEXT: lxv v2, 0(r3) 3372; P9BE-NEXT: blr 3373; 3374; P9LE-LABEL: fromDiffConstsConvdtoui: 3375; P9LE: # %bb.0: # %entry 3376; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3377; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3378; P9LE-NEXT: lxv v2, 0(r3) 3379; P9LE-NEXT: blr 3380; 3381; P8BE-LABEL: fromDiffConstsConvdtoui: 3382; P8BE: # %bb.0: # %entry 3383; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3384; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3385; P8BE-NEXT: lxvw4x v2, 0, r3 3386; P8BE-NEXT: blr 3387; 3388; P8LE-LABEL: fromDiffConstsConvdtoui: 3389; P8LE: # %bb.0: # %entry 3390; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3391; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3392; P8LE-NEXT: lxvd2x vs0, 0, r3 3393; P8LE-NEXT: xxswapd v2, vs0 3394; P8LE-NEXT: blr 3395entry: 3396 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3397} 3398 3399define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3400; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3401; P9BE: # %bb.0: # %entry 3402; P9BE-NEXT: lxv vs0, 0(r3) 3403; P9BE-NEXT: lxv vs1, 16(r3) 3404; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3405; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3406; P9BE-NEXT: xvcvdpuxws v2, vs2 3407; P9BE-NEXT: xvcvdpuxws v3, vs0 3408; P9BE-NEXT: vmrgew v2, v3, v2 3409; P9BE-NEXT: blr 3410; 3411; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3412; P9LE: # %bb.0: # %entry 3413; P9LE-NEXT: lxv vs0, 0(r3) 3414; P9LE-NEXT: lxv vs1, 16(r3) 3415; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3416; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3417; P9LE-NEXT: xvcvdpuxws v2, vs2 3418; P9LE-NEXT: xvcvdpuxws v3, vs0 3419; P9LE-NEXT: vmrgew v2, v3, v2 3420; P9LE-NEXT: blr 3421; 3422; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3423; P8BE: # %bb.0: # %entry 3424; P8BE-NEXT: li r4, 16 3425; P8BE-NEXT: lxvd2x vs0, 0, r3 3426; P8BE-NEXT: lxvd2x vs1, r3, r4 3427; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3428; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3429; P8BE-NEXT: xvcvdpuxws v2, vs2 3430; P8BE-NEXT: xvcvdpuxws v3, vs0 3431; P8BE-NEXT: vmrgew v2, v3, v2 3432; P8BE-NEXT: blr 3433; 3434; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3435; P8LE: # %bb.0: # %entry 3436; P8LE-NEXT: li r4, 16 3437; P8LE-NEXT: lxvd2x vs0, 0, r3 3438; P8LE-NEXT: lxvd2x vs1, r3, r4 3439; P8LE-NEXT: xxswapd vs0, vs0 3440; P8LE-NEXT: xxswapd vs1, vs1 3441; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3442; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3443; P8LE-NEXT: xvcvdpuxws v2, vs2 3444; P8LE-NEXT: xvcvdpuxws v3, vs0 3445; P8LE-NEXT: vmrgew v2, v3, v2 3446; P8LE-NEXT: blr 3447entry: 3448 %0 = bitcast double* %ptr to <2 x double>* 3449 %1 = load <2 x double>, <2 x double>* %0, align 8 3450 %2 = fptoui <2 x double> %1 to <2 x i32> 3451 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3452 %3 = bitcast double* %arrayidx4 to <2 x double>* 3453 %4 = load <2 x double>, <2 x double>* %3, align 8 3454 %5 = fptoui <2 x double> %4 to <2 x i32> 3455 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3456 ret <4 x i32> %vecinit9 3457} 3458 3459define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3460; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3461; P9BE: # %bb.0: # %entry 3462; P9BE-NEXT: lfd f0, 24(r3) 3463; P9BE-NEXT: lfd f1, 16(r3) 3464; P9BE-NEXT: lfd f2, 8(r3) 3465; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3466; P9BE-NEXT: lfd f3, 0(r3) 3467; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3468; P9BE-NEXT: xvcvdpuxws v2, vs1 3469; P9BE-NEXT: xvcvdpuxws v3, vs0 3470; P9BE-NEXT: vmrgew v2, v3, v2 3471; P9BE-NEXT: blr 3472; 3473; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3474; P9LE: # %bb.0: # %entry 3475; P9LE-NEXT: lfd f0, 24(r3) 3476; P9LE-NEXT: lfd f2, 8(r3) 3477; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3478; P9LE-NEXT: lfd f1, 16(r3) 3479; P9LE-NEXT: lfd f3, 0(r3) 3480; P9LE-NEXT: xvcvdpuxws v2, vs0 3481; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3482; P9LE-NEXT: xvcvdpuxws v3, vs0 3483; P9LE-NEXT: vmrgew v2, v3, v2 3484; P9LE-NEXT: blr 3485; 3486; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3487; P8BE: # %bb.0: # %entry 3488; P8BE-NEXT: lfd f0, 16(r3) 3489; P8BE-NEXT: lfd f1, 0(r3) 3490; P8BE-NEXT: lfd f2, 24(r3) 3491; P8BE-NEXT: lfd f3, 8(r3) 3492; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3493; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3494; P8BE-NEXT: xvcvdpuxws v2, vs0 3495; P8BE-NEXT: xvcvdpuxws v3, vs1 3496; P8BE-NEXT: vmrgew v2, v3, v2 3497; P8BE-NEXT: blr 3498; 3499; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3500; P8LE: # %bb.0: # %entry 3501; P8LE-NEXT: lfd f0, 24(r3) 3502; P8LE-NEXT: lfd f1, 8(r3) 3503; P8LE-NEXT: lfd f2, 16(r3) 3504; P8LE-NEXT: lfd f3, 0(r3) 3505; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3506; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3507; P8LE-NEXT: xvcvdpuxws v2, vs0 3508; P8LE-NEXT: xvcvdpuxws v3, vs1 3509; P8LE-NEXT: vmrgew v2, v3, v2 3510; P8LE-NEXT: blr 3511entry: 3512 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3513 %0 = load double, double* %arrayidx, align 8 3514 %conv = fptoui double %0 to i32 3515 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3516 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3517 %1 = load double, double* %arrayidx1, align 8 3518 %conv2 = fptoui double %1 to i32 3519 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3520 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3521 %2 = load double, double* %arrayidx4, align 8 3522 %conv5 = fptoui double %2 to i32 3523 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3524 %3 = load double, double* %ptr, align 8 3525 %conv8 = fptoui double %3 to i32 3526 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3527 ret <4 x i32> %vecinit9 3528} 3529 3530define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3531; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3532; P9BE: # %bb.0: # %entry 3533; P9BE-NEXT: sldi r4, r4, 3 3534; P9BE-NEXT: lfdux f0, r3, r4 3535; P9BE-NEXT: lfd f1, 8(r3) 3536; P9BE-NEXT: lfd f2, 16(r3) 3537; P9BE-NEXT: lfd f3, 24(r3) 3538; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3539; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3540; P9BE-NEXT: xvcvdpuxws v2, vs1 3541; P9BE-NEXT: xvcvdpuxws v3, vs0 3542; P9BE-NEXT: vmrgew v2, v3, v2 3543; P9BE-NEXT: blr 3544; 3545; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3546; P9LE: # %bb.0: # %entry 3547; P9LE-NEXT: sldi r4, r4, 3 3548; P9LE-NEXT: lfdux f0, r3, r4 3549; P9LE-NEXT: lfd f2, 16(r3) 3550; P9LE-NEXT: lfd f1, 8(r3) 3551; P9LE-NEXT: lfd f3, 24(r3) 3552; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3553; P9LE-NEXT: xvcvdpuxws v2, vs0 3554; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3555; P9LE-NEXT: xvcvdpuxws v3, vs0 3556; P9LE-NEXT: vmrgew v2, v3, v2 3557; P9LE-NEXT: blr 3558; 3559; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3560; P8BE: # %bb.0: # %entry 3561; P8BE-NEXT: sldi r4, r4, 3 3562; P8BE-NEXT: lfdux f0, r3, r4 3563; P8BE-NEXT: lfd f1, 8(r3) 3564; P8BE-NEXT: lfd f2, 24(r3) 3565; P8BE-NEXT: lfd f3, 16(r3) 3566; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3567; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3568; P8BE-NEXT: xvcvdpuxws v2, vs1 3569; P8BE-NEXT: xvcvdpuxws v3, vs0 3570; P8BE-NEXT: vmrgew v2, v3, v2 3571; P8BE-NEXT: blr 3572; 3573; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3574; P8LE: # %bb.0: # %entry 3575; P8LE-NEXT: sldi r4, r4, 3 3576; P8LE-NEXT: lfdux f0, r3, r4 3577; P8LE-NEXT: lfd f1, 16(r3) 3578; P8LE-NEXT: lfd f2, 8(r3) 3579; P8LE-NEXT: lfd f3, 24(r3) 3580; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3581; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3582; P8LE-NEXT: xvcvdpuxws v2, vs0 3583; P8LE-NEXT: xvcvdpuxws v3, vs1 3584; P8LE-NEXT: vmrgew v2, v3, v2 3585; P8LE-NEXT: blr 3586entry: 3587 %idxprom = sext i32 %elem to i64 3588 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3589 %0 = load double, double* %arrayidx, align 8 3590 %conv = fptoui double %0 to i32 3591 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3592 %add = add nsw i32 %elem, 1 3593 %idxprom1 = sext i32 %add to i64 3594 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3595 %1 = load double, double* %arrayidx2, align 8 3596 %conv3 = fptoui double %1 to i32 3597 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3598 %add5 = add nsw i32 %elem, 2 3599 %idxprom6 = sext i32 %add5 to i64 3600 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3601 %2 = load double, double* %arrayidx7, align 8 3602 %conv8 = fptoui double %2 to i32 3603 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3604 %add10 = add nsw i32 %elem, 3 3605 %idxprom11 = sext i32 %add10 to i64 3606 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3607 %3 = load double, double* %arrayidx12, align 8 3608 %conv13 = fptoui double %3 to i32 3609 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3610 ret <4 x i32> %vecinit14 3611} 3612 3613define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3614; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3615; P9BE: # %bb.0: # %entry 3616; P9BE-NEXT: sldi r4, r4, 3 3617; P9BE-NEXT: lfdux f0, r3, r4 3618; P9BE-NEXT: lfd f1, -8(r3) 3619; P9BE-NEXT: lfd f2, -16(r3) 3620; P9BE-NEXT: lfd f3, -24(r3) 3621; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3622; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3623; P9BE-NEXT: xvcvdpuxws v2, vs1 3624; P9BE-NEXT: xvcvdpuxws v3, vs0 3625; P9BE-NEXT: vmrgew v2, v3, v2 3626; P9BE-NEXT: blr 3627; 3628; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3629; P9LE: # %bb.0: # %entry 3630; P9LE-NEXT: sldi r4, r4, 3 3631; P9LE-NEXT: lfdux f0, r3, r4 3632; P9LE-NEXT: lfd f2, -16(r3) 3633; P9LE-NEXT: lfd f1, -8(r3) 3634; P9LE-NEXT: lfd f3, -24(r3) 3635; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3636; P9LE-NEXT: xvcvdpuxws v2, vs0 3637; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3638; P9LE-NEXT: xvcvdpuxws v3, vs0 3639; P9LE-NEXT: vmrgew v2, v3, v2 3640; P9LE-NEXT: blr 3641; 3642; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3643; P8BE: # %bb.0: # %entry 3644; P8BE-NEXT: sldi r4, r4, 3 3645; P8BE-NEXT: lfdux f0, r3, r4 3646; P8BE-NEXT: lfd f1, -8(r3) 3647; P8BE-NEXT: lfd f2, -24(r3) 3648; P8BE-NEXT: lfd f3, -16(r3) 3649; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3650; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3651; P8BE-NEXT: xvcvdpuxws v2, vs1 3652; P8BE-NEXT: xvcvdpuxws v3, vs0 3653; P8BE-NEXT: vmrgew v2, v3, v2 3654; P8BE-NEXT: blr 3655; 3656; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3657; P8LE: # %bb.0: # %entry 3658; P8LE-NEXT: sldi r4, r4, 3 3659; P8LE-NEXT: lfdux f0, r3, r4 3660; P8LE-NEXT: lfd f1, -16(r3) 3661; P8LE-NEXT: lfd f2, -8(r3) 3662; P8LE-NEXT: lfd f3, -24(r3) 3663; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3664; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3665; P8LE-NEXT: xvcvdpuxws v2, vs0 3666; P8LE-NEXT: xvcvdpuxws v3, vs1 3667; P8LE-NEXT: vmrgew v2, v3, v2 3668; P8LE-NEXT: blr 3669entry: 3670 %idxprom = sext i32 %elem to i64 3671 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3672 %0 = load double, double* %arrayidx, align 8 3673 %conv = fptoui double %0 to i32 3674 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3675 %sub = add nsw i32 %elem, -1 3676 %idxprom1 = sext i32 %sub to i64 3677 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3678 %1 = load double, double* %arrayidx2, align 8 3679 %conv3 = fptoui double %1 to i32 3680 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3681 %sub5 = add nsw i32 %elem, -2 3682 %idxprom6 = sext i32 %sub5 to i64 3683 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3684 %2 = load double, double* %arrayidx7, align 8 3685 %conv8 = fptoui double %2 to i32 3686 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3687 %sub10 = add nsw i32 %elem, -3 3688 %idxprom11 = sext i32 %sub10 to i64 3689 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3690 %3 = load double, double* %arrayidx12, align 8 3691 %conv13 = fptoui double %3 to i32 3692 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3693 ret <4 x i32> %vecinit14 3694} 3695 3696define <4 x i32> @spltRegValConvdtoui(double %val) { 3697; P9BE-LABEL: spltRegValConvdtoui: 3698; P9BE: # %bb.0: # %entry 3699; P9BE-NEXT: xscvdpuxws f0, f1 3700; P9BE-NEXT: xxspltw v2, vs0, 1 3701; P9BE-NEXT: blr 3702; 3703; P9LE-LABEL: spltRegValConvdtoui: 3704; P9LE: # %bb.0: # %entry 3705; P9LE-NEXT: xscvdpuxws f0, f1 3706; P9LE-NEXT: xxspltw v2, vs0, 1 3707; P9LE-NEXT: blr 3708; 3709; P8BE-LABEL: spltRegValConvdtoui: 3710; P8BE: # %bb.0: # %entry 3711; P8BE-NEXT: xscvdpuxws f0, f1 3712; P8BE-NEXT: xxspltw v2, vs0, 1 3713; P8BE-NEXT: blr 3714; 3715; P8LE-LABEL: spltRegValConvdtoui: 3716; P8LE: # %bb.0: # %entry 3717; P8LE-NEXT: xscvdpuxws f0, f1 3718; P8LE-NEXT: xxspltw v2, vs0, 1 3719; P8LE-NEXT: blr 3720entry: 3721 %conv = fptoui double %val to i32 3722 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3723 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3724 ret <4 x i32> %splat.splat 3725} 3726 3727define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3728; P9BE-LABEL: spltMemValConvdtoui: 3729; P9BE: # %bb.0: # %entry 3730; P9BE-NEXT: lfd f0, 0(r3) 3731; P9BE-NEXT: xscvdpuxws f0, f0 3732; P9BE-NEXT: xxspltw v2, vs0, 1 3733; P9BE-NEXT: blr 3734; 3735; P9LE-LABEL: spltMemValConvdtoui: 3736; P9LE: # %bb.0: # %entry 3737; P9LE-NEXT: lfd f0, 0(r3) 3738; P9LE-NEXT: xscvdpuxws f0, f0 3739; P9LE-NEXT: xxspltw v2, vs0, 1 3740; P9LE-NEXT: blr 3741; 3742; P8BE-LABEL: spltMemValConvdtoui: 3743; P8BE: # %bb.0: # %entry 3744; P8BE-NEXT: lfdx f0, 0, r3 3745; P8BE-NEXT: xscvdpuxws f0, f0 3746; P8BE-NEXT: xxspltw v2, vs0, 1 3747; P8BE-NEXT: blr 3748; 3749; P8LE-LABEL: spltMemValConvdtoui: 3750; P8LE: # %bb.0: # %entry 3751; P8LE-NEXT: lfdx f0, 0, r3 3752; P8LE-NEXT: xscvdpuxws f0, f0 3753; P8LE-NEXT: xxspltw v2, vs0, 1 3754; P8LE-NEXT: blr 3755entry: 3756 %0 = load double, double* %ptr, align 8 3757 %conv = fptoui double %0 to i32 3758 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3759 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3760 ret <4 x i32> %splat.splat 3761} 3762 3763define <2 x i64> @allZeroll() { 3764; P9BE-LABEL: allZeroll: 3765; P9BE: # %bb.0: # %entry 3766; P9BE-NEXT: xxlxor v2, v2, v2 3767; P9BE-NEXT: blr 3768; 3769; P9LE-LABEL: allZeroll: 3770; P9LE: # %bb.0: # %entry 3771; P9LE-NEXT: xxlxor v2, v2, v2 3772; P9LE-NEXT: blr 3773; 3774; P8BE-LABEL: allZeroll: 3775; P8BE: # %bb.0: # %entry 3776; P8BE-NEXT: xxlxor v2, v2, v2 3777; P8BE-NEXT: blr 3778; 3779; P8LE-LABEL: allZeroll: 3780; P8LE: # %bb.0: # %entry 3781; P8LE-NEXT: xxlxor v2, v2, v2 3782; P8LE-NEXT: blr 3783entry: 3784 ret <2 x i64> zeroinitializer 3785} 3786 3787define <2 x i64> @spltConst1ll() { 3788; P9BE-LABEL: spltConst1ll: 3789; P9BE: # %bb.0: # %entry 3790; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3791; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3792; P9BE-NEXT: lxv v2, 0(r3) 3793; P9BE-NEXT: blr 3794; 3795; P9LE-LABEL: spltConst1ll: 3796; P9LE: # %bb.0: # %entry 3797; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3798; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3799; P9LE-NEXT: lxv v2, 0(r3) 3800; P9LE-NEXT: blr 3801; 3802; P8BE-LABEL: spltConst1ll: 3803; P8BE: # %bb.0: # %entry 3804; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3805; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3806; P8BE-NEXT: lxvd2x v2, 0, r3 3807; P8BE-NEXT: blr 3808; 3809; P8LE-LABEL: spltConst1ll: 3810; P8LE: # %bb.0: # %entry 3811; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3812; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3813; P8LE-NEXT: lxvd2x vs0, 0, r3 3814; P8LE-NEXT: xxswapd v2, vs0 3815; P8LE-NEXT: blr 3816entry: 3817 ret <2 x i64> <i64 1, i64 1> 3818} 3819 3820define <2 x i64> @spltConst16kll() { 3821; P9BE-LABEL: spltConst16kll: 3822; P9BE: # %bb.0: # %entry 3823; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3824; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3825; P9BE-NEXT: lxv v2, 0(r3) 3826; P9BE-NEXT: blr 3827; 3828; P9LE-LABEL: spltConst16kll: 3829; P9LE: # %bb.0: # %entry 3830; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3831; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3832; P9LE-NEXT: lxv v2, 0(r3) 3833; P9LE-NEXT: blr 3834; 3835; P8BE-LABEL: spltConst16kll: 3836; P8BE: # %bb.0: # %entry 3837; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3838; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3839; P8BE-NEXT: lxvd2x v2, 0, r3 3840; P8BE-NEXT: blr 3841; 3842; P8LE-LABEL: spltConst16kll: 3843; P8LE: # %bb.0: # %entry 3844; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3845; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3846; P8LE-NEXT: lxvd2x vs0, 0, r3 3847; P8LE-NEXT: xxswapd v2, vs0 3848; P8LE-NEXT: blr 3849entry: 3850 ret <2 x i64> <i64 32767, i64 32767> 3851} 3852 3853define <2 x i64> @spltConst32kll() { 3854; P9BE-LABEL: spltConst32kll: 3855; P9BE: # %bb.0: # %entry 3856; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3857; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3858; P9BE-NEXT: lxv v2, 0(r3) 3859; P9BE-NEXT: blr 3860; 3861; P9LE-LABEL: spltConst32kll: 3862; P9LE: # %bb.0: # %entry 3863; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3864; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3865; P9LE-NEXT: lxv v2, 0(r3) 3866; P9LE-NEXT: blr 3867; 3868; P8BE-LABEL: spltConst32kll: 3869; P8BE: # %bb.0: # %entry 3870; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3871; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3872; P8BE-NEXT: lxvd2x v2, 0, r3 3873; P8BE-NEXT: blr 3874; 3875; P8LE-LABEL: spltConst32kll: 3876; P8LE: # %bb.0: # %entry 3877; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3878; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3879; P8LE-NEXT: lxvd2x vs0, 0, r3 3880; P8LE-NEXT: xxswapd v2, vs0 3881; P8LE-NEXT: blr 3882entry: 3883 ret <2 x i64> <i64 65535, i64 65535> 3884} 3885 3886define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3887; P9BE-LABEL: fromRegsll: 3888; P9BE: # %bb.0: # %entry 3889; P9BE-NEXT: mtvsrdd v2, r3, r4 3890; P9BE-NEXT: blr 3891; 3892; P9LE-LABEL: fromRegsll: 3893; P9LE: # %bb.0: # %entry 3894; P9LE-NEXT: mtvsrdd v2, r4, r3 3895; P9LE-NEXT: blr 3896; 3897; P8BE-LABEL: fromRegsll: 3898; P8BE: # %bb.0: # %entry 3899; P8BE-NEXT: mtfprd f0, r4 3900; P8BE-NEXT: mtfprd f1, r3 3901; P8BE-NEXT: xxmrghd v2, vs1, vs0 3902; P8BE-NEXT: blr 3903; 3904; P8LE-LABEL: fromRegsll: 3905; P8LE: # %bb.0: # %entry 3906; P8LE-NEXT: mtfprd f0, r3 3907; P8LE-NEXT: mtfprd f1, r4 3908; P8LE-NEXT: xxmrghd v2, vs1, vs0 3909; P8LE-NEXT: blr 3910entry: 3911 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3912 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3913 ret <2 x i64> %vecinit1 3914} 3915 3916define <2 x i64> @fromDiffConstsll() { 3917; P9BE-LABEL: fromDiffConstsll: 3918; P9BE: # %bb.0: # %entry 3919; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3920; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3921; P9BE-NEXT: lxv v2, 0(r3) 3922; P9BE-NEXT: blr 3923; 3924; P9LE-LABEL: fromDiffConstsll: 3925; P9LE: # %bb.0: # %entry 3926; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3927; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3928; P9LE-NEXT: lxv v2, 0(r3) 3929; P9LE-NEXT: blr 3930; 3931; P8BE-LABEL: fromDiffConstsll: 3932; P8BE: # %bb.0: # %entry 3933; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3934; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3935; P8BE-NEXT: lxvd2x v2, 0, r3 3936; P8BE-NEXT: blr 3937; 3938; P8LE-LABEL: fromDiffConstsll: 3939; P8LE: # %bb.0: # %entry 3940; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3941; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3942; P8LE-NEXT: lxvd2x vs0, 0, r3 3943; P8LE-NEXT: xxswapd v2, vs0 3944; P8LE-NEXT: blr 3945entry: 3946 ret <2 x i64> <i64 242, i64 -113> 3947} 3948 3949define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3950; P9BE-LABEL: fromDiffMemConsAll: 3951; P9BE: # %bb.0: # %entry 3952; P9BE-NEXT: lxv v2, 0(r3) 3953; P9BE-NEXT: blr 3954; 3955; P9LE-LABEL: fromDiffMemConsAll: 3956; P9LE: # %bb.0: # %entry 3957; P9LE-NEXT: lxv v2, 0(r3) 3958; P9LE-NEXT: blr 3959; 3960; P8BE-LABEL: fromDiffMemConsAll: 3961; P8BE: # %bb.0: # %entry 3962; P8BE-NEXT: lxvd2x v2, 0, r3 3963; P8BE-NEXT: blr 3964; 3965; P8LE-LABEL: fromDiffMemConsAll: 3966; P8LE: # %bb.0: # %entry 3967; P8LE-NEXT: lxvd2x vs0, 0, r3 3968; P8LE-NEXT: xxswapd v2, vs0 3969; P8LE-NEXT: blr 3970entry: 3971 %0 = load i64, i64* %arr, align 8 3972 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3973 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3974 %1 = load i64, i64* %arrayidx1, align 8 3975 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3976 ret <2 x i64> %vecinit2 3977} 3978 3979define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3980; P9BE-LABEL: fromDiffMemConsDll: 3981; P9BE: # %bb.0: # %entry 3982; P9BE-NEXT: lxv v2, 16(r3) 3983; P9BE-NEXT: xxswapd v2, v2 3984; P9BE-NEXT: blr 3985; 3986; P9LE-LABEL: fromDiffMemConsDll: 3987; P9LE: # %bb.0: # %entry 3988; P9LE-NEXT: addi r3, r3, 16 3989; P9LE-NEXT: lxvd2x v2, 0, r3 3990; P9LE-NEXT: blr 3991; 3992; P8BE-LABEL: fromDiffMemConsDll: 3993; P8BE: # %bb.0: # %entry 3994; P8BE-NEXT: addi r3, r3, 16 3995; P8BE-NEXT: lxvd2x v2, 0, r3 3996; P8BE-NEXT: xxswapd v2, v2 3997; P8BE-NEXT: blr 3998; 3999; P8LE-LABEL: fromDiffMemConsDll: 4000; P8LE: # %bb.0: # %entry 4001; P8LE-NEXT: addi r3, r3, 16 4002; P8LE-NEXT: lxvd2x v2, 0, r3 4003; P8LE-NEXT: blr 4004entry: 4005 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4006 %0 = load i64, i64* %arrayidx, align 8 4007 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4008 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4009 %1 = load i64, i64* %arrayidx1, align 8 4010 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4011 ret <2 x i64> %vecinit2 4012} 4013 4014define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4015; P9BE-LABEL: fromDiffMemVarAll: 4016; P9BE: # %bb.0: # %entry 4017; P9BE-NEXT: sldi r4, r4, 3 4018; P9BE-NEXT: lxvx v2, r3, r4 4019; P9BE-NEXT: blr 4020; 4021; P9LE-LABEL: fromDiffMemVarAll: 4022; P9LE: # %bb.0: # %entry 4023; P9LE-NEXT: sldi r4, r4, 3 4024; P9LE-NEXT: lxvx v2, r3, r4 4025; P9LE-NEXT: blr 4026; 4027; P8BE-LABEL: fromDiffMemVarAll: 4028; P8BE: # %bb.0: # %entry 4029; P8BE-NEXT: sldi r4, r4, 3 4030; P8BE-NEXT: lxvd2x v2, r3, r4 4031; P8BE-NEXT: blr 4032; 4033; P8LE-LABEL: fromDiffMemVarAll: 4034; P8LE: # %bb.0: # %entry 4035; P8LE-NEXT: sldi r4, r4, 3 4036; P8LE-NEXT: lxvd2x vs0, r3, r4 4037; P8LE-NEXT: xxswapd v2, vs0 4038; P8LE-NEXT: blr 4039entry: 4040 %idxprom = sext i32 %elem to i64 4041 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4042 %0 = load i64, i64* %arrayidx, align 8 4043 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4044 %add = add nsw i32 %elem, 1 4045 %idxprom1 = sext i32 %add to i64 4046 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4047 %1 = load i64, i64* %arrayidx2, align 8 4048 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4049 ret <2 x i64> %vecinit3 4050} 4051 4052define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4053; P9BE-LABEL: fromDiffMemVarDll: 4054; P9BE: # %bb.0: # %entry 4055; P9BE-NEXT: sldi r4, r4, 3 4056; P9BE-NEXT: add r3, r3, r4 4057; P9BE-NEXT: li r4, -8 4058; P9BE-NEXT: lxvx v2, r3, r4 4059; P9BE-NEXT: xxswapd v2, v2 4060; P9BE-NEXT: blr 4061; 4062; P9LE-LABEL: fromDiffMemVarDll: 4063; P9LE: # %bb.0: # %entry 4064; P9LE-NEXT: sldi r4, r4, 3 4065; P9LE-NEXT: add r3, r3, r4 4066; P9LE-NEXT: addi r3, r3, -8 4067; P9LE-NEXT: lxvd2x v2, 0, r3 4068; P9LE-NEXT: blr 4069; 4070; P8BE-LABEL: fromDiffMemVarDll: 4071; P8BE: # %bb.0: # %entry 4072; P8BE-NEXT: sldi r4, r4, 3 4073; P8BE-NEXT: add r3, r3, r4 4074; P8BE-NEXT: addi r3, r3, -8 4075; P8BE-NEXT: lxvd2x v2, 0, r3 4076; P8BE-NEXT: xxswapd v2, v2 4077; P8BE-NEXT: blr 4078; 4079; P8LE-LABEL: fromDiffMemVarDll: 4080; P8LE: # %bb.0: # %entry 4081; P8LE-NEXT: sldi r4, r4, 3 4082; P8LE-NEXT: add r3, r3, r4 4083; P8LE-NEXT: addi r3, r3, -8 4084; P8LE-NEXT: lxvd2x v2, 0, r3 4085; P8LE-NEXT: blr 4086entry: 4087 %idxprom = sext i32 %elem to i64 4088 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4089 %0 = load i64, i64* %arrayidx, align 8 4090 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4091 %sub = add nsw i32 %elem, -1 4092 %idxprom1 = sext i32 %sub to i64 4093 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4094 %1 = load i64, i64* %arrayidx2, align 8 4095 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4096 ret <2 x i64> %vecinit3 4097} 4098 4099define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4100; P9BE-LABEL: fromRandMemConsll: 4101; P9BE: # %bb.0: # %entry 4102; P9BE-NEXT: ld r4, 32(r3) 4103; P9BE-NEXT: ld r3, 144(r3) 4104; P9BE-NEXT: mtvsrdd v2, r4, r3 4105; P9BE-NEXT: blr 4106; 4107; P9LE-LABEL: fromRandMemConsll: 4108; P9LE: # %bb.0: # %entry 4109; P9LE-NEXT: ld r4, 32(r3) 4110; P9LE-NEXT: ld r3, 144(r3) 4111; P9LE-NEXT: mtvsrdd v2, r3, r4 4112; P9LE-NEXT: blr 4113; 4114; P8BE-LABEL: fromRandMemConsll: 4115; P8BE: # %bb.0: # %entry 4116; P8BE-NEXT: ld r4, 144(r3) 4117; P8BE-NEXT: ld r3, 32(r3) 4118; P8BE-NEXT: mtfprd f0, r4 4119; P8BE-NEXT: mtfprd f1, r3 4120; P8BE-NEXT: xxmrghd v2, vs1, vs0 4121; P8BE-NEXT: blr 4122; 4123; P8LE-LABEL: fromRandMemConsll: 4124; P8LE: # %bb.0: # %entry 4125; P8LE-NEXT: ld r4, 32(r3) 4126; P8LE-NEXT: ld r3, 144(r3) 4127; P8LE-NEXT: mtfprd f0, r4 4128; P8LE-NEXT: mtfprd f1, r3 4129; P8LE-NEXT: xxmrghd v2, vs1, vs0 4130; P8LE-NEXT: blr 4131entry: 4132 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4133 %0 = load i64, i64* %arrayidx, align 8 4134 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4135 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4136 %1 = load i64, i64* %arrayidx1, align 8 4137 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4138 ret <2 x i64> %vecinit2 4139} 4140 4141define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4142; P9BE-LABEL: fromRandMemVarll: 4143; P9BE: # %bb.0: # %entry 4144; P9BE-NEXT: sldi r4, r4, 3 4145; P9BE-NEXT: add r3, r3, r4 4146; P9BE-NEXT: ld r4, 32(r3) 4147; P9BE-NEXT: ld r3, 8(r3) 4148; P9BE-NEXT: mtvsrdd v2, r4, r3 4149; P9BE-NEXT: blr 4150; 4151; P9LE-LABEL: fromRandMemVarll: 4152; P9LE: # %bb.0: # %entry 4153; P9LE-NEXT: sldi r4, r4, 3 4154; P9LE-NEXT: add r3, r3, r4 4155; P9LE-NEXT: ld r4, 32(r3) 4156; P9LE-NEXT: ld r3, 8(r3) 4157; P9LE-NEXT: mtvsrdd v2, r3, r4 4158; P9LE-NEXT: blr 4159; 4160; P8BE-LABEL: fromRandMemVarll: 4161; P8BE: # %bb.0: # %entry 4162; P8BE-NEXT: sldi r4, r4, 3 4163; P8BE-NEXT: add r3, r3, r4 4164; P8BE-NEXT: ld r4, 8(r3) 4165; P8BE-NEXT: ld r3, 32(r3) 4166; P8BE-NEXT: mtfprd f0, r4 4167; P8BE-NEXT: mtfprd f1, r3 4168; P8BE-NEXT: xxmrghd v2, vs1, vs0 4169; P8BE-NEXT: blr 4170; 4171; P8LE-LABEL: fromRandMemVarll: 4172; P8LE: # %bb.0: # %entry 4173; P8LE-NEXT: sldi r4, r4, 3 4174; P8LE-NEXT: add r3, r3, r4 4175; P8LE-NEXT: ld r4, 32(r3) 4176; P8LE-NEXT: ld r3, 8(r3) 4177; P8LE-NEXT: mtfprd f0, r4 4178; P8LE-NEXT: mtfprd f1, r3 4179; P8LE-NEXT: xxmrghd v2, vs1, vs0 4180; P8LE-NEXT: blr 4181entry: 4182 %add = add nsw i32 %elem, 4 4183 %idxprom = sext i32 %add to i64 4184 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4185 %0 = load i64, i64* %arrayidx, align 8 4186 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4187 %add1 = add nsw i32 %elem, 1 4188 %idxprom2 = sext i32 %add1 to i64 4189 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4190 %1 = load i64, i64* %arrayidx3, align 8 4191 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4192 ret <2 x i64> %vecinit4 4193} 4194 4195define <2 x i64> @spltRegValll(i64 %val) { 4196; P9BE-LABEL: spltRegValll: 4197; P9BE: # %bb.0: # %entry 4198; P9BE-NEXT: mtvsrdd v2, r3, r3 4199; P9BE-NEXT: blr 4200; 4201; P9LE-LABEL: spltRegValll: 4202; P9LE: # %bb.0: # %entry 4203; P9LE-NEXT: mtvsrdd v2, r3, r3 4204; P9LE-NEXT: blr 4205; 4206; P8BE-LABEL: spltRegValll: 4207; P8BE: # %bb.0: # %entry 4208; P8BE-NEXT: mtfprd f0, r3 4209; P8BE-NEXT: xxspltd v2, vs0, 0 4210; P8BE-NEXT: blr 4211; 4212; P8LE-LABEL: spltRegValll: 4213; P8LE: # %bb.0: # %entry 4214; P8LE-NEXT: mtfprd f0, r3 4215; P8LE-NEXT: xxspltd v2, vs0, 0 4216; P8LE-NEXT: blr 4217entry: 4218 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4219 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4220 ret <2 x i64> %splat.splat 4221} 4222 4223define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4224; P9BE-LABEL: spltMemValll: 4225; P9BE: # %bb.0: # %entry 4226; P9BE-NEXT: lxvdsx v2, 0, r3 4227; P9BE-NEXT: blr 4228; 4229; P9LE-LABEL: spltMemValll: 4230; P9LE: # %bb.0: # %entry 4231; P9LE-NEXT: lxvdsx v2, 0, r3 4232; P9LE-NEXT: blr 4233; 4234; P8BE-LABEL: spltMemValll: 4235; P8BE: # %bb.0: # %entry 4236; P8BE-NEXT: lxvdsx v2, 0, r3 4237; P8BE-NEXT: blr 4238; 4239; P8LE-LABEL: spltMemValll: 4240; P8LE: # %bb.0: # %entry 4241; P8LE-NEXT: lxvdsx v2, 0, r3 4242; P8LE-NEXT: blr 4243entry: 4244 %0 = load i64, i64* %ptr, align 8 4245 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4246 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4247 ret <2 x i64> %splat.splat 4248} 4249 4250define <2 x i64> @spltCnstConvftoll() { 4251; P9BE-LABEL: spltCnstConvftoll: 4252; P9BE: # %bb.0: # %entry 4253; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4254; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4255; P9BE-NEXT: lxv v2, 0(r3) 4256; P9BE-NEXT: blr 4257; 4258; P9LE-LABEL: spltCnstConvftoll: 4259; P9LE: # %bb.0: # %entry 4260; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4261; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4262; P9LE-NEXT: lxv v2, 0(r3) 4263; P9LE-NEXT: blr 4264; 4265; P8BE-LABEL: spltCnstConvftoll: 4266; P8BE: # %bb.0: # %entry 4267; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4268; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4269; P8BE-NEXT: lxvd2x v2, 0, r3 4270; P8BE-NEXT: blr 4271; 4272; P8LE-LABEL: spltCnstConvftoll: 4273; P8LE: # %bb.0: # %entry 4274; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4275; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4276; P8LE-NEXT: lxvd2x vs0, 0, r3 4277; P8LE-NEXT: xxswapd v2, vs0 4278; P8LE-NEXT: blr 4279entry: 4280 ret <2 x i64> <i64 4, i64 4> 4281} 4282 4283define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4284; P9BE-LABEL: fromRegsConvftoll: 4285; P9BE: # %bb.0: # %entry 4286; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4287; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4288; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4289; P9BE-NEXT: xvcvdpsxds v2, vs0 4290; P9BE-NEXT: blr 4291; 4292; P9LE-LABEL: fromRegsConvftoll: 4293; P9LE: # %bb.0: # %entry 4294; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4295; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4296; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4297; P9LE-NEXT: xvcvdpsxds v2, vs0 4298; P9LE-NEXT: blr 4299; 4300; P8BE-LABEL: fromRegsConvftoll: 4301; P8BE: # %bb.0: # %entry 4302; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4303; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4304; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4305; P8BE-NEXT: xvcvdpsxds v2, vs0 4306; P8BE-NEXT: blr 4307; 4308; P8LE-LABEL: fromRegsConvftoll: 4309; P8LE: # %bb.0: # %entry 4310; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4311; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4312; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4313; P8LE-NEXT: xvcvdpsxds v2, vs0 4314; P8LE-NEXT: blr 4315entry: 4316 %conv = fptosi float %a to i64 4317 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4318 %conv1 = fptosi float %b to i64 4319 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4320 ret <2 x i64> %vecinit2 4321} 4322 4323define <2 x i64> @fromDiffConstsConvftoll() { 4324; P9BE-LABEL: fromDiffConstsConvftoll: 4325; P9BE: # %bb.0: # %entry 4326; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4327; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4328; P9BE-NEXT: lxv v2, 0(r3) 4329; P9BE-NEXT: blr 4330; 4331; P9LE-LABEL: fromDiffConstsConvftoll: 4332; P9LE: # %bb.0: # %entry 4333; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4334; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4335; P9LE-NEXT: lxv v2, 0(r3) 4336; P9LE-NEXT: blr 4337; 4338; P8BE-LABEL: fromDiffConstsConvftoll: 4339; P8BE: # %bb.0: # %entry 4340; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4341; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4342; P8BE-NEXT: lxvd2x v2, 0, r3 4343; P8BE-NEXT: blr 4344; 4345; P8LE-LABEL: fromDiffConstsConvftoll: 4346; P8LE: # %bb.0: # %entry 4347; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4348; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4349; P8LE-NEXT: lxvd2x vs0, 0, r3 4350; P8LE-NEXT: xxswapd v2, vs0 4351; P8LE-NEXT: blr 4352entry: 4353 ret <2 x i64> <i64 24, i64 234> 4354} 4355 4356define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4357; P9BE-LABEL: fromDiffMemConsAConvftoll: 4358; P9BE: # %bb.0: # %entry 4359; P9BE-NEXT: lfs f0, 0(r3) 4360; P9BE-NEXT: lfs f1, 4(r3) 4361; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4362; P9BE-NEXT: xvcvdpsxds v2, vs0 4363; P9BE-NEXT: blr 4364; 4365; P9LE-LABEL: fromDiffMemConsAConvftoll: 4366; P9LE: # %bb.0: # %entry 4367; P9LE-NEXT: lfs f0, 0(r3) 4368; P9LE-NEXT: lfs f1, 4(r3) 4369; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4370; P9LE-NEXT: xvcvdpsxds v2, vs0 4371; P9LE-NEXT: blr 4372; 4373; P8BE-LABEL: fromDiffMemConsAConvftoll: 4374; P8BE: # %bb.0: # %entry 4375; P8BE-NEXT: lfs f0, 0(r3) 4376; P8BE-NEXT: lfs f1, 4(r3) 4377; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4378; P8BE-NEXT: xvcvdpsxds v2, vs0 4379; P8BE-NEXT: blr 4380; 4381; P8LE-LABEL: fromDiffMemConsAConvftoll: 4382; P8LE: # %bb.0: # %entry 4383; P8LE-NEXT: lfs f0, 0(r3) 4384; P8LE-NEXT: lfs f1, 4(r3) 4385; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4386; P8LE-NEXT: xvcvdpsxds v2, vs0 4387; P8LE-NEXT: blr 4388entry: 4389 %0 = load float, float* %ptr, align 4 4390 %conv = fptosi float %0 to i64 4391 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4392 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4393 %1 = load float, float* %arrayidx1, align 4 4394 %conv2 = fptosi float %1 to i64 4395 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4396 ret <2 x i64> %vecinit3 4397} 4398 4399define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4400; P9BE-LABEL: fromDiffMemConsDConvftoll: 4401; P9BE: # %bb.0: # %entry 4402; P9BE-NEXT: lfs f0, 12(r3) 4403; P9BE-NEXT: lfs f1, 8(r3) 4404; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4405; P9BE-NEXT: xvcvdpsxds v2, vs0 4406; P9BE-NEXT: blr 4407; 4408; P9LE-LABEL: fromDiffMemConsDConvftoll: 4409; P9LE: # %bb.0: # %entry 4410; P9LE-NEXT: lfs f0, 12(r3) 4411; P9LE-NEXT: lfs f1, 8(r3) 4412; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4413; P9LE-NEXT: xvcvdpsxds v2, vs0 4414; P9LE-NEXT: blr 4415; 4416; P8BE-LABEL: fromDiffMemConsDConvftoll: 4417; P8BE: # %bb.0: # %entry 4418; P8BE-NEXT: lfs f0, 12(r3) 4419; P8BE-NEXT: lfs f1, 8(r3) 4420; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4421; P8BE-NEXT: xvcvdpsxds v2, vs0 4422; P8BE-NEXT: blr 4423; 4424; P8LE-LABEL: fromDiffMemConsDConvftoll: 4425; P8LE: # %bb.0: # %entry 4426; P8LE-NEXT: lfs f0, 12(r3) 4427; P8LE-NEXT: lfs f1, 8(r3) 4428; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4429; P8LE-NEXT: xvcvdpsxds v2, vs0 4430; P8LE-NEXT: blr 4431entry: 4432 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4433 %0 = load float, float* %arrayidx, align 4 4434 %conv = fptosi float %0 to i64 4435 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4436 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4437 %1 = load float, float* %arrayidx1, align 4 4438 %conv2 = fptosi float %1 to i64 4439 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4440 ret <2 x i64> %vecinit3 4441} 4442 4443define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4444; P9BE-LABEL: fromDiffMemVarAConvftoll: 4445; P9BE: # %bb.0: # %entry 4446; P9BE-NEXT: sldi r4, r4, 2 4447; P9BE-NEXT: lfsux f0, r3, r4 4448; P9BE-NEXT: lfs f1, 4(r3) 4449; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4450; P9BE-NEXT: xvcvdpsxds v2, vs0 4451; P9BE-NEXT: blr 4452; 4453; P9LE-LABEL: fromDiffMemVarAConvftoll: 4454; P9LE: # %bb.0: # %entry 4455; P9LE-NEXT: sldi r4, r4, 2 4456; P9LE-NEXT: lfsux f0, r3, r4 4457; P9LE-NEXT: lfs f1, 4(r3) 4458; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4459; P9LE-NEXT: xvcvdpsxds v2, vs0 4460; P9LE-NEXT: blr 4461; 4462; P8BE-LABEL: fromDiffMemVarAConvftoll: 4463; P8BE: # %bb.0: # %entry 4464; P8BE-NEXT: sldi r4, r4, 2 4465; P8BE-NEXT: lfsux f0, r3, r4 4466; P8BE-NEXT: lfs f1, 4(r3) 4467; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4468; P8BE-NEXT: xvcvdpsxds v2, vs0 4469; P8BE-NEXT: blr 4470; 4471; P8LE-LABEL: fromDiffMemVarAConvftoll: 4472; P8LE: # %bb.0: # %entry 4473; P8LE-NEXT: sldi r4, r4, 2 4474; P8LE-NEXT: lfsux f0, r3, r4 4475; P8LE-NEXT: lfs f1, 4(r3) 4476; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4477; P8LE-NEXT: xvcvdpsxds v2, vs0 4478; P8LE-NEXT: blr 4479entry: 4480 %idxprom = sext i32 %elem to i64 4481 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4482 %0 = load float, float* %arrayidx, align 4 4483 %conv = fptosi float %0 to i64 4484 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4485 %add = add nsw i32 %elem, 1 4486 %idxprom1 = sext i32 %add to i64 4487 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4488 %1 = load float, float* %arrayidx2, align 4 4489 %conv3 = fptosi float %1 to i64 4490 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4491 ret <2 x i64> %vecinit4 4492} 4493 4494define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4495; P9BE-LABEL: fromDiffMemVarDConvftoll: 4496; P9BE: # %bb.0: # %entry 4497; P9BE-NEXT: sldi r4, r4, 2 4498; P9BE-NEXT: lfsux f0, r3, r4 4499; P9BE-NEXT: lfs f1, -4(r3) 4500; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4501; P9BE-NEXT: xvcvdpsxds v2, vs0 4502; P9BE-NEXT: blr 4503; 4504; P9LE-LABEL: fromDiffMemVarDConvftoll: 4505; P9LE: # %bb.0: # %entry 4506; P9LE-NEXT: sldi r4, r4, 2 4507; P9LE-NEXT: lfsux f0, r3, r4 4508; P9LE-NEXT: lfs f1, -4(r3) 4509; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4510; P9LE-NEXT: xvcvdpsxds v2, vs0 4511; P9LE-NEXT: blr 4512; 4513; P8BE-LABEL: fromDiffMemVarDConvftoll: 4514; P8BE: # %bb.0: # %entry 4515; P8BE-NEXT: sldi r4, r4, 2 4516; P8BE-NEXT: lfsux f0, r3, r4 4517; P8BE-NEXT: lfs f1, -4(r3) 4518; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4519; P8BE-NEXT: xvcvdpsxds v2, vs0 4520; P8BE-NEXT: blr 4521; 4522; P8LE-LABEL: fromDiffMemVarDConvftoll: 4523; P8LE: # %bb.0: # %entry 4524; P8LE-NEXT: sldi r4, r4, 2 4525; P8LE-NEXT: lfsux f0, r3, r4 4526; P8LE-NEXT: lfs f1, -4(r3) 4527; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4528; P8LE-NEXT: xvcvdpsxds v2, vs0 4529; P8LE-NEXT: blr 4530entry: 4531 %idxprom = sext i32 %elem to i64 4532 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4533 %0 = load float, float* %arrayidx, align 4 4534 %conv = fptosi float %0 to i64 4535 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4536 %sub = add nsw i32 %elem, -1 4537 %idxprom1 = sext i32 %sub to i64 4538 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4539 %1 = load float, float* %arrayidx2, align 4 4540 %conv3 = fptosi float %1 to i64 4541 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4542 ret <2 x i64> %vecinit4 4543} 4544 4545define <2 x i64> @spltRegValConvftoll(float %val) { 4546; P9BE-LABEL: spltRegValConvftoll: 4547; P9BE: # %bb.0: # %entry 4548; P9BE-NEXT: xscvdpsxds f0, f1 4549; P9BE-NEXT: xxspltd v2, f0, 0 4550; P9BE-NEXT: blr 4551; 4552; P9LE-LABEL: spltRegValConvftoll: 4553; P9LE: # %bb.0: # %entry 4554; P9LE-NEXT: xscvdpsxds f0, f1 4555; P9LE-NEXT: xxspltd v2, f0, 0 4556; P9LE-NEXT: blr 4557; 4558; P8BE-LABEL: spltRegValConvftoll: 4559; P8BE: # %bb.0: # %entry 4560; P8BE-NEXT: xscvdpsxds f0, f1 4561; P8BE-NEXT: xxspltd v2, f0, 0 4562; P8BE-NEXT: blr 4563; 4564; P8LE-LABEL: spltRegValConvftoll: 4565; P8LE: # %bb.0: # %entry 4566; P8LE-NEXT: xscvdpsxds f0, f1 4567; P8LE-NEXT: xxspltd v2, f0, 0 4568; P8LE-NEXT: blr 4569entry: 4570 %conv = fptosi float %val to i64 4571 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4572 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4573 ret <2 x i64> %splat.splat 4574} 4575 4576define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4577; P9BE-LABEL: spltMemValConvftoll: 4578; P9BE: # %bb.0: # %entry 4579; P9BE-NEXT: lfs f0, 0(r3) 4580; P9BE-NEXT: xscvdpsxds f0, f0 4581; P9BE-NEXT: xxspltd v2, f0, 0 4582; P9BE-NEXT: blr 4583; 4584; P9LE-LABEL: spltMemValConvftoll: 4585; P9LE: # %bb.0: # %entry 4586; P9LE-NEXT: lfs f0, 0(r3) 4587; P9LE-NEXT: xscvdpsxds f0, f0 4588; P9LE-NEXT: xxspltd v2, vs0, 0 4589; P9LE-NEXT: blr 4590; 4591; P8BE-LABEL: spltMemValConvftoll: 4592; P8BE: # %bb.0: # %entry 4593; P8BE-NEXT: lfsx f0, 0, r3 4594; P8BE-NEXT: xscvdpsxds f0, f0 4595; P8BE-NEXT: xxspltd v2, f0, 0 4596; P8BE-NEXT: blr 4597; 4598; P8LE-LABEL: spltMemValConvftoll: 4599; P8LE: # %bb.0: # %entry 4600; P8LE-NEXT: lfsx f0, 0, r3 4601; P8LE-NEXT: xscvdpsxds f0, f0 4602; P8LE-NEXT: xxspltd v2, vs0, 0 4603; P8LE-NEXT: blr 4604entry: 4605 %0 = load float, float* %ptr, align 4 4606 %conv = fptosi float %0 to i64 4607 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4608 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4609 ret <2 x i64> %splat.splat 4610} 4611 4612define <2 x i64> @spltCnstConvdtoll() { 4613; P9BE-LABEL: spltCnstConvdtoll: 4614; P9BE: # %bb.0: # %entry 4615; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4616; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4617; P9BE-NEXT: lxv v2, 0(r3) 4618; P9BE-NEXT: blr 4619; 4620; P9LE-LABEL: spltCnstConvdtoll: 4621; P9LE: # %bb.0: # %entry 4622; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4623; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4624; P9LE-NEXT: lxv v2, 0(r3) 4625; P9LE-NEXT: blr 4626; 4627; P8BE-LABEL: spltCnstConvdtoll: 4628; P8BE: # %bb.0: # %entry 4629; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4630; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4631; P8BE-NEXT: lxvd2x v2, 0, r3 4632; P8BE-NEXT: blr 4633; 4634; P8LE-LABEL: spltCnstConvdtoll: 4635; P8LE: # %bb.0: # %entry 4636; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4637; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4638; P8LE-NEXT: lxvd2x vs0, 0, r3 4639; P8LE-NEXT: xxswapd v2, vs0 4640; P8LE-NEXT: blr 4641entry: 4642 ret <2 x i64> <i64 4, i64 4> 4643} 4644 4645define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4646; P9BE-LABEL: fromRegsConvdtoll: 4647; P9BE: # %bb.0: # %entry 4648; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4649; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4650; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4651; P9BE-NEXT: xvcvdpsxds v2, vs0 4652; P9BE-NEXT: blr 4653; 4654; P9LE-LABEL: fromRegsConvdtoll: 4655; P9LE: # %bb.0: # %entry 4656; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4657; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4658; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4659; P9LE-NEXT: xvcvdpsxds v2, vs0 4660; P9LE-NEXT: blr 4661; 4662; P8BE-LABEL: fromRegsConvdtoll: 4663; P8BE: # %bb.0: # %entry 4664; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4665; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4666; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4667; P8BE-NEXT: xvcvdpsxds v2, vs0 4668; P8BE-NEXT: blr 4669; 4670; P8LE-LABEL: fromRegsConvdtoll: 4671; P8LE: # %bb.0: # %entry 4672; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4673; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4674; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4675; P8LE-NEXT: xvcvdpsxds v2, vs0 4676; P8LE-NEXT: blr 4677entry: 4678 %conv = fptosi double %a to i64 4679 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4680 %conv1 = fptosi double %b to i64 4681 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4682 ret <2 x i64> %vecinit2 4683} 4684 4685define <2 x i64> @fromDiffConstsConvdtoll() { 4686; P9BE-LABEL: fromDiffConstsConvdtoll: 4687; P9BE: # %bb.0: # %entry 4688; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4689; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4690; P9BE-NEXT: lxv v2, 0(r3) 4691; P9BE-NEXT: blr 4692; 4693; P9LE-LABEL: fromDiffConstsConvdtoll: 4694; P9LE: # %bb.0: # %entry 4695; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4696; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4697; P9LE-NEXT: lxv v2, 0(r3) 4698; P9LE-NEXT: blr 4699; 4700; P8BE-LABEL: fromDiffConstsConvdtoll: 4701; P8BE: # %bb.0: # %entry 4702; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4703; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4704; P8BE-NEXT: lxvd2x v2, 0, r3 4705; P8BE-NEXT: blr 4706; 4707; P8LE-LABEL: fromDiffConstsConvdtoll: 4708; P8LE: # %bb.0: # %entry 4709; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4710; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4711; P8LE-NEXT: lxvd2x vs0, 0, r3 4712; P8LE-NEXT: xxswapd v2, vs0 4713; P8LE-NEXT: blr 4714entry: 4715 ret <2 x i64> <i64 24, i64 234> 4716} 4717 4718define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4719; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4720; P9BE: # %bb.0: # %entry 4721; P9BE-NEXT: lxv vs0, 0(r3) 4722; P9BE-NEXT: xvcvdpsxds v2, vs0 4723; P9BE-NEXT: blr 4724; 4725; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4726; P9LE: # %bb.0: # %entry 4727; P9LE-NEXT: lxv vs0, 0(r3) 4728; P9LE-NEXT: xvcvdpsxds v2, vs0 4729; P9LE-NEXT: blr 4730; 4731; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4732; P8BE: # %bb.0: # %entry 4733; P8BE-NEXT: lxvd2x vs0, 0, r3 4734; P8BE-NEXT: xvcvdpsxds v2, vs0 4735; P8BE-NEXT: blr 4736; 4737; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4738; P8LE: # %bb.0: # %entry 4739; P8LE-NEXT: lxvd2x vs0, 0, r3 4740; P8LE-NEXT: xxswapd vs0, vs0 4741; P8LE-NEXT: xvcvdpsxds v2, vs0 4742; P8LE-NEXT: blr 4743entry: 4744 %0 = bitcast double* %ptr to <2 x double>* 4745 %1 = load <2 x double>, <2 x double>* %0, align 8 4746 %2 = fptosi <2 x double> %1 to <2 x i64> 4747 ret <2 x i64> %2 4748} 4749 4750define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4751; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4752; P9BE: # %bb.0: # %entry 4753; P9BE-NEXT: lxv vs0, 16(r3) 4754; P9BE-NEXT: xxswapd vs0, vs0 4755; P9BE-NEXT: xvcvdpsxds v2, vs0 4756; P9BE-NEXT: blr 4757; 4758; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4759; P9LE: # %bb.0: # %entry 4760; P9LE-NEXT: addi r3, r3, 16 4761; P9LE-NEXT: lxvd2x vs0, 0, r3 4762; P9LE-NEXT: xvcvdpsxds v2, vs0 4763; P9LE-NEXT: blr 4764; 4765; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4766; P8BE: # %bb.0: # %entry 4767; P8BE-NEXT: addi r3, r3, 16 4768; P8BE-NEXT: lxvd2x vs0, 0, r3 4769; P8BE-NEXT: xxswapd vs0, vs0 4770; P8BE-NEXT: xvcvdpsxds v2, vs0 4771; P8BE-NEXT: blr 4772; 4773; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4774; P8LE: # %bb.0: # %entry 4775; P8LE-NEXT: addi r3, r3, 16 4776; P8LE-NEXT: lxvd2x vs0, 0, r3 4777; P8LE-NEXT: xvcvdpsxds v2, vs0 4778; P8LE-NEXT: blr 4779entry: 4780 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4781 %0 = load double, double* %arrayidx, align 8 4782 %conv = fptosi double %0 to i64 4783 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4784 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4785 %1 = load double, double* %arrayidx1, align 8 4786 %conv2 = fptosi double %1 to i64 4787 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4788 ret <2 x i64> %vecinit3 4789} 4790 4791define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4792; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4793; P9BE: # %bb.0: # %entry 4794; P9BE-NEXT: sldi r4, r4, 3 4795; P9BE-NEXT: lxvx vs0, r3, r4 4796; P9BE-NEXT: xvcvdpsxds v2, vs0 4797; P9BE-NEXT: blr 4798; 4799; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4800; P9LE: # %bb.0: # %entry 4801; P9LE-NEXT: sldi r4, r4, 3 4802; P9LE-NEXT: lxvx vs0, r3, r4 4803; P9LE-NEXT: xvcvdpsxds v2, vs0 4804; P9LE-NEXT: blr 4805; 4806; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4807; P8BE: # %bb.0: # %entry 4808; P8BE-NEXT: sldi r4, r4, 3 4809; P8BE-NEXT: lxvd2x vs0, r3, r4 4810; P8BE-NEXT: xvcvdpsxds v2, vs0 4811; P8BE-NEXT: blr 4812; 4813; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4814; P8LE: # %bb.0: # %entry 4815; P8LE-NEXT: sldi r4, r4, 3 4816; P8LE-NEXT: lxvd2x vs0, r3, r4 4817; P8LE-NEXT: xxswapd vs0, vs0 4818; P8LE-NEXT: xvcvdpsxds v2, vs0 4819; P8LE-NEXT: blr 4820entry: 4821 %idxprom = sext i32 %elem to i64 4822 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4823 %0 = load double, double* %arrayidx, align 8 4824 %conv = fptosi double %0 to i64 4825 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4826 %add = add nsw i32 %elem, 1 4827 %idxprom1 = sext i32 %add to i64 4828 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4829 %1 = load double, double* %arrayidx2, align 8 4830 %conv3 = fptosi double %1 to i64 4831 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4832 ret <2 x i64> %vecinit4 4833} 4834 4835define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4836; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4837; P9BE: # %bb.0: # %entry 4838; P9BE-NEXT: sldi r4, r4, 3 4839; P9BE-NEXT: add r3, r3, r4 4840; P9BE-NEXT: li r4, -8 4841; P9BE-NEXT: lxvx vs0, r3, r4 4842; P9BE-NEXT: xxswapd vs0, vs0 4843; P9BE-NEXT: xvcvdpsxds v2, vs0 4844; P9BE-NEXT: blr 4845; 4846; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4847; P9LE: # %bb.0: # %entry 4848; P9LE-NEXT: sldi r4, r4, 3 4849; P9LE-NEXT: add r3, r3, r4 4850; P9LE-NEXT: addi r3, r3, -8 4851; P9LE-NEXT: lxvd2x vs0, 0, r3 4852; P9LE-NEXT: xvcvdpsxds v2, vs0 4853; P9LE-NEXT: blr 4854; 4855; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4856; P8BE: # %bb.0: # %entry 4857; P8BE-NEXT: sldi r4, r4, 3 4858; P8BE-NEXT: add r3, r3, r4 4859; P8BE-NEXT: addi r3, r3, -8 4860; P8BE-NEXT: lxvd2x vs0, 0, r3 4861; P8BE-NEXT: xxswapd vs0, vs0 4862; P8BE-NEXT: xvcvdpsxds v2, vs0 4863; P8BE-NEXT: blr 4864; 4865; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4866; P8LE: # %bb.0: # %entry 4867; P8LE-NEXT: sldi r4, r4, 3 4868; P8LE-NEXT: add r3, r3, r4 4869; P8LE-NEXT: addi r3, r3, -8 4870; P8LE-NEXT: lxvd2x vs0, 0, r3 4871; P8LE-NEXT: xvcvdpsxds v2, vs0 4872; P8LE-NEXT: blr 4873entry: 4874 %idxprom = sext i32 %elem to i64 4875 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4876 %0 = load double, double* %arrayidx, align 8 4877 %conv = fptosi double %0 to i64 4878 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4879 %sub = add nsw i32 %elem, -1 4880 %idxprom1 = sext i32 %sub to i64 4881 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4882 %1 = load double, double* %arrayidx2, align 8 4883 %conv3 = fptosi double %1 to i64 4884 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4885 ret <2 x i64> %vecinit4 4886} 4887 4888define <2 x i64> @spltRegValConvdtoll(double %val) { 4889; P9BE-LABEL: spltRegValConvdtoll: 4890; P9BE: # %bb.0: # %entry 4891; P9BE-NEXT: xscvdpsxds f0, f1 4892; P9BE-NEXT: xxspltd v2, vs0, 0 4893; P9BE-NEXT: blr 4894; 4895; P9LE-LABEL: spltRegValConvdtoll: 4896; P9LE: # %bb.0: # %entry 4897; P9LE-NEXT: xscvdpsxds f0, f1 4898; P9LE-NEXT: xxspltd v2, vs0, 0 4899; P9LE-NEXT: blr 4900; 4901; P8BE-LABEL: spltRegValConvdtoll: 4902; P8BE: # %bb.0: # %entry 4903; P8BE-NEXT: xscvdpsxds f0, f1 4904; P8BE-NEXT: xxspltd v2, vs0, 0 4905; P8BE-NEXT: blr 4906; 4907; P8LE-LABEL: spltRegValConvdtoll: 4908; P8LE: # %bb.0: # %entry 4909; P8LE-NEXT: xscvdpsxds f0, f1 4910; P8LE-NEXT: xxspltd v2, vs0, 0 4911; P8LE-NEXT: blr 4912entry: 4913 %conv = fptosi double %val to i64 4914 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4915 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4916 ret <2 x i64> %splat.splat 4917} 4918 4919define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 4920; P9BE-LABEL: spltMemValConvdtoll: 4921; P9BE: # %bb.0: # %entry 4922; P9BE-NEXT: lxvdsx vs0, 0, r3 4923; P9BE-NEXT: xvcvdpsxds v2, vs0 4924; P9BE-NEXT: blr 4925; 4926; P9LE-LABEL: spltMemValConvdtoll: 4927; P9LE: # %bb.0: # %entry 4928; P9LE-NEXT: lxvdsx vs0, 0, r3 4929; P9LE-NEXT: xvcvdpsxds v2, vs0 4930; P9LE-NEXT: blr 4931; 4932; P8BE-LABEL: spltMemValConvdtoll: 4933; P8BE: # %bb.0: # %entry 4934; P8BE-NEXT: lxvdsx vs0, 0, r3 4935; P8BE-NEXT: xvcvdpsxds v2, vs0 4936; P8BE-NEXT: blr 4937; 4938; P8LE-LABEL: spltMemValConvdtoll: 4939; P8LE: # %bb.0: # %entry 4940; P8LE-NEXT: lxvdsx vs0, 0, r3 4941; P8LE-NEXT: xvcvdpsxds v2, vs0 4942; P8LE-NEXT: blr 4943entry: 4944 %0 = load double, double* %ptr, align 8 4945 %conv = fptosi double %0 to i64 4946 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4947 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4948 ret <2 x i64> %splat.splat 4949} 4950 4951define <2 x i64> @allZeroull() { 4952; P9BE-LABEL: allZeroull: 4953; P9BE: # %bb.0: # %entry 4954; P9BE-NEXT: xxlxor v2, v2, v2 4955; P9BE-NEXT: blr 4956; 4957; P9LE-LABEL: allZeroull: 4958; P9LE: # %bb.0: # %entry 4959; P9LE-NEXT: xxlxor v2, v2, v2 4960; P9LE-NEXT: blr 4961; 4962; P8BE-LABEL: allZeroull: 4963; P8BE: # %bb.0: # %entry 4964; P8BE-NEXT: xxlxor v2, v2, v2 4965; P8BE-NEXT: blr 4966; 4967; P8LE-LABEL: allZeroull: 4968; P8LE: # %bb.0: # %entry 4969; P8LE-NEXT: xxlxor v2, v2, v2 4970; P8LE-NEXT: blr 4971entry: 4972 ret <2 x i64> zeroinitializer 4973} 4974 4975define <2 x i64> @spltConst1ull() { 4976; P9BE-LABEL: spltConst1ull: 4977; P9BE: # %bb.0: # %entry 4978; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4979; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4980; P9BE-NEXT: lxv v2, 0(r3) 4981; P9BE-NEXT: blr 4982; 4983; P9LE-LABEL: spltConst1ull: 4984; P9LE: # %bb.0: # %entry 4985; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4986; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4987; P9LE-NEXT: lxv v2, 0(r3) 4988; P9LE-NEXT: blr 4989; 4990; P8BE-LABEL: spltConst1ull: 4991; P8BE: # %bb.0: # %entry 4992; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4993; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4994; P8BE-NEXT: lxvd2x v2, 0, r3 4995; P8BE-NEXT: blr 4996; 4997; P8LE-LABEL: spltConst1ull: 4998; P8LE: # %bb.0: # %entry 4999; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5000; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5001; P8LE-NEXT: lxvd2x vs0, 0, r3 5002; P8LE-NEXT: xxswapd v2, vs0 5003; P8LE-NEXT: blr 5004entry: 5005 ret <2 x i64> <i64 1, i64 1> 5006} 5007 5008define <2 x i64> @spltConst16kull() { 5009; P9BE-LABEL: spltConst16kull: 5010; P9BE: # %bb.0: # %entry 5011; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5012; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5013; P9BE-NEXT: lxv v2, 0(r3) 5014; P9BE-NEXT: blr 5015; 5016; P9LE-LABEL: spltConst16kull: 5017; P9LE: # %bb.0: # %entry 5018; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5019; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5020; P9LE-NEXT: lxv v2, 0(r3) 5021; P9LE-NEXT: blr 5022; 5023; P8BE-LABEL: spltConst16kull: 5024; P8BE: # %bb.0: # %entry 5025; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5026; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5027; P8BE-NEXT: lxvd2x v2, 0, r3 5028; P8BE-NEXT: blr 5029; 5030; P8LE-LABEL: spltConst16kull: 5031; P8LE: # %bb.0: # %entry 5032; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5033; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5034; P8LE-NEXT: lxvd2x vs0, 0, r3 5035; P8LE-NEXT: xxswapd v2, vs0 5036; P8LE-NEXT: blr 5037entry: 5038 ret <2 x i64> <i64 32767, i64 32767> 5039} 5040 5041define <2 x i64> @spltConst32kull() { 5042; P9BE-LABEL: spltConst32kull: 5043; P9BE: # %bb.0: # %entry 5044; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5045; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5046; P9BE-NEXT: lxv v2, 0(r3) 5047; P9BE-NEXT: blr 5048; 5049; P9LE-LABEL: spltConst32kull: 5050; P9LE: # %bb.0: # %entry 5051; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5052; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5053; P9LE-NEXT: lxv v2, 0(r3) 5054; P9LE-NEXT: blr 5055; 5056; P8BE-LABEL: spltConst32kull: 5057; P8BE: # %bb.0: # %entry 5058; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5059; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5060; P8BE-NEXT: lxvd2x v2, 0, r3 5061; P8BE-NEXT: blr 5062; 5063; P8LE-LABEL: spltConst32kull: 5064; P8LE: # %bb.0: # %entry 5065; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5066; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5067; P8LE-NEXT: lxvd2x vs0, 0, r3 5068; P8LE-NEXT: xxswapd v2, vs0 5069; P8LE-NEXT: blr 5070entry: 5071 ret <2 x i64> <i64 65535, i64 65535> 5072} 5073 5074define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5075; P9BE-LABEL: fromRegsull: 5076; P9BE: # %bb.0: # %entry 5077; P9BE-NEXT: mtvsrdd v2, r3, r4 5078; P9BE-NEXT: blr 5079; 5080; P9LE-LABEL: fromRegsull: 5081; P9LE: # %bb.0: # %entry 5082; P9LE-NEXT: mtvsrdd v2, r4, r3 5083; P9LE-NEXT: blr 5084; 5085; P8BE-LABEL: fromRegsull: 5086; P8BE: # %bb.0: # %entry 5087; P8BE-NEXT: mtfprd f0, r4 5088; P8BE-NEXT: mtfprd f1, r3 5089; P8BE-NEXT: xxmrghd v2, vs1, vs0 5090; P8BE-NEXT: blr 5091; 5092; P8LE-LABEL: fromRegsull: 5093; P8LE: # %bb.0: # %entry 5094; P8LE-NEXT: mtfprd f0, r3 5095; P8LE-NEXT: mtfprd f1, r4 5096; P8LE-NEXT: xxmrghd v2, vs1, vs0 5097; P8LE-NEXT: blr 5098entry: 5099 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5100 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5101 ret <2 x i64> %vecinit1 5102} 5103 5104define <2 x i64> @fromDiffConstsull() { 5105; P9BE-LABEL: fromDiffConstsull: 5106; P9BE: # %bb.0: # %entry 5107; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5108; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5109; P9BE-NEXT: lxv v2, 0(r3) 5110; P9BE-NEXT: blr 5111; 5112; P9LE-LABEL: fromDiffConstsull: 5113; P9LE: # %bb.0: # %entry 5114; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5115; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5116; P9LE-NEXT: lxv v2, 0(r3) 5117; P9LE-NEXT: blr 5118; 5119; P8BE-LABEL: fromDiffConstsull: 5120; P8BE: # %bb.0: # %entry 5121; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5122; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5123; P8BE-NEXT: lxvd2x v2, 0, r3 5124; P8BE-NEXT: blr 5125; 5126; P8LE-LABEL: fromDiffConstsull: 5127; P8LE: # %bb.0: # %entry 5128; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5129; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5130; P8LE-NEXT: lxvd2x vs0, 0, r3 5131; P8LE-NEXT: xxswapd v2, vs0 5132; P8LE-NEXT: blr 5133entry: 5134 ret <2 x i64> <i64 242, i64 -113> 5135} 5136 5137define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5138; P9BE-LABEL: fromDiffMemConsAull: 5139; P9BE: # %bb.0: # %entry 5140; P9BE-NEXT: lxv v2, 0(r3) 5141; P9BE-NEXT: blr 5142; 5143; P9LE-LABEL: fromDiffMemConsAull: 5144; P9LE: # %bb.0: # %entry 5145; P9LE-NEXT: lxv v2, 0(r3) 5146; P9LE-NEXT: blr 5147; 5148; P8BE-LABEL: fromDiffMemConsAull: 5149; P8BE: # %bb.0: # %entry 5150; P8BE-NEXT: lxvd2x v2, 0, r3 5151; P8BE-NEXT: blr 5152; 5153; P8LE-LABEL: fromDiffMemConsAull: 5154; P8LE: # %bb.0: # %entry 5155; P8LE-NEXT: lxvd2x vs0, 0, r3 5156; P8LE-NEXT: xxswapd v2, vs0 5157; P8LE-NEXT: blr 5158entry: 5159 %0 = load i64, i64* %arr, align 8 5160 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5161 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5162 %1 = load i64, i64* %arrayidx1, align 8 5163 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5164 ret <2 x i64> %vecinit2 5165} 5166 5167define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5168; P9BE-LABEL: fromDiffMemConsDull: 5169; P9BE: # %bb.0: # %entry 5170; P9BE-NEXT: lxv v2, 16(r3) 5171; P9BE-NEXT: xxswapd v2, v2 5172; P9BE-NEXT: blr 5173; 5174; P9LE-LABEL: fromDiffMemConsDull: 5175; P9LE: # %bb.0: # %entry 5176; P9LE-NEXT: addi r3, r3, 16 5177; P9LE-NEXT: lxvd2x v2, 0, r3 5178; P9LE-NEXT: blr 5179; 5180; P8BE-LABEL: fromDiffMemConsDull: 5181; P8BE: # %bb.0: # %entry 5182; P8BE-NEXT: addi r3, r3, 16 5183; P8BE-NEXT: lxvd2x v2, 0, r3 5184; P8BE-NEXT: xxswapd v2, v2 5185; P8BE-NEXT: blr 5186; 5187; P8LE-LABEL: fromDiffMemConsDull: 5188; P8LE: # %bb.0: # %entry 5189; P8LE-NEXT: addi r3, r3, 16 5190; P8LE-NEXT: lxvd2x v2, 0, r3 5191; P8LE-NEXT: blr 5192entry: 5193 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5194 %0 = load i64, i64* %arrayidx, align 8 5195 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5196 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5197 %1 = load i64, i64* %arrayidx1, align 8 5198 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5199 ret <2 x i64> %vecinit2 5200} 5201 5202define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5203; P9BE-LABEL: fromDiffMemVarAull: 5204; P9BE: # %bb.0: # %entry 5205; P9BE-NEXT: sldi r4, r4, 3 5206; P9BE-NEXT: lxvx v2, r3, r4 5207; P9BE-NEXT: blr 5208; 5209; P9LE-LABEL: fromDiffMemVarAull: 5210; P9LE: # %bb.0: # %entry 5211; P9LE-NEXT: sldi r4, r4, 3 5212; P9LE-NEXT: lxvx v2, r3, r4 5213; P9LE-NEXT: blr 5214; 5215; P8BE-LABEL: fromDiffMemVarAull: 5216; P8BE: # %bb.0: # %entry 5217; P8BE-NEXT: sldi r4, r4, 3 5218; P8BE-NEXT: lxvd2x v2, r3, r4 5219; P8BE-NEXT: blr 5220; 5221; P8LE-LABEL: fromDiffMemVarAull: 5222; P8LE: # %bb.0: # %entry 5223; P8LE-NEXT: sldi r4, r4, 3 5224; P8LE-NEXT: lxvd2x vs0, r3, r4 5225; P8LE-NEXT: xxswapd v2, vs0 5226; P8LE-NEXT: blr 5227entry: 5228 %idxprom = sext i32 %elem to i64 5229 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5230 %0 = load i64, i64* %arrayidx, align 8 5231 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5232 %add = add nsw i32 %elem, 1 5233 %idxprom1 = sext i32 %add to i64 5234 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5235 %1 = load i64, i64* %arrayidx2, align 8 5236 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5237 ret <2 x i64> %vecinit3 5238} 5239 5240define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5241; P9BE-LABEL: fromDiffMemVarDull: 5242; P9BE: # %bb.0: # %entry 5243; P9BE-NEXT: sldi r4, r4, 3 5244; P9BE-NEXT: add r3, r3, r4 5245; P9BE-NEXT: li r4, -8 5246; P9BE-NEXT: lxvx v2, r3, r4 5247; P9BE-NEXT: xxswapd v2, v2 5248; P9BE-NEXT: blr 5249; 5250; P9LE-LABEL: fromDiffMemVarDull: 5251; P9LE: # %bb.0: # %entry 5252; P9LE-NEXT: sldi r4, r4, 3 5253; P9LE-NEXT: add r3, r3, r4 5254; P9LE-NEXT: addi r3, r3, -8 5255; P9LE-NEXT: lxvd2x v2, 0, r3 5256; P9LE-NEXT: blr 5257; 5258; P8BE-LABEL: fromDiffMemVarDull: 5259; P8BE: # %bb.0: # %entry 5260; P8BE-NEXT: sldi r4, r4, 3 5261; P8BE-NEXT: add r3, r3, r4 5262; P8BE-NEXT: addi r3, r3, -8 5263; P8BE-NEXT: lxvd2x v2, 0, r3 5264; P8BE-NEXT: xxswapd v2, v2 5265; P8BE-NEXT: blr 5266; 5267; P8LE-LABEL: fromDiffMemVarDull: 5268; P8LE: # %bb.0: # %entry 5269; P8LE-NEXT: sldi r4, r4, 3 5270; P8LE-NEXT: add r3, r3, r4 5271; P8LE-NEXT: addi r3, r3, -8 5272; P8LE-NEXT: lxvd2x v2, 0, r3 5273; P8LE-NEXT: blr 5274entry: 5275 %idxprom = sext i32 %elem to i64 5276 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5277 %0 = load i64, i64* %arrayidx, align 8 5278 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5279 %sub = add nsw i32 %elem, -1 5280 %idxprom1 = sext i32 %sub to i64 5281 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5282 %1 = load i64, i64* %arrayidx2, align 8 5283 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5284 ret <2 x i64> %vecinit3 5285} 5286 5287define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5288; P9BE-LABEL: fromRandMemConsull: 5289; P9BE: # %bb.0: # %entry 5290; P9BE-NEXT: ld r4, 32(r3) 5291; P9BE-NEXT: ld r3, 144(r3) 5292; P9BE-NEXT: mtvsrdd v2, r4, r3 5293; P9BE-NEXT: blr 5294; 5295; P9LE-LABEL: fromRandMemConsull: 5296; P9LE: # %bb.0: # %entry 5297; P9LE-NEXT: ld r4, 32(r3) 5298; P9LE-NEXT: ld r3, 144(r3) 5299; P9LE-NEXT: mtvsrdd v2, r3, r4 5300; P9LE-NEXT: blr 5301; 5302; P8BE-LABEL: fromRandMemConsull: 5303; P8BE: # %bb.0: # %entry 5304; P8BE-NEXT: ld r4, 144(r3) 5305; P8BE-NEXT: ld r3, 32(r3) 5306; P8BE-NEXT: mtfprd f0, r4 5307; P8BE-NEXT: mtfprd f1, r3 5308; P8BE-NEXT: xxmrghd v2, vs1, vs0 5309; P8BE-NEXT: blr 5310; 5311; P8LE-LABEL: fromRandMemConsull: 5312; P8LE: # %bb.0: # %entry 5313; P8LE-NEXT: ld r4, 32(r3) 5314; P8LE-NEXT: ld r3, 144(r3) 5315; P8LE-NEXT: mtfprd f0, r4 5316; P8LE-NEXT: mtfprd f1, r3 5317; P8LE-NEXT: xxmrghd v2, vs1, vs0 5318; P8LE-NEXT: blr 5319entry: 5320 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5321 %0 = load i64, i64* %arrayidx, align 8 5322 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5323 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5324 %1 = load i64, i64* %arrayidx1, align 8 5325 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5326 ret <2 x i64> %vecinit2 5327} 5328 5329define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5330; P9BE-LABEL: fromRandMemVarull: 5331; P9BE: # %bb.0: # %entry 5332; P9BE-NEXT: sldi r4, r4, 3 5333; P9BE-NEXT: add r3, r3, r4 5334; P9BE-NEXT: ld r4, 32(r3) 5335; P9BE-NEXT: ld r3, 8(r3) 5336; P9BE-NEXT: mtvsrdd v2, r4, r3 5337; P9BE-NEXT: blr 5338; 5339; P9LE-LABEL: fromRandMemVarull: 5340; P9LE: # %bb.0: # %entry 5341; P9LE-NEXT: sldi r4, r4, 3 5342; P9LE-NEXT: add r3, r3, r4 5343; P9LE-NEXT: ld r4, 32(r3) 5344; P9LE-NEXT: ld r3, 8(r3) 5345; P9LE-NEXT: mtvsrdd v2, r3, r4 5346; P9LE-NEXT: blr 5347; 5348; P8BE-LABEL: fromRandMemVarull: 5349; P8BE: # %bb.0: # %entry 5350; P8BE-NEXT: sldi r4, r4, 3 5351; P8BE-NEXT: add r3, r3, r4 5352; P8BE-NEXT: ld r4, 8(r3) 5353; P8BE-NEXT: ld r3, 32(r3) 5354; P8BE-NEXT: mtfprd f0, r4 5355; P8BE-NEXT: mtfprd f1, r3 5356; P8BE-NEXT: xxmrghd v2, vs1, vs0 5357; P8BE-NEXT: blr 5358; 5359; P8LE-LABEL: fromRandMemVarull: 5360; P8LE: # %bb.0: # %entry 5361; P8LE-NEXT: sldi r4, r4, 3 5362; P8LE-NEXT: add r3, r3, r4 5363; P8LE-NEXT: ld r4, 32(r3) 5364; P8LE-NEXT: ld r3, 8(r3) 5365; P8LE-NEXT: mtfprd f0, r4 5366; P8LE-NEXT: mtfprd f1, r3 5367; P8LE-NEXT: xxmrghd v2, vs1, vs0 5368; P8LE-NEXT: blr 5369entry: 5370 %add = add nsw i32 %elem, 4 5371 %idxprom = sext i32 %add to i64 5372 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5373 %0 = load i64, i64* %arrayidx, align 8 5374 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5375 %add1 = add nsw i32 %elem, 1 5376 %idxprom2 = sext i32 %add1 to i64 5377 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5378 %1 = load i64, i64* %arrayidx3, align 8 5379 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5380 ret <2 x i64> %vecinit4 5381} 5382 5383define <2 x i64> @spltRegValull(i64 %val) { 5384; P9BE-LABEL: spltRegValull: 5385; P9BE: # %bb.0: # %entry 5386; P9BE-NEXT: mtvsrdd v2, r3, r3 5387; P9BE-NEXT: blr 5388; 5389; P9LE-LABEL: spltRegValull: 5390; P9LE: # %bb.0: # %entry 5391; P9LE-NEXT: mtvsrdd v2, r3, r3 5392; P9LE-NEXT: blr 5393; 5394; P8BE-LABEL: spltRegValull: 5395; P8BE: # %bb.0: # %entry 5396; P8BE-NEXT: mtfprd f0, r3 5397; P8BE-NEXT: xxspltd v2, vs0, 0 5398; P8BE-NEXT: blr 5399; 5400; P8LE-LABEL: spltRegValull: 5401; P8LE: # %bb.0: # %entry 5402; P8LE-NEXT: mtfprd f0, r3 5403; P8LE-NEXT: xxspltd v2, vs0, 0 5404; P8LE-NEXT: blr 5405entry: 5406 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5407 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5408 ret <2 x i64> %splat.splat 5409} 5410 5411define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5412; P9BE-LABEL: spltMemValull: 5413; P9BE: # %bb.0: # %entry 5414; P9BE-NEXT: lxvdsx v2, 0, r3 5415; P9BE-NEXT: blr 5416; 5417; P9LE-LABEL: spltMemValull: 5418; P9LE: # %bb.0: # %entry 5419; P9LE-NEXT: lxvdsx v2, 0, r3 5420; P9LE-NEXT: blr 5421; 5422; P8BE-LABEL: spltMemValull: 5423; P8BE: # %bb.0: # %entry 5424; P8BE-NEXT: lxvdsx v2, 0, r3 5425; P8BE-NEXT: blr 5426; 5427; P8LE-LABEL: spltMemValull: 5428; P8LE: # %bb.0: # %entry 5429; P8LE-NEXT: lxvdsx v2, 0, r3 5430; P8LE-NEXT: blr 5431entry: 5432 %0 = load i64, i64* %ptr, align 8 5433 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5434 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5435 ret <2 x i64> %splat.splat 5436} 5437 5438define <2 x i64> @spltCnstConvftoull() { 5439; P9BE-LABEL: spltCnstConvftoull: 5440; P9BE: # %bb.0: # %entry 5441; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5442; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5443; P9BE-NEXT: lxv v2, 0(r3) 5444; P9BE-NEXT: blr 5445; 5446; P9LE-LABEL: spltCnstConvftoull: 5447; P9LE: # %bb.0: # %entry 5448; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5449; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5450; P9LE-NEXT: lxv v2, 0(r3) 5451; P9LE-NEXT: blr 5452; 5453; P8BE-LABEL: spltCnstConvftoull: 5454; P8BE: # %bb.0: # %entry 5455; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5456; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5457; P8BE-NEXT: lxvd2x v2, 0, r3 5458; P8BE-NEXT: blr 5459; 5460; P8LE-LABEL: spltCnstConvftoull: 5461; P8LE: # %bb.0: # %entry 5462; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5463; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5464; P8LE-NEXT: lxvd2x vs0, 0, r3 5465; P8LE-NEXT: xxswapd v2, vs0 5466; P8LE-NEXT: blr 5467entry: 5468 ret <2 x i64> <i64 4, i64 4> 5469} 5470 5471define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5472; P9BE-LABEL: fromRegsConvftoull: 5473; P9BE: # %bb.0: # %entry 5474; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5475; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5476; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5477; P9BE-NEXT: xvcvdpuxds v2, vs0 5478; P9BE-NEXT: blr 5479; 5480; P9LE-LABEL: fromRegsConvftoull: 5481; P9LE: # %bb.0: # %entry 5482; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5483; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5484; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5485; P9LE-NEXT: xvcvdpuxds v2, vs0 5486; P9LE-NEXT: blr 5487; 5488; P8BE-LABEL: fromRegsConvftoull: 5489; P8BE: # %bb.0: # %entry 5490; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5491; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5492; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5493; P8BE-NEXT: xvcvdpuxds v2, vs0 5494; P8BE-NEXT: blr 5495; 5496; P8LE-LABEL: fromRegsConvftoull: 5497; P8LE: # %bb.0: # %entry 5498; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5499; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5500; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5501; P8LE-NEXT: xvcvdpuxds v2, vs0 5502; P8LE-NEXT: blr 5503entry: 5504 %conv = fptoui float %a to i64 5505 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5506 %conv1 = fptoui float %b to i64 5507 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5508 ret <2 x i64> %vecinit2 5509} 5510 5511define <2 x i64> @fromDiffConstsConvftoull() { 5512; P9BE-LABEL: fromDiffConstsConvftoull: 5513; P9BE: # %bb.0: # %entry 5514; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5515; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5516; P9BE-NEXT: lxv v2, 0(r3) 5517; P9BE-NEXT: blr 5518; 5519; P9LE-LABEL: fromDiffConstsConvftoull: 5520; P9LE: # %bb.0: # %entry 5521; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5522; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5523; P9LE-NEXT: lxv v2, 0(r3) 5524; P9LE-NEXT: blr 5525; 5526; P8BE-LABEL: fromDiffConstsConvftoull: 5527; P8BE: # %bb.0: # %entry 5528; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5529; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5530; P8BE-NEXT: lxvd2x v2, 0, r3 5531; P8BE-NEXT: blr 5532; 5533; P8LE-LABEL: fromDiffConstsConvftoull: 5534; P8LE: # %bb.0: # %entry 5535; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5536; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5537; P8LE-NEXT: lxvd2x vs0, 0, r3 5538; P8LE-NEXT: xxswapd v2, vs0 5539; P8LE-NEXT: blr 5540entry: 5541 ret <2 x i64> <i64 24, i64 234> 5542} 5543 5544define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5545; P9BE-LABEL: fromDiffMemConsAConvftoull: 5546; P9BE: # %bb.0: # %entry 5547; P9BE-NEXT: lfs f0, 0(r3) 5548; P9BE-NEXT: lfs f1, 4(r3) 5549; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5550; P9BE-NEXT: xvcvdpuxds v2, vs0 5551; P9BE-NEXT: blr 5552; 5553; P9LE-LABEL: fromDiffMemConsAConvftoull: 5554; P9LE: # %bb.0: # %entry 5555; P9LE-NEXT: lfs f0, 0(r3) 5556; P9LE-NEXT: lfs f1, 4(r3) 5557; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5558; P9LE-NEXT: xvcvdpuxds v2, vs0 5559; P9LE-NEXT: blr 5560; 5561; P8BE-LABEL: fromDiffMemConsAConvftoull: 5562; P8BE: # %bb.0: # %entry 5563; P8BE-NEXT: lfs f0, 0(r3) 5564; P8BE-NEXT: lfs f1, 4(r3) 5565; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5566; P8BE-NEXT: xvcvdpuxds v2, vs0 5567; P8BE-NEXT: blr 5568; 5569; P8LE-LABEL: fromDiffMemConsAConvftoull: 5570; P8LE: # %bb.0: # %entry 5571; P8LE-NEXT: lfs f0, 0(r3) 5572; P8LE-NEXT: lfs f1, 4(r3) 5573; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5574; P8LE-NEXT: xvcvdpuxds v2, vs0 5575; P8LE-NEXT: blr 5576entry: 5577 %0 = load float, float* %ptr, align 4 5578 %conv = fptoui float %0 to i64 5579 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5580 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5581 %1 = load float, float* %arrayidx1, align 4 5582 %conv2 = fptoui float %1 to i64 5583 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5584 ret <2 x i64> %vecinit3 5585} 5586 5587define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5588; P9BE-LABEL: fromDiffMemConsDConvftoull: 5589; P9BE: # %bb.0: # %entry 5590; P9BE-NEXT: lfs f0, 12(r3) 5591; P9BE-NEXT: lfs f1, 8(r3) 5592; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5593; P9BE-NEXT: xvcvdpuxds v2, vs0 5594; P9BE-NEXT: blr 5595; 5596; P9LE-LABEL: fromDiffMemConsDConvftoull: 5597; P9LE: # %bb.0: # %entry 5598; P9LE-NEXT: lfs f0, 12(r3) 5599; P9LE-NEXT: lfs f1, 8(r3) 5600; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5601; P9LE-NEXT: xvcvdpuxds v2, vs0 5602; P9LE-NEXT: blr 5603; 5604; P8BE-LABEL: fromDiffMemConsDConvftoull: 5605; P8BE: # %bb.0: # %entry 5606; P8BE-NEXT: lfs f0, 12(r3) 5607; P8BE-NEXT: lfs f1, 8(r3) 5608; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5609; P8BE-NEXT: xvcvdpuxds v2, vs0 5610; P8BE-NEXT: blr 5611; 5612; P8LE-LABEL: fromDiffMemConsDConvftoull: 5613; P8LE: # %bb.0: # %entry 5614; P8LE-NEXT: lfs f0, 12(r3) 5615; P8LE-NEXT: lfs f1, 8(r3) 5616; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5617; P8LE-NEXT: xvcvdpuxds v2, vs0 5618; P8LE-NEXT: blr 5619entry: 5620 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5621 %0 = load float, float* %arrayidx, align 4 5622 %conv = fptoui float %0 to i64 5623 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5624 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5625 %1 = load float, float* %arrayidx1, align 4 5626 %conv2 = fptoui float %1 to i64 5627 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5628 ret <2 x i64> %vecinit3 5629} 5630 5631define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5632; P9BE-LABEL: fromDiffMemVarAConvftoull: 5633; P9BE: # %bb.0: # %entry 5634; P9BE-NEXT: sldi r4, r4, 2 5635; P9BE-NEXT: lfsux f0, r3, r4 5636; P9BE-NEXT: lfs f1, 4(r3) 5637; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5638; P9BE-NEXT: xvcvdpuxds v2, vs0 5639; P9BE-NEXT: blr 5640; 5641; P9LE-LABEL: fromDiffMemVarAConvftoull: 5642; P9LE: # %bb.0: # %entry 5643; P9LE-NEXT: sldi r4, r4, 2 5644; P9LE-NEXT: lfsux f0, r3, r4 5645; P9LE-NEXT: lfs f1, 4(r3) 5646; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5647; P9LE-NEXT: xvcvdpuxds v2, vs0 5648; P9LE-NEXT: blr 5649; 5650; P8BE-LABEL: fromDiffMemVarAConvftoull: 5651; P8BE: # %bb.0: # %entry 5652; P8BE-NEXT: sldi r4, r4, 2 5653; P8BE-NEXT: lfsux f0, r3, r4 5654; P8BE-NEXT: lfs f1, 4(r3) 5655; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5656; P8BE-NEXT: xvcvdpuxds v2, vs0 5657; P8BE-NEXT: blr 5658; 5659; P8LE-LABEL: fromDiffMemVarAConvftoull: 5660; P8LE: # %bb.0: # %entry 5661; P8LE-NEXT: sldi r4, r4, 2 5662; P8LE-NEXT: lfsux f0, r3, r4 5663; P8LE-NEXT: lfs f1, 4(r3) 5664; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5665; P8LE-NEXT: xvcvdpuxds v2, vs0 5666; P8LE-NEXT: blr 5667entry: 5668 %idxprom = sext i32 %elem to i64 5669 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5670 %0 = load float, float* %arrayidx, align 4 5671 %conv = fptoui float %0 to i64 5672 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5673 %add = add nsw i32 %elem, 1 5674 %idxprom1 = sext i32 %add to i64 5675 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5676 %1 = load float, float* %arrayidx2, align 4 5677 %conv3 = fptoui float %1 to i64 5678 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5679 ret <2 x i64> %vecinit4 5680} 5681 5682define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5683; P9BE-LABEL: fromDiffMemVarDConvftoull: 5684; P9BE: # %bb.0: # %entry 5685; P9BE-NEXT: sldi r4, r4, 2 5686; P9BE-NEXT: lfsux f0, r3, r4 5687; P9BE-NEXT: lfs f1, -4(r3) 5688; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5689; P9BE-NEXT: xvcvdpuxds v2, vs0 5690; P9BE-NEXT: blr 5691; 5692; P9LE-LABEL: fromDiffMemVarDConvftoull: 5693; P9LE: # %bb.0: # %entry 5694; P9LE-NEXT: sldi r4, r4, 2 5695; P9LE-NEXT: lfsux f0, r3, r4 5696; P9LE-NEXT: lfs f1, -4(r3) 5697; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5698; P9LE-NEXT: xvcvdpuxds v2, vs0 5699; P9LE-NEXT: blr 5700; 5701; P8BE-LABEL: fromDiffMemVarDConvftoull: 5702; P8BE: # %bb.0: # %entry 5703; P8BE-NEXT: sldi r4, r4, 2 5704; P8BE-NEXT: lfsux f0, r3, r4 5705; P8BE-NEXT: lfs f1, -4(r3) 5706; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5707; P8BE-NEXT: xvcvdpuxds v2, vs0 5708; P8BE-NEXT: blr 5709; 5710; P8LE-LABEL: fromDiffMemVarDConvftoull: 5711; P8LE: # %bb.0: # %entry 5712; P8LE-NEXT: sldi r4, r4, 2 5713; P8LE-NEXT: lfsux f0, r3, r4 5714; P8LE-NEXT: lfs f1, -4(r3) 5715; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5716; P8LE-NEXT: xvcvdpuxds v2, vs0 5717; P8LE-NEXT: blr 5718entry: 5719 %idxprom = sext i32 %elem to i64 5720 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5721 %0 = load float, float* %arrayidx, align 4 5722 %conv = fptoui float %0 to i64 5723 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5724 %sub = add nsw i32 %elem, -1 5725 %idxprom1 = sext i32 %sub to i64 5726 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5727 %1 = load float, float* %arrayidx2, align 4 5728 %conv3 = fptoui float %1 to i64 5729 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5730 ret <2 x i64> %vecinit4 5731} 5732 5733define <2 x i64> @spltRegValConvftoull(float %val) { 5734; P9BE-LABEL: spltRegValConvftoull: 5735; P9BE: # %bb.0: # %entry 5736; P9BE-NEXT: xscvdpuxds f0, f1 5737; P9BE-NEXT: xxspltd v2, f0, 0 5738; P9BE-NEXT: blr 5739; 5740; P9LE-LABEL: spltRegValConvftoull: 5741; P9LE: # %bb.0: # %entry 5742; P9LE-NEXT: xscvdpuxds f0, f1 5743; P9LE-NEXT: xxspltd v2, f0, 0 5744; P9LE-NEXT: blr 5745; 5746; P8BE-LABEL: spltRegValConvftoull: 5747; P8BE: # %bb.0: # %entry 5748; P8BE-NEXT: xscvdpuxds f0, f1 5749; P8BE-NEXT: xxspltd v2, f0, 0 5750; P8BE-NEXT: blr 5751; 5752; P8LE-LABEL: spltRegValConvftoull: 5753; P8LE: # %bb.0: # %entry 5754; P8LE-NEXT: xscvdpuxds f0, f1 5755; P8LE-NEXT: xxspltd v2, f0, 0 5756; P8LE-NEXT: blr 5757entry: 5758 %conv = fptoui float %val to i64 5759 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5760 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5761 ret <2 x i64> %splat.splat 5762} 5763 5764define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5765; P9BE-LABEL: spltMemValConvftoull: 5766; P9BE: # %bb.0: # %entry 5767; P9BE-NEXT: lfs f0, 0(r3) 5768; P9BE-NEXT: xscvdpuxds f0, f0 5769; P9BE-NEXT: xxspltd v2, f0, 0 5770; P9BE-NEXT: blr 5771; 5772; P9LE-LABEL: spltMemValConvftoull: 5773; P9LE: # %bb.0: # %entry 5774; P9LE-NEXT: lfs f0, 0(r3) 5775; P9LE-NEXT: xscvdpuxds f0, f0 5776; P9LE-NEXT: xxspltd v2, vs0, 0 5777; P9LE-NEXT: blr 5778; 5779; P8BE-LABEL: spltMemValConvftoull: 5780; P8BE: # %bb.0: # %entry 5781; P8BE-NEXT: lfsx f0, 0, r3 5782; P8BE-NEXT: xscvdpuxds f0, f0 5783; P8BE-NEXT: xxspltd v2, f0, 0 5784; P8BE-NEXT: blr 5785; 5786; P8LE-LABEL: spltMemValConvftoull: 5787; P8LE: # %bb.0: # %entry 5788; P8LE-NEXT: lfsx f0, 0, r3 5789; P8LE-NEXT: xscvdpuxds f0, f0 5790; P8LE-NEXT: xxspltd v2, vs0, 0 5791; P8LE-NEXT: blr 5792entry: 5793 %0 = load float, float* %ptr, align 4 5794 %conv = fptoui float %0 to i64 5795 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5796 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5797 ret <2 x i64> %splat.splat 5798} 5799 5800define <2 x i64> @spltCnstConvdtoull() { 5801; P9BE-LABEL: spltCnstConvdtoull: 5802; P9BE: # %bb.0: # %entry 5803; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5804; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5805; P9BE-NEXT: lxv v2, 0(r3) 5806; P9BE-NEXT: blr 5807; 5808; P9LE-LABEL: spltCnstConvdtoull: 5809; P9LE: # %bb.0: # %entry 5810; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5811; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5812; P9LE-NEXT: lxv v2, 0(r3) 5813; P9LE-NEXT: blr 5814; 5815; P8BE-LABEL: spltCnstConvdtoull: 5816; P8BE: # %bb.0: # %entry 5817; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5818; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5819; P8BE-NEXT: lxvd2x v2, 0, r3 5820; P8BE-NEXT: blr 5821; 5822; P8LE-LABEL: spltCnstConvdtoull: 5823; P8LE: # %bb.0: # %entry 5824; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5825; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5826; P8LE-NEXT: lxvd2x vs0, 0, r3 5827; P8LE-NEXT: xxswapd v2, vs0 5828; P8LE-NEXT: blr 5829entry: 5830 ret <2 x i64> <i64 4, i64 4> 5831} 5832 5833define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5834; P9BE-LABEL: fromRegsConvdtoull: 5835; P9BE: # %bb.0: # %entry 5836; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5837; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5838; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5839; P9BE-NEXT: xvcvdpuxds v2, vs0 5840; P9BE-NEXT: blr 5841; 5842; P9LE-LABEL: fromRegsConvdtoull: 5843; P9LE: # %bb.0: # %entry 5844; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5845; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5846; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5847; P9LE-NEXT: xvcvdpuxds v2, vs0 5848; P9LE-NEXT: blr 5849; 5850; P8BE-LABEL: fromRegsConvdtoull: 5851; P8BE: # %bb.0: # %entry 5852; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5853; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5854; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5855; P8BE-NEXT: xvcvdpuxds v2, vs0 5856; P8BE-NEXT: blr 5857; 5858; P8LE-LABEL: fromRegsConvdtoull: 5859; P8LE: # %bb.0: # %entry 5860; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5861; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5862; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5863; P8LE-NEXT: xvcvdpuxds v2, vs0 5864; P8LE-NEXT: blr 5865entry: 5866 %conv = fptoui double %a to i64 5867 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5868 %conv1 = fptoui double %b to i64 5869 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5870 ret <2 x i64> %vecinit2 5871} 5872 5873define <2 x i64> @fromDiffConstsConvdtoull() { 5874; P9BE-LABEL: fromDiffConstsConvdtoull: 5875; P9BE: # %bb.0: # %entry 5876; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5877; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5878; P9BE-NEXT: lxv v2, 0(r3) 5879; P9BE-NEXT: blr 5880; 5881; P9LE-LABEL: fromDiffConstsConvdtoull: 5882; P9LE: # %bb.0: # %entry 5883; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5884; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5885; P9LE-NEXT: lxv v2, 0(r3) 5886; P9LE-NEXT: blr 5887; 5888; P8BE-LABEL: fromDiffConstsConvdtoull: 5889; P8BE: # %bb.0: # %entry 5890; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5891; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5892; P8BE-NEXT: lxvd2x v2, 0, r3 5893; P8BE-NEXT: blr 5894; 5895; P8LE-LABEL: fromDiffConstsConvdtoull: 5896; P8LE: # %bb.0: # %entry 5897; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5898; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5899; P8LE-NEXT: lxvd2x vs0, 0, r3 5900; P8LE-NEXT: xxswapd v2, vs0 5901; P8LE-NEXT: blr 5902entry: 5903 ret <2 x i64> <i64 24, i64 234> 5904} 5905 5906define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 5907; P9BE-LABEL: fromDiffMemConsAConvdtoull: 5908; P9BE: # %bb.0: # %entry 5909; P9BE-NEXT: lxv vs0, 0(r3) 5910; P9BE-NEXT: xvcvdpuxds v2, vs0 5911; P9BE-NEXT: blr 5912; 5913; P9LE-LABEL: fromDiffMemConsAConvdtoull: 5914; P9LE: # %bb.0: # %entry 5915; P9LE-NEXT: lxv vs0, 0(r3) 5916; P9LE-NEXT: xvcvdpuxds v2, vs0 5917; P9LE-NEXT: blr 5918; 5919; P8BE-LABEL: fromDiffMemConsAConvdtoull: 5920; P8BE: # %bb.0: # %entry 5921; P8BE-NEXT: lxvd2x vs0, 0, r3 5922; P8BE-NEXT: xvcvdpuxds v2, vs0 5923; P8BE-NEXT: blr 5924; 5925; P8LE-LABEL: fromDiffMemConsAConvdtoull: 5926; P8LE: # %bb.0: # %entry 5927; P8LE-NEXT: lxvd2x vs0, 0, r3 5928; P8LE-NEXT: xxswapd vs0, vs0 5929; P8LE-NEXT: xvcvdpuxds v2, vs0 5930; P8LE-NEXT: blr 5931entry: 5932 %0 = bitcast double* %ptr to <2 x double>* 5933 %1 = load <2 x double>, <2 x double>* %0, align 8 5934 %2 = fptoui <2 x double> %1 to <2 x i64> 5935 ret <2 x i64> %2 5936} 5937 5938define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 5939; P9BE-LABEL: fromDiffMemConsDConvdtoull: 5940; P9BE: # %bb.0: # %entry 5941; P9BE-NEXT: lxv vs0, 16(r3) 5942; P9BE-NEXT: xxswapd vs0, vs0 5943; P9BE-NEXT: xvcvdpuxds v2, vs0 5944; P9BE-NEXT: blr 5945; 5946; P9LE-LABEL: fromDiffMemConsDConvdtoull: 5947; P9LE: # %bb.0: # %entry 5948; P9LE-NEXT: addi r3, r3, 16 5949; P9LE-NEXT: lxvd2x vs0, 0, r3 5950; P9LE-NEXT: xvcvdpuxds v2, vs0 5951; P9LE-NEXT: blr 5952; 5953; P8BE-LABEL: fromDiffMemConsDConvdtoull: 5954; P8BE: # %bb.0: # %entry 5955; P8BE-NEXT: addi r3, r3, 16 5956; P8BE-NEXT: lxvd2x vs0, 0, r3 5957; P8BE-NEXT: xxswapd vs0, vs0 5958; P8BE-NEXT: xvcvdpuxds v2, vs0 5959; P8BE-NEXT: blr 5960; 5961; P8LE-LABEL: fromDiffMemConsDConvdtoull: 5962; P8LE: # %bb.0: # %entry 5963; P8LE-NEXT: addi r3, r3, 16 5964; P8LE-NEXT: lxvd2x vs0, 0, r3 5965; P8LE-NEXT: xvcvdpuxds v2, vs0 5966; P8LE-NEXT: blr 5967entry: 5968 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 5969 %0 = load double, double* %arrayidx, align 8 5970 %conv = fptoui double %0 to i64 5971 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5972 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 5973 %1 = load double, double* %arrayidx1, align 8 5974 %conv2 = fptoui double %1 to i64 5975 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5976 ret <2 x i64> %vecinit3 5977} 5978 5979define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 5980; P9BE-LABEL: fromDiffMemVarAConvdtoull: 5981; P9BE: # %bb.0: # %entry 5982; P9BE-NEXT: sldi r4, r4, 3 5983; P9BE-NEXT: lxvx vs0, r3, r4 5984; P9BE-NEXT: xvcvdpuxds v2, vs0 5985; P9BE-NEXT: blr 5986; 5987; P9LE-LABEL: fromDiffMemVarAConvdtoull: 5988; P9LE: # %bb.0: # %entry 5989; P9LE-NEXT: sldi r4, r4, 3 5990; P9LE-NEXT: lxvx vs0, r3, r4 5991; P9LE-NEXT: xvcvdpuxds v2, vs0 5992; P9LE-NEXT: blr 5993; 5994; P8BE-LABEL: fromDiffMemVarAConvdtoull: 5995; P8BE: # %bb.0: # %entry 5996; P8BE-NEXT: sldi r4, r4, 3 5997; P8BE-NEXT: lxvd2x vs0, r3, r4 5998; P8BE-NEXT: xvcvdpuxds v2, vs0 5999; P8BE-NEXT: blr 6000; 6001; P8LE-LABEL: fromDiffMemVarAConvdtoull: 6002; P8LE: # %bb.0: # %entry 6003; P8LE-NEXT: sldi r4, r4, 3 6004; P8LE-NEXT: lxvd2x vs0, r3, r4 6005; P8LE-NEXT: xxswapd vs0, vs0 6006; P8LE-NEXT: xvcvdpuxds v2, vs0 6007; P8LE-NEXT: blr 6008entry: 6009 %idxprom = sext i32 %elem to i64 6010 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6011 %0 = load double, double* %arrayidx, align 8 6012 %conv = fptoui double %0 to i64 6013 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6014 %add = add nsw i32 %elem, 1 6015 %idxprom1 = sext i32 %add to i64 6016 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6017 %1 = load double, double* %arrayidx2, align 8 6018 %conv3 = fptoui double %1 to i64 6019 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6020 ret <2 x i64> %vecinit4 6021} 6022 6023define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6024; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6025; P9BE: # %bb.0: # %entry 6026; P9BE-NEXT: sldi r4, r4, 3 6027; P9BE-NEXT: add r3, r3, r4 6028; P9BE-NEXT: li r4, -8 6029; P9BE-NEXT: lxvx vs0, r3, r4 6030; P9BE-NEXT: xxswapd vs0, vs0 6031; P9BE-NEXT: xvcvdpuxds v2, vs0 6032; P9BE-NEXT: blr 6033; 6034; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6035; P9LE: # %bb.0: # %entry 6036; P9LE-NEXT: sldi r4, r4, 3 6037; P9LE-NEXT: add r3, r3, r4 6038; P9LE-NEXT: addi r3, r3, -8 6039; P9LE-NEXT: lxvd2x vs0, 0, r3 6040; P9LE-NEXT: xvcvdpuxds v2, vs0 6041; P9LE-NEXT: blr 6042; 6043; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6044; P8BE: # %bb.0: # %entry 6045; P8BE-NEXT: sldi r4, r4, 3 6046; P8BE-NEXT: add r3, r3, r4 6047; P8BE-NEXT: addi r3, r3, -8 6048; P8BE-NEXT: lxvd2x vs0, 0, r3 6049; P8BE-NEXT: xxswapd vs0, vs0 6050; P8BE-NEXT: xvcvdpuxds v2, vs0 6051; P8BE-NEXT: blr 6052; 6053; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6054; P8LE: # %bb.0: # %entry 6055; P8LE-NEXT: sldi r4, r4, 3 6056; P8LE-NEXT: add r3, r3, r4 6057; P8LE-NEXT: addi r3, r3, -8 6058; P8LE-NEXT: lxvd2x vs0, 0, r3 6059; P8LE-NEXT: xvcvdpuxds v2, vs0 6060; P8LE-NEXT: blr 6061entry: 6062 %idxprom = sext i32 %elem to i64 6063 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6064 %0 = load double, double* %arrayidx, align 8 6065 %conv = fptoui double %0 to i64 6066 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6067 %sub = add nsw i32 %elem, -1 6068 %idxprom1 = sext i32 %sub to i64 6069 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6070 %1 = load double, double* %arrayidx2, align 8 6071 %conv3 = fptoui double %1 to i64 6072 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6073 ret <2 x i64> %vecinit4 6074} 6075 6076define <2 x i64> @spltRegValConvdtoull(double %val) { 6077; P9BE-LABEL: spltRegValConvdtoull: 6078; P9BE: # %bb.0: # %entry 6079; P9BE-NEXT: xscvdpuxds f0, f1 6080; P9BE-NEXT: xxspltd v2, vs0, 0 6081; P9BE-NEXT: blr 6082; 6083; P9LE-LABEL: spltRegValConvdtoull: 6084; P9LE: # %bb.0: # %entry 6085; P9LE-NEXT: xscvdpuxds f0, f1 6086; P9LE-NEXT: xxspltd v2, vs0, 0 6087; P9LE-NEXT: blr 6088; 6089; P8BE-LABEL: spltRegValConvdtoull: 6090; P8BE: # %bb.0: # %entry 6091; P8BE-NEXT: xscvdpuxds f0, f1 6092; P8BE-NEXT: xxspltd v2, vs0, 0 6093; P8BE-NEXT: blr 6094; 6095; P8LE-LABEL: spltRegValConvdtoull: 6096; P8LE: # %bb.0: # %entry 6097; P8LE-NEXT: xscvdpuxds f0, f1 6098; P8LE-NEXT: xxspltd v2, vs0, 0 6099; P8LE-NEXT: blr 6100entry: 6101 %conv = fptoui double %val to i64 6102 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6103 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6104 ret <2 x i64> %splat.splat 6105} 6106 6107define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6108; P9BE-LABEL: spltMemValConvdtoull: 6109; P9BE: # %bb.0: # %entry 6110; P9BE-NEXT: lxvdsx vs0, 0, r3 6111; P9BE-NEXT: xvcvdpuxds v2, vs0 6112; P9BE-NEXT: blr 6113; 6114; P9LE-LABEL: spltMemValConvdtoull: 6115; P9LE: # %bb.0: # %entry 6116; P9LE-NEXT: lxvdsx vs0, 0, r3 6117; P9LE-NEXT: xvcvdpuxds v2, vs0 6118; P9LE-NEXT: blr 6119; 6120; P8BE-LABEL: spltMemValConvdtoull: 6121; P8BE: # %bb.0: # %entry 6122; P8BE-NEXT: lxvdsx vs0, 0, r3 6123; P8BE-NEXT: xvcvdpuxds v2, vs0 6124; P8BE-NEXT: blr 6125; 6126; P8LE-LABEL: spltMemValConvdtoull: 6127; P8LE: # %bb.0: # %entry 6128; P8LE-NEXT: lxvdsx vs0, 0, r3 6129; P8LE-NEXT: xvcvdpuxds v2, vs0 6130; P8LE-NEXT: blr 6131entry: 6132 %0 = load double, double* %ptr, align 8 6133 %conv = fptoui double %0 to i64 6134 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6135 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6136 ret <2 x i64> %splat.splat 6137} 6138 6139; Some additional patterns that come up in real code. 6140define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) { 6141; P9BE-LABEL: sint_to_fp_widen02: 6142; P9BE: # %bb.0: # %entry 6143; P9BE-NEXT: xvcvsxwdp v2, v2 6144; P9BE-NEXT: blr 6145; 6146; P9LE-LABEL: sint_to_fp_widen02: 6147; P9LE: # %bb.0: # %entry 6148; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6149; P9LE-NEXT: xvcvsxwdp v2, vs0 6150; P9LE-NEXT: blr 6151; 6152; P8BE-LABEL: sint_to_fp_widen02: 6153; P8BE: # %bb.0: # %entry 6154; P8BE-NEXT: xvcvsxwdp v2, v2 6155; P8BE-NEXT: blr 6156; 6157; P8LE-LABEL: sint_to_fp_widen02: 6158; P8LE: # %bb.0: # %entry 6159; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6160; P8LE-NEXT: xvcvsxwdp v2, vs0 6161; P8LE-NEXT: blr 6162entry: 6163 %vecext = extractelement <4 x i32> %a, i32 0 6164 %conv = sitofp i32 %vecext to double 6165 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6166 %vecext1 = extractelement <4 x i32> %a, i32 2 6167 %conv2 = sitofp i32 %vecext1 to double 6168 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6169 ret <2 x double> %vecinit3 6170} 6171 6172define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) { 6173; P9BE-LABEL: sint_to_fp_widen13: 6174; P9BE: # %bb.0: # %entry 6175; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6176; P9BE-NEXT: xvcvsxwdp v2, vs0 6177; P9BE-NEXT: blr 6178; 6179; P9LE-LABEL: sint_to_fp_widen13: 6180; P9LE: # %bb.0: # %entry 6181; P9LE-NEXT: xvcvsxwdp v2, v2 6182; P9LE-NEXT: blr 6183; 6184; P8BE-LABEL: sint_to_fp_widen13: 6185; P8BE: # %bb.0: # %entry 6186; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6187; P8BE-NEXT: xvcvsxwdp v2, vs0 6188; P8BE-NEXT: blr 6189; 6190; P8LE-LABEL: sint_to_fp_widen13: 6191; P8LE: # %bb.0: # %entry 6192; P8LE-NEXT: xvcvsxwdp v2, v2 6193; P8LE-NEXT: blr 6194entry: 6195 %vecext = extractelement <4 x i32> %a, i32 1 6196 %conv = sitofp i32 %vecext to double 6197 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6198 %vecext1 = extractelement <4 x i32> %a, i32 3 6199 %conv2 = sitofp i32 %vecext1 to double 6200 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6201 ret <2 x double> %vecinit3 6202} 6203 6204define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) { 6205; P9BE-LABEL: uint_to_fp_widen02: 6206; P9BE: # %bb.0: # %entry 6207; P9BE-NEXT: xvcvuxwdp v2, v2 6208; P9BE-NEXT: blr 6209; 6210; P9LE-LABEL: uint_to_fp_widen02: 6211; P9LE: # %bb.0: # %entry 6212; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6213; P9LE-NEXT: xvcvuxwdp v2, vs0 6214; P9LE-NEXT: blr 6215; 6216; P8BE-LABEL: uint_to_fp_widen02: 6217; P8BE: # %bb.0: # %entry 6218; P8BE-NEXT: xvcvuxwdp v2, v2 6219; P8BE-NEXT: blr 6220; 6221; P8LE-LABEL: uint_to_fp_widen02: 6222; P8LE: # %bb.0: # %entry 6223; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6224; P8LE-NEXT: xvcvuxwdp v2, vs0 6225; P8LE-NEXT: blr 6226entry: 6227 %vecext = extractelement <4 x i32> %a, i32 0 6228 %conv = uitofp i32 %vecext to double 6229 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6230 %vecext1 = extractelement <4 x i32> %a, i32 2 6231 %conv2 = uitofp i32 %vecext1 to double 6232 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6233 ret <2 x double> %vecinit3 6234} 6235 6236define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) { 6237; P9BE-LABEL: uint_to_fp_widen13: 6238; P9BE: # %bb.0: # %entry 6239; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6240; P9BE-NEXT: xvcvuxwdp v2, vs0 6241; P9BE-NEXT: blr 6242; 6243; P9LE-LABEL: uint_to_fp_widen13: 6244; P9LE: # %bb.0: # %entry 6245; P9LE-NEXT: xvcvuxwdp v2, v2 6246; P9LE-NEXT: blr 6247; 6248; P8BE-LABEL: uint_to_fp_widen13: 6249; P8BE: # %bb.0: # %entry 6250; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6251; P8BE-NEXT: xvcvuxwdp v2, vs0 6252; P8BE-NEXT: blr 6253; 6254; P8LE-LABEL: uint_to_fp_widen13: 6255; P8LE: # %bb.0: # %entry 6256; P8LE-NEXT: xvcvuxwdp v2, v2 6257; P8LE-NEXT: blr 6258entry: 6259 %vecext = extractelement <4 x i32> %a, i32 1 6260 %conv = uitofp i32 %vecext to double 6261 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6262 %vecext1 = extractelement <4 x i32> %a, i32 3 6263 %conv2 = uitofp i32 %vecext1 to double 6264 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6265 ret <2 x double> %vecinit3 6266} 6267 6268define dso_local <2 x double> @fp_extend01(<4 x float> %a) { 6269; P9BE-LABEL: fp_extend01: 6270; P9BE: # %bb.0: # %entry 6271; P9BE-NEXT: xxmrghw vs0, v2, v2 6272; P9BE-NEXT: xvcvspdp v2, vs0 6273; P9BE-NEXT: blr 6274; 6275; P9LE-LABEL: fp_extend01: 6276; P9LE: # %bb.0: # %entry 6277; P9LE-NEXT: xxmrglw vs0, v2, v2 6278; P9LE-NEXT: xvcvspdp v2, vs0 6279; P9LE-NEXT: blr 6280; 6281; P8BE-LABEL: fp_extend01: 6282; P8BE: # %bb.0: # %entry 6283; P8BE-NEXT: xxmrghw vs0, v2, v2 6284; P8BE-NEXT: xvcvspdp v2, vs0 6285; P8BE-NEXT: blr 6286; 6287; P8LE-LABEL: fp_extend01: 6288; P8LE: # %bb.0: # %entry 6289; P8LE-NEXT: xxmrglw vs0, v2, v2 6290; P8LE-NEXT: xvcvspdp v2, vs0 6291; P8LE-NEXT: blr 6292entry: 6293 %vecext = extractelement <4 x float> %a, i32 0 6294 %conv = fpext float %vecext to double 6295 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6296 %vecext1 = extractelement <4 x float> %a, i32 1 6297 %conv2 = fpext float %vecext1 to double 6298 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6299 ret <2 x double> %vecinit3 6300} 6301 6302define dso_local <2 x double> @fp_extend10(<4 x float> %a) { 6303; P9BE-LABEL: fp_extend10: 6304; P9BE: # %bb.0: # %entry 6305; P9BE-NEXT: xxmrghw vs0, v2, v2 6306; P9BE-NEXT: xvcvspdp vs0, vs0 6307; P9BE-NEXT: xxswapd v2, vs0 6308; P9BE-NEXT: blr 6309; 6310; P9LE-LABEL: fp_extend10: 6311; P9LE: # %bb.0: # %entry 6312; P9LE-NEXT: xxmrglw vs0, v2, v2 6313; P9LE-NEXT: xvcvspdp vs0, vs0 6314; P9LE-NEXT: xxswapd v2, vs0 6315; P9LE-NEXT: blr 6316; 6317; P8BE-LABEL: fp_extend10: 6318; P8BE: # %bb.0: # %entry 6319; P8BE-NEXT: xxmrghw vs0, v2, v2 6320; P8BE-NEXT: xvcvspdp vs0, vs0 6321; P8BE-NEXT: xxswapd v2, vs0 6322; P8BE-NEXT: blr 6323; 6324; P8LE-LABEL: fp_extend10: 6325; P8LE: # %bb.0: # %entry 6326; P8LE-NEXT: xxmrglw vs0, v2, v2 6327; P8LE-NEXT: xvcvspdp vs0, vs0 6328; P8LE-NEXT: xxswapd v2, vs0 6329; P8LE-NEXT: blr 6330entry: 6331 %vecext = extractelement <4 x float> %a, i32 1 6332 %conv = fpext float %vecext to double 6333 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6334 %vecext1 = extractelement <4 x float> %a, i32 0 6335 %conv2 = fpext float %vecext1 to double 6336 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6337 ret <2 x double> %vecinit3 6338} 6339 6340define dso_local <2 x double> @fp_extend02(<4 x float> %a) { 6341; P9BE-LABEL: fp_extend02: 6342; P9BE: # %bb.0: # %entry 6343; P9BE-NEXT: xvcvspdp v2, v2 6344; P9BE-NEXT: blr 6345; 6346; P9LE-LABEL: fp_extend02: 6347; P9LE: # %bb.0: # %entry 6348; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6349; P9LE-NEXT: xvcvspdp v2, vs0 6350; P9LE-NEXT: blr 6351; 6352; P8BE-LABEL: fp_extend02: 6353; P8BE: # %bb.0: # %entry 6354; P8BE-NEXT: xvcvspdp v2, v2 6355; P8BE-NEXT: blr 6356; 6357; P8LE-LABEL: fp_extend02: 6358; P8LE: # %bb.0: # %entry 6359; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6360; P8LE-NEXT: xvcvspdp v2, vs0 6361; P8LE-NEXT: blr 6362entry: 6363 %vecext = extractelement <4 x float> %a, i32 0 6364 %conv = fpext float %vecext to double 6365 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6366 %vecext1 = extractelement <4 x float> %a, i32 2 6367 %conv2 = fpext float %vecext1 to double 6368 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6369 ret <2 x double> %vecinit3 6370} 6371 6372define dso_local <2 x double> @fp_extend13(<4 x float> %a) { 6373; P9BE-LABEL: fp_extend13: 6374; P9BE: # %bb.0: # %entry 6375; P9BE-NEXT: xxsldwi vs0, v2, v2, 3 6376; P9BE-NEXT: xvcvspdp v2, vs0 6377; P9BE-NEXT: blr 6378; 6379; P9LE-LABEL: fp_extend13: 6380; P9LE: # %bb.0: # %entry 6381; P9LE-NEXT: xvcvspdp v2, v2 6382; P9LE-NEXT: blr 6383; 6384; P8BE-LABEL: fp_extend13: 6385; P8BE: # %bb.0: # %entry 6386; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 6387; P8BE-NEXT: xvcvspdp v2, vs0 6388; P8BE-NEXT: blr 6389; 6390; P8LE-LABEL: fp_extend13: 6391; P8LE: # %bb.0: # %entry 6392; P8LE-NEXT: xvcvspdp v2, v2 6393; P8LE-NEXT: blr 6394entry: 6395 %vecext = extractelement <4 x float> %a, i32 1 6396 %conv = fpext float %vecext to double 6397 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6398 %vecext1 = extractelement <4 x float> %a, i32 3 6399 %conv2 = fpext float %vecext1 to double 6400 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6401 ret <2 x double> %vecinit3 6402} 6403 6404define dso_local <2 x double> @fp_extend23(<4 x float> %a) { 6405; P9BE-LABEL: fp_extend23: 6406; P9BE: # %bb.0: # %entry 6407; P9BE-NEXT: xxmrglw vs0, v2, v2 6408; P9BE-NEXT: xvcvspdp v2, vs0 6409; P9BE-NEXT: blr 6410; 6411; P9LE-LABEL: fp_extend23: 6412; P9LE: # %bb.0: # %entry 6413; P9LE-NEXT: xxmrghw vs0, v2, v2 6414; P9LE-NEXT: xvcvspdp v2, vs0 6415; P9LE-NEXT: blr 6416; 6417; P8BE-LABEL: fp_extend23: 6418; P8BE: # %bb.0: # %entry 6419; P8BE-NEXT: xxmrglw vs0, v2, v2 6420; P8BE-NEXT: xvcvspdp v2, vs0 6421; P8BE-NEXT: blr 6422; 6423; P8LE-LABEL: fp_extend23: 6424; P8LE: # %bb.0: # %entry 6425; P8LE-NEXT: xxmrghw vs0, v2, v2 6426; P8LE-NEXT: xvcvspdp v2, vs0 6427; P8LE-NEXT: blr 6428entry: 6429 %vecext = extractelement <4 x float> %a, i32 2 6430 %conv = fpext float %vecext to double 6431 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6432 %vecext1 = extractelement <4 x float> %a, i32 3 6433 %conv2 = fpext float %vecext1 to double 6434 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6435 ret <2 x double> %vecinit3 6436} 6437 6438define dso_local <2 x double> @fp_extend32(<4 x float> %a) { 6439; P9BE-LABEL: fp_extend32: 6440; P9BE: # %bb.0: # %entry 6441; P9BE-NEXT: xxmrglw vs0, v2, v2 6442; P9BE-NEXT: xvcvspdp vs0, vs0 6443; P9BE-NEXT: xxswapd v2, vs0 6444; P9BE-NEXT: blr 6445; 6446; P9LE-LABEL: fp_extend32: 6447; P9LE: # %bb.0: # %entry 6448; P9LE-NEXT: xxmrghw vs0, v2, v2 6449; P9LE-NEXT: xvcvspdp vs0, vs0 6450; P9LE-NEXT: xxswapd v2, vs0 6451; P9LE-NEXT: blr 6452; 6453; P8BE-LABEL: fp_extend32: 6454; P8BE: # %bb.0: # %entry 6455; P8BE-NEXT: xxmrglw vs0, v2, v2 6456; P8BE-NEXT: xvcvspdp vs0, vs0 6457; P8BE-NEXT: xxswapd v2, vs0 6458; P8BE-NEXT: blr 6459; 6460; P8LE-LABEL: fp_extend32: 6461; P8LE: # %bb.0: # %entry 6462; P8LE-NEXT: xxmrghw vs0, v2, v2 6463; P8LE-NEXT: xvcvspdp vs0, vs0 6464; P8LE-NEXT: xxswapd v2, vs0 6465; P8LE-NEXT: blr 6466entry: 6467 %vecext = extractelement <4 x float> %a, i32 3 6468 %conv = fpext float %vecext to double 6469 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6470 %vecext1 = extractelement <4 x float> %a, i32 2 6471 %conv2 = fpext float %vecext1 to double 6472 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6473 ret <2 x double> %vecinit3 6474} 6475 6476define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) { 6477; P9BE-LABEL: fp_extend_two00: 6478; P9BE: # %bb.0: # %entry 6479; P9BE-NEXT: xxmrghd vs0, v2, v3 6480; P9BE-NEXT: xvcvspdp v2, vs0 6481; P9BE-NEXT: blr 6482; 6483; P9LE-LABEL: fp_extend_two00: 6484; P9LE: # %bb.0: # %entry 6485; P9LE-NEXT: xxmrgld vs0, v3, v2 6486; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6487; P9LE-NEXT: xvcvspdp v2, vs0 6488; P9LE-NEXT: blr 6489; 6490; P8BE-LABEL: fp_extend_two00: 6491; P8BE: # %bb.0: # %entry 6492; P8BE-NEXT: xxmrghd vs0, v2, v3 6493; P8BE-NEXT: xvcvspdp v2, vs0 6494; P8BE-NEXT: blr 6495; 6496; P8LE-LABEL: fp_extend_two00: 6497; P8LE: # %bb.0: # %entry 6498; P8LE-NEXT: xxmrgld vs0, v3, v2 6499; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6500; P8LE-NEXT: xvcvspdp v2, vs0 6501; P8LE-NEXT: blr 6502entry: 6503 %vecext = extractelement <4 x float> %a, i32 0 6504 %conv = fpext float %vecext to double 6505 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6506 %vecext1 = extractelement <4 x float> %b, i32 0 6507 %conv2 = fpext float %vecext1 to double 6508 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6509 ret <2 x double> %vecinit3 6510} 6511 6512define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) { 6513; P9BE-LABEL: fp_extend_two33: 6514; P9BE: # %bb.0: # %entry 6515; P9BE-NEXT: xxmrgld vs0, v2, v3 6516; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6517; P9BE-NEXT: xvcvspdp v2, vs0 6518; P9BE-NEXT: blr 6519; 6520; P9LE-LABEL: fp_extend_two33: 6521; P9LE: # %bb.0: # %entry 6522; P9LE-NEXT: xxmrghd vs0, v3, v2 6523; P9LE-NEXT: xvcvspdp v2, vs0 6524; P9LE-NEXT: blr 6525; 6526; P8BE-LABEL: fp_extend_two33: 6527; P8BE: # %bb.0: # %entry 6528; P8BE-NEXT: xxmrgld vs0, v2, v3 6529; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6530; P8BE-NEXT: xvcvspdp v2, vs0 6531; P8BE-NEXT: blr 6532; 6533; P8LE-LABEL: fp_extend_two33: 6534; P8LE: # %bb.0: # %entry 6535; P8LE-NEXT: xxmrghd vs0, v3, v2 6536; P8LE-NEXT: xvcvspdp v2, vs0 6537; P8LE-NEXT: blr 6538entry: 6539 %vecext = extractelement <4 x float> %a, i32 3 6540 %conv = fpext float %vecext to double 6541 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6542 %vecext1 = extractelement <4 x float> %b, i32 3 6543 %conv2 = fpext float %vecext1 to double 6544 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6545 ret <2 x double> %vecinit3 6546} 6547 6548define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr { 6549; P9BE-LABEL: test_xvcvspsxds13: 6550; P9BE: # %bb.0: # %entry 6551; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6552; P9BE-NEXT: xvcvspsxds v2, vs0 6553; P9BE-NEXT: blr 6554; 6555; P9LE-LABEL: test_xvcvspsxds13: 6556; P9LE: # %bb.0: # %entry 6557; P9LE-NEXT: xvcvspsxds v2, v2 6558; P9LE-NEXT: blr 6559; 6560; P8BE-LABEL: test_xvcvspsxds13: 6561; P8BE: # %bb.0: # %entry 6562; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6563; P8BE-NEXT: xvcvspsxds v2, vs0 6564; P8BE-NEXT: blr 6565; 6566; P8LE-LABEL: test_xvcvspsxds13: 6567; P8LE: # %bb.0: # %entry 6568; P8LE-NEXT: xvcvspsxds v2, v2 6569; P8LE-NEXT: blr 6570entry: 6571 %vecext = extractelement <4 x float> %a, i32 1 6572 %conv = fptosi float %vecext to i64 6573 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6574 %vecext1 = extractelement <4 x float> %a, i32 3 6575 %conv2 = fptosi float %vecext1 to i64 6576 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6577 ret <2 x i64> %vecinit3 6578} 6579 6580define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr { 6581; P9BE-LABEL: test_xvcvspuxds13: 6582; P9BE: # %bb.0: # %entry 6583; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6584; P9BE-NEXT: xvcvspuxds v2, vs0 6585; P9BE-NEXT: blr 6586; 6587; P9LE-LABEL: test_xvcvspuxds13: 6588; P9LE: # %bb.0: # %entry 6589; P9LE-NEXT: xvcvspuxds v2, v2 6590; P9LE-NEXT: blr 6591; 6592; P8BE-LABEL: test_xvcvspuxds13: 6593; P8BE: # %bb.0: # %entry 6594; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6595; P8BE-NEXT: xvcvspuxds v2, vs0 6596; P8BE-NEXT: blr 6597; 6598; P8LE-LABEL: test_xvcvspuxds13: 6599; P8LE: # %bb.0: # %entry 6600; P8LE-NEXT: xvcvspuxds v2, v2 6601; P8LE-NEXT: blr 6602entry: 6603 %vecext = extractelement <4 x float> %a, i32 1 6604 %conv = fptoui float %vecext to i64 6605 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6606 %vecext1 = extractelement <4 x float> %a, i32 3 6607 %conv2 = fptoui float %vecext1 to i64 6608 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6609 ret <2 x i64> %vecinit3 6610} 6611 6612define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr { 6613; P9BE-LABEL: test_xvcvspsxds02: 6614; P9BE: # %bb.0: # %entry 6615; P9BE-NEXT: xvcvspsxds v2, v2 6616; P9BE-NEXT: blr 6617; 6618; P9LE-LABEL: test_xvcvspsxds02: 6619; P9LE: # %bb.0: # %entry 6620; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6621; P9LE-NEXT: xvcvspsxds v2, vs0 6622; P9LE-NEXT: blr 6623; 6624; P8BE-LABEL: test_xvcvspsxds02: 6625; P8BE: # %bb.0: # %entry 6626; P8BE-NEXT: xvcvspsxds v2, v2 6627; P8BE-NEXT: blr 6628; 6629; P8LE-LABEL: test_xvcvspsxds02: 6630; P8LE: # %bb.0: # %entry 6631; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6632; P8LE-NEXT: xvcvspsxds v2, vs0 6633; P8LE-NEXT: blr 6634entry: 6635 %vecext = extractelement <4 x float> %a, i32 0 6636 %conv = fptosi float %vecext to i64 6637 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6638 %vecext1 = extractelement <4 x float> %a, i32 2 6639 %conv2 = fptosi float %vecext1 to i64 6640 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6641 ret <2 x i64> %vecinit3 6642} 6643 6644define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr { 6645; P9BE-LABEL: test_xvcvspuxds02: 6646; P9BE: # %bb.0: # %entry 6647; P9BE-NEXT: xvcvspuxds v2, v2 6648; P9BE-NEXT: blr 6649; 6650; P9LE-LABEL: test_xvcvspuxds02: 6651; P9LE: # %bb.0: # %entry 6652; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6653; P9LE-NEXT: xvcvspuxds v2, vs0 6654; P9LE-NEXT: blr 6655; 6656; P8BE-LABEL: test_xvcvspuxds02: 6657; P8BE: # %bb.0: # %entry 6658; P8BE-NEXT: xvcvspuxds v2, v2 6659; P8BE-NEXT: blr 6660; 6661; P8LE-LABEL: test_xvcvspuxds02: 6662; P8LE: # %bb.0: # %entry 6663; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6664; P8LE-NEXT: xvcvspuxds v2, vs0 6665; P8LE-NEXT: blr 6666entry: 6667 %vecext = extractelement <4 x float> %a, i32 0 6668 %conv = fptoui float %vecext to i64 6669 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6670 %vecext1 = extractelement <4 x float> %a, i32 2 6671 %conv2 = fptoui float %vecext1 to i64 6672 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6673 ret <2 x i64> %vecinit3 6674} 6675