xref: /llvm-project/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll (revision afd9582b36ba87b48730f95ab42b79d07c29235e)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-BE %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-BE %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-LE %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-LE %s
6
7define  <2 x i64> @build_v2i64_extload_0(ptr nocapture noundef readonly %p) {
8; PWR7-BE-LABEL: build_v2i64_extload_0:
9; PWR7-BE:       # %bb.0: # %entry
10; PWR7-BE-NEXT:    lwz 3, 0(3)
11; PWR7-BE-NEXT:    li 4, 0
12; PWR7-BE-NEXT:    std 4, -8(1)
13; PWR7-BE-NEXT:    std 3, -16(1)
14; PWR7-BE-NEXT:    addi 3, 1, -16
15; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
16; PWR7-BE-NEXT:    blr
17;
18; PWR8-BE-LABEL: build_v2i64_extload_0:
19; PWR8-BE:       # %bb.0: # %entry
20; PWR8-BE-NEXT:    lwz 3, 0(3)
21; PWR8-BE-NEXT:    li 4, 0
22; PWR8-BE-NEXT:    mtfprd 0, 4
23; PWR8-BE-NEXT:    mtfprd 1, 3
24; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
25; PWR8-BE-NEXT:    blr
26;
27; PWR7-LE-LABEL: build_v2i64_extload_0:
28; PWR7-LE:       # %bb.0: # %entry
29; PWR7-LE-NEXT:    li 4, 0
30; PWR7-LE-NEXT:    lwz 3, 0(3)
31; PWR7-LE-NEXT:    stw 4, -16(1)
32; PWR7-LE-NEXT:    addis 4, 2, .LCPI0_0@toc@ha
33; PWR7-LE-NEXT:    addi 4, 4, .LCPI0_0@toc@l
34; PWR7-LE-NEXT:    stw 3, -32(1)
35; PWR7-LE-NEXT:    addi 3, 1, -32
36; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
37; PWR7-LE-NEXT:    addi 4, 1, -16
38; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
39; PWR7-LE-NEXT:    xxswapd 34, 0
40; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
41; PWR7-LE-NEXT:    xxswapd 35, 1
42; PWR7-LE-NEXT:    xxswapd 36, 0
43; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
44; PWR7-LE-NEXT:    blr
45;
46; PWR8-LE-LABEL: build_v2i64_extload_0:
47; PWR8-LE:       # %bb.0: # %entry
48; PWR8-LE-NEXT:    lwz 3, 0(3)
49; PWR8-LE-NEXT:    li 4, 0
50; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
51; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
52; PWR8-LE-NEXT:    mtfprd 0, 3
53; PWR8-LE-NEXT:    mtfprd 1, 4
54; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
55; PWR8-LE-NEXT:    blr
56entry:
57  %0 = load i32, ptr %p, align 4
58  %conv = zext i32 %0 to i64
59  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 0
60  ret <2 x i64> %vecinit1
61}
62
63define  <2 x i64> @build_v2i64_extload_1(ptr nocapture noundef readonly %p) {
64; PWR7-BE-LABEL: build_v2i64_extload_1:
65; PWR7-BE:       # %bb.0: # %entry
66; PWR7-BE-NEXT:    lwz 3, 0(3)
67; PWR7-BE-NEXT:    li 4, 0
68; PWR7-BE-NEXT:    std 4, -16(1)
69; PWR7-BE-NEXT:    std 3, -8(1)
70; PWR7-BE-NEXT:    addi 3, 1, -16
71; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
72; PWR7-BE-NEXT:    blr
73;
74; PWR8-BE-LABEL: build_v2i64_extload_1:
75; PWR8-BE:       # %bb.0: # %entry
76; PWR8-BE-NEXT:    lwz 3, 0(3)
77; PWR8-BE-NEXT:    li 4, 0
78; PWR8-BE-NEXT:    mtfprd 0, 4
79; PWR8-BE-NEXT:    mtfprd 1, 3
80; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
81; PWR8-BE-NEXT:    blr
82;
83; PWR7-LE-LABEL: build_v2i64_extload_1:
84; PWR7-LE:       # %bb.0: # %entry
85; PWR7-LE-NEXT:    lwz 3, 0(3)
86; PWR7-LE-NEXT:    li 4, 0
87; PWR7-LE-NEXT:    std 4, -16(1)
88; PWR7-LE-NEXT:    std 3, -8(1)
89; PWR7-LE-NEXT:    addi 3, 1, -16
90; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
91; PWR7-LE-NEXT:    xxswapd 34, 0
92; PWR7-LE-NEXT:    blr
93;
94; PWR8-LE-LABEL: build_v2i64_extload_1:
95; PWR8-LE:       # %bb.0: # %entry
96; PWR8-LE-NEXT:    lwz 3, 0(3)
97; PWR8-LE-NEXT:    li 4, 0
98; PWR8-LE-NEXT:    mtfprd 0, 4
99; PWR8-LE-NEXT:    mtfprd 1, 3
100; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
101; PWR8-LE-NEXT:    blr
102entry:
103  %0 = load i32, ptr %p, align 4
104  %conv = zext i32 %0 to i64
105  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 1
106  ret <2 x i64> %vecinit1
107}
108
109define <2 x double> @build_v2f64_extload_0(ptr nocapture noundef readonly %p) {
110; PWR7-BE-LABEL: build_v2f64_extload_0:
111; PWR7-BE:       # %bb.0: # %entry
112; PWR7-BE-NEXT:    lfs 0, 0(3)
113; PWR7-BE-NEXT:    xxlxor 1, 1, 1
114; PWR7-BE-NEXT:    xxmrghd 34, 0, 1
115; PWR7-BE-NEXT:    blr
116;
117; PWR8-BE-LABEL: build_v2f64_extload_0:
118; PWR8-BE:       # %bb.0: # %entry
119; PWR8-BE-NEXT:    lfs 0, 0(3)
120; PWR8-BE-NEXT:    xxlxor 1, 1, 1
121; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
122; PWR8-BE-NEXT:    blr
123;
124; PWR7-LE-LABEL: build_v2f64_extload_0:
125; PWR7-LE:       # %bb.0: # %entry
126; PWR7-LE-NEXT:    lfs 0, 0(3)
127; PWR7-LE-NEXT:    xxlxor 1, 1, 1
128; PWR7-LE-NEXT:    xxmrghd 34, 1, 0
129; PWR7-LE-NEXT:    blr
130;
131; PWR8-LE-LABEL: build_v2f64_extload_0:
132; PWR8-LE:       # %bb.0: # %entry
133; PWR8-LE-NEXT:    lfs 0, 0(3)
134; PWR8-LE-NEXT:    xxlxor 1, 1, 1
135; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
136; PWR8-LE-NEXT:    blr
137entry:
138  %0 = load float, ptr %p, align 4
139  %conv = fpext float %0 to double
140  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 0
141  ret <2 x double> %vecinit1
142}
143
144define <2 x double> @build_v2f64_extload_1(ptr nocapture noundef readonly %p) {
145; PWR7-BE-LABEL: build_v2f64_extload_1:
146; PWR7-BE:       # %bb.0: # %entry
147; PWR7-BE-NEXT:    lfs 0, 0(3)
148; PWR7-BE-NEXT:    xxlxor 1, 1, 1
149; PWR7-BE-NEXT:    xxmrghd 34, 1, 0
150; PWR7-BE-NEXT:    blr
151;
152; PWR8-BE-LABEL: build_v2f64_extload_1:
153; PWR8-BE:       # %bb.0: # %entry
154; PWR8-BE-NEXT:    lfs 0, 0(3)
155; PWR8-BE-NEXT:    xxlxor 1, 1, 1
156; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
157; PWR8-BE-NEXT:    blr
158;
159; PWR7-LE-LABEL: build_v2f64_extload_1:
160; PWR7-LE:       # %bb.0: # %entry
161; PWR7-LE-NEXT:    lfs 0, 0(3)
162; PWR7-LE-NEXT:    xxlxor 1, 1, 1
163; PWR7-LE-NEXT:    xxmrghd 34, 0, 1
164; PWR7-LE-NEXT:    blr
165;
166; PWR8-LE-LABEL: build_v2f64_extload_1:
167; PWR8-LE:       # %bb.0: # %entry
168; PWR8-LE-NEXT:    lfs 0, 0(3)
169; PWR8-LE-NEXT:    xxlxor 1, 1, 1
170; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
171; PWR8-LE-NEXT:    blr
172entry:
173  %0 = load float, ptr %p, align 4
174  %conv = fpext float %0 to double
175  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 1
176  ret <2 x double> %vecinit1
177}
178
179define <2 x double> @build_v2f64_load_0(ptr nocapture noundef readonly %p) {
180; PWR7-BE-LABEL: build_v2f64_load_0:
181; PWR7-BE:       # %bb.0: # %entry
182; PWR7-BE-NEXT:    lfd 0, 0(3)
183; PWR7-BE-NEXT:    xxlxor 1, 1, 1
184; PWR7-BE-NEXT:    xxmrghd 34, 0, 1
185; PWR7-BE-NEXT:    blr
186;
187; PWR8-BE-LABEL: build_v2f64_load_0:
188; PWR8-BE:       # %bb.0: # %entry
189; PWR8-BE-NEXT:    lfd 0, 0(3)
190; PWR8-BE-NEXT:    xxlxor 1, 1, 1
191; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
192; PWR8-BE-NEXT:    blr
193;
194; PWR7-LE-LABEL: build_v2f64_load_0:
195; PWR7-LE:       # %bb.0: # %entry
196; PWR7-LE-NEXT:    lfd 0, 0(3)
197; PWR7-LE-NEXT:    xxlxor 1, 1, 1
198; PWR7-LE-NEXT:    xxmrghd 34, 1, 0
199; PWR7-LE-NEXT:    blr
200;
201; PWR8-LE-LABEL: build_v2f64_load_0:
202; PWR8-LE:       # %bb.0: # %entry
203; PWR8-LE-NEXT:    lfd 0, 0(3)
204; PWR8-LE-NEXT:    xxlxor 1, 1, 1
205; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
206; PWR8-LE-NEXT:    blr
207entry:
208  %0 = load double, ptr %p, align 8
209  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 0
210  ret <2 x double> %vecinit1
211}
212
213define <2 x double> @build_v2f64_load_1(ptr nocapture noundef readonly %p) {
214; PWR7-BE-LABEL: build_v2f64_load_1:
215; PWR7-BE:       # %bb.0: # %entry
216; PWR7-BE-NEXT:    lfd 0, 0(3)
217; PWR7-BE-NEXT:    xxlxor 1, 1, 1
218; PWR7-BE-NEXT:    xxmrghd 34, 1, 0
219; PWR7-BE-NEXT:    blr
220;
221; PWR8-BE-LABEL: build_v2f64_load_1:
222; PWR8-BE:       # %bb.0: # %entry
223; PWR8-BE-NEXT:    lfd 0, 0(3)
224; PWR8-BE-NEXT:    xxlxor 1, 1, 1
225; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
226; PWR8-BE-NEXT:    blr
227;
228; PWR7-LE-LABEL: build_v2f64_load_1:
229; PWR7-LE:       # %bb.0: # %entry
230; PWR7-LE-NEXT:    lfd 0, 0(3)
231; PWR7-LE-NEXT:    xxlxor 1, 1, 1
232; PWR7-LE-NEXT:    xxmrghd 34, 0, 1
233; PWR7-LE-NEXT:    blr
234;
235; PWR8-LE-LABEL: build_v2f64_load_1:
236; PWR8-LE:       # %bb.0: # %entry
237; PWR8-LE-NEXT:    lfd 0, 0(3)
238; PWR8-LE-NEXT:    xxlxor 1, 1, 1
239; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
240; PWR8-LE-NEXT:    blr
241entry:
242  %0 = load double, ptr %p, align 8
243  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 1
244  ret <2 x double> %vecinit1
245}
246
247define <2 x i64> @build_v2i64_load_0(ptr nocapture noundef readonly %p) {
248; PWR7-BE-LABEL: build_v2i64_load_0:
249; PWR7-BE:       # %bb.0: # %entry
250; PWR7-BE-NEXT:    ld 3, 0(3)
251; PWR7-BE-NEXT:    li 4, 0
252; PWR7-BE-NEXT:    std 4, -8(1)
253; PWR7-BE-NEXT:    std 3, -16(1)
254; PWR7-BE-NEXT:    addi 3, 1, -16
255; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
256; PWR7-BE-NEXT:    blr
257;
258; PWR8-BE-LABEL: build_v2i64_load_0:
259; PWR8-BE:       # %bb.0: # %entry
260; PWR8-BE-NEXT:    ld 3, 0(3)
261; PWR8-BE-NEXT:    li 4, 0
262; PWR8-BE-NEXT:    mtfprd 0, 4
263; PWR8-BE-NEXT:    mtfprd 1, 3
264; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
265; PWR8-BE-NEXT:    blr
266;
267; PWR7-LE-LABEL: build_v2i64_load_0:
268; PWR7-LE:       # %bb.0: # %entry
269; PWR7-LE-NEXT:    ld 3, 0(3)
270; PWR7-LE-NEXT:    li 4, 0
271; PWR7-LE-NEXT:    std 4, -8(1)
272; PWR7-LE-NEXT:    std 3, -16(1)
273; PWR7-LE-NEXT:    addi 3, 1, -16
274; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
275; PWR7-LE-NEXT:    xxswapd 34, 0
276; PWR7-LE-NEXT:    blr
277;
278; PWR8-LE-LABEL: build_v2i64_load_0:
279; PWR8-LE:       # %bb.0: # %entry
280; PWR8-LE-NEXT:    ld 3, 0(3)
281; PWR8-LE-NEXT:    li 4, 0
282; PWR8-LE-NEXT:    mtfprd 0, 4
283; PWR8-LE-NEXT:    mtfprd 1, 3
284; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
285; PWR8-LE-NEXT:    blr
286entry:
287  %0 = load i64, ptr %p, align 8
288  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 0
289  ret <2 x i64> %vecinit1
290}
291
292define <2 x i64> @build_v2i64_load_1(ptr nocapture noundef readonly %p) {
293; PWR7-BE-LABEL: build_v2i64_load_1:
294; PWR7-BE:       # %bb.0: # %entry
295; PWR7-BE-NEXT:    ld 3, 0(3)
296; PWR7-BE-NEXT:    li 4, 0
297; PWR7-BE-NEXT:    std 4, -16(1)
298; PWR7-BE-NEXT:    std 3, -8(1)
299; PWR7-BE-NEXT:    addi 3, 1, -16
300; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
301; PWR7-BE-NEXT:    blr
302;
303; PWR8-BE-LABEL: build_v2i64_load_1:
304; PWR8-BE:       # %bb.0: # %entry
305; PWR8-BE-NEXT:    ld 3, 0(3)
306; PWR8-BE-NEXT:    li 4, 0
307; PWR8-BE-NEXT:    mtfprd 0, 4
308; PWR8-BE-NEXT:    mtfprd 1, 3
309; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
310; PWR8-BE-NEXT:    blr
311;
312; PWR7-LE-LABEL: build_v2i64_load_1:
313; PWR7-LE:       # %bb.0: # %entry
314; PWR7-LE-NEXT:    ld 3, 0(3)
315; PWR7-LE-NEXT:    li 4, 0
316; PWR7-LE-NEXT:    std 4, -16(1)
317; PWR7-LE-NEXT:    std 3, -8(1)
318; PWR7-LE-NEXT:    addi 3, 1, -16
319; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
320; PWR7-LE-NEXT:    xxswapd 34, 0
321; PWR7-LE-NEXT:    blr
322;
323; PWR8-LE-LABEL: build_v2i64_load_1:
324; PWR8-LE:       # %bb.0: # %entry
325; PWR8-LE-NEXT:    ld 3, 0(3)
326; PWR8-LE-NEXT:    li 4, 0
327; PWR8-LE-NEXT:    mtfprd 0, 4
328; PWR8-LE-NEXT:    mtfprd 1, 3
329; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
330; PWR8-LE-NEXT:    blr
331entry:
332  %0 = load i64, ptr %p, align 8
333  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 1
334  ret <2 x i64> %vecinit1
335}
336
337define <4 x i32> @build_v4i32_load_0(ptr nocapture noundef readonly %p) {
338; PWR7-BE-LABEL: build_v4i32_load_0:
339; PWR7-BE:       # %bb.0: # %entry
340; PWR7-BE-NEXT:    lwz 3, 0(3)
341; PWR7-BE-NEXT:    li 4, 0
342; PWR7-BE-NEXT:    stw 4, -16(1)
343; PWR7-BE-NEXT:    stw 3, -32(1)
344; PWR7-BE-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
345; PWR7-BE-NEXT:    addi 3, 3, .LCPI8_0@toc@l
346; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
347; PWR7-BE-NEXT:    addi 3, 1, -16
348; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
349; PWR7-BE-NEXT:    addi 3, 1, -32
350; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
351; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
352; PWR7-BE-NEXT:    blr
353;
354; PWR8-BE-LABEL: build_v4i32_load_0:
355; PWR8-BE:       # %bb.0: # %entry
356; PWR8-BE-NEXT:    lwz 3, 0(3)
357; PWR8-BE-NEXT:    li 4, 0
358; PWR8-BE-NEXT:    li 5, 0
359; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
360; PWR8-BE-NEXT:    rldimi 5, 3, 32, 0
361; PWR8-BE-NEXT:    mtfprd 1, 4
362; PWR8-BE-NEXT:    mtfprd 0, 5
363; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
364; PWR8-BE-NEXT:    blr
365;
366; PWR7-LE-LABEL: build_v4i32_load_0:
367; PWR7-LE:       # %bb.0: # %entry
368; PWR7-LE-NEXT:    li 4, 0
369; PWR7-LE-NEXT:    lwz 3, 0(3)
370; PWR7-LE-NEXT:    stw 4, -16(1)
371; PWR7-LE-NEXT:    addis 4, 2, .LCPI8_0@toc@ha
372; PWR7-LE-NEXT:    addi 4, 4, .LCPI8_0@toc@l
373; PWR7-LE-NEXT:    stw 3, -32(1)
374; PWR7-LE-NEXT:    addi 3, 1, -32
375; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
376; PWR7-LE-NEXT:    addi 4, 1, -16
377; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
378; PWR7-LE-NEXT:    xxswapd 34, 0
379; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
380; PWR7-LE-NEXT:    xxswapd 35, 1
381; PWR7-LE-NEXT:    xxswapd 36, 0
382; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
383; PWR7-LE-NEXT:    blr
384;
385; PWR8-LE-LABEL: build_v4i32_load_0:
386; PWR8-LE:       # %bb.0: # %entry
387; PWR8-LE-NEXT:    lwz 3, 0(3)
388; PWR8-LE-NEXT:    li 4, 0
389; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
390; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
391; PWR8-LE-NEXT:    mtfprd 0, 3
392; PWR8-LE-NEXT:    mtfprd 1, 4
393; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
394; PWR8-LE-NEXT:    blr
395entry:
396  %0 = load i32, ptr %p, align 4
397  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 0
398  ret <4 x i32> %vecinit1
399}
400
401define <4 x i32> @build_v4i32_load_1(ptr nocapture noundef readonly %p) {
402; PWR7-BE-LABEL: build_v4i32_load_1:
403; PWR7-BE:       # %bb.0: # %entry
404; PWR7-BE-NEXT:    lwz 3, 0(3)
405; PWR7-BE-NEXT:    li 4, 0
406; PWR7-BE-NEXT:    stw 4, -32(1)
407; PWR7-BE-NEXT:    stw 3, -16(1)
408; PWR7-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
409; PWR7-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
410; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
411; PWR7-BE-NEXT:    addi 3, 1, -32
412; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
413; PWR7-BE-NEXT:    addi 3, 1, -16
414; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
415; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
416; PWR7-BE-NEXT:    blr
417;
418; PWR8-BE-LABEL: build_v4i32_load_1:
419; PWR8-BE:       # %bb.0: # %entry
420; PWR8-BE-NEXT:    lwz 3, 0(3)
421; PWR8-BE-NEXT:    li 4, 0
422; PWR8-BE-NEXT:    rldimi 3, 4, 32, 0
423; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
424; PWR8-BE-NEXT:    mtfprd 0, 3
425; PWR8-BE-NEXT:    mtfprd 1, 4
426; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
427; PWR8-BE-NEXT:    blr
428;
429; PWR7-LE-LABEL: build_v4i32_load_1:
430; PWR7-LE:       # %bb.0: # %entry
431; PWR7-LE-NEXT:    li 4, 0
432; PWR7-LE-NEXT:    lwz 3, 0(3)
433; PWR7-LE-NEXT:    stw 4, -32(1)
434; PWR7-LE-NEXT:    addis 4, 2, .LCPI9_0@toc@ha
435; PWR7-LE-NEXT:    addi 4, 4, .LCPI9_0@toc@l
436; PWR7-LE-NEXT:    stw 3, -16(1)
437; PWR7-LE-NEXT:    addi 3, 1, -16
438; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
439; PWR7-LE-NEXT:    addi 4, 1, -32
440; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
441; PWR7-LE-NEXT:    xxswapd 34, 0
442; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
443; PWR7-LE-NEXT:    xxswapd 35, 1
444; PWR7-LE-NEXT:    xxswapd 36, 0
445; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
446; PWR7-LE-NEXT:    blr
447;
448; PWR8-LE-LABEL: build_v4i32_load_1:
449; PWR8-LE:       # %bb.0: # %entry
450; PWR8-LE-NEXT:    lwz 3, 0(3)
451; PWR8-LE-NEXT:    li 4, 0
452; PWR8-LE-NEXT:    li 5, 0
453; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
454; PWR8-LE-NEXT:    rldimi 5, 3, 32, 0
455; PWR8-LE-NEXT:    mtfprd 1, 4
456; PWR8-LE-NEXT:    mtfprd 0, 5
457; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
458; PWR8-LE-NEXT:    blr
459entry:
460  %0 = load i32, ptr %p, align 4
461  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 1
462  ret <4 x i32> %vecinit1
463}
464
465define <4 x i32> @build_v4i32_load_2(ptr nocapture noundef readonly %p) {
466; PWR7-BE-LABEL: build_v4i32_load_2:
467; PWR7-BE:       # %bb.0: # %entry
468; PWR7-BE-NEXT:    lwz 3, 0(3)
469; PWR7-BE-NEXT:    li 4, 0
470; PWR7-BE-NEXT:    stw 4, -32(1)
471; PWR7-BE-NEXT:    stw 3, -16(1)
472; PWR7-BE-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
473; PWR7-BE-NEXT:    addi 3, 3, .LCPI10_0@toc@l
474; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
475; PWR7-BE-NEXT:    addi 3, 1, -32
476; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
477; PWR7-BE-NEXT:    addi 3, 1, -16
478; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
479; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
480; PWR7-BE-NEXT:    blr
481;
482; PWR8-BE-LABEL: build_v4i32_load_2:
483; PWR8-BE:       # %bb.0: # %entry
484; PWR8-BE-NEXT:    lwz 3, 0(3)
485; PWR8-BE-NEXT:    li 4, 0
486; PWR8-BE-NEXT:    li 5, 0
487; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
488; PWR8-BE-NEXT:    rldimi 5, 3, 32, 0
489; PWR8-BE-NEXT:    mtfprd 1, 4
490; PWR8-BE-NEXT:    mtfprd 0, 5
491; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
492; PWR8-BE-NEXT:    blr
493;
494; PWR7-LE-LABEL: build_v4i32_load_2:
495; PWR7-LE:       # %bb.0: # %entry
496; PWR7-LE-NEXT:    li 4, 0
497; PWR7-LE-NEXT:    lwz 3, 0(3)
498; PWR7-LE-NEXT:    stw 4, -32(1)
499; PWR7-LE-NEXT:    addis 4, 2, .LCPI10_0@toc@ha
500; PWR7-LE-NEXT:    addi 4, 4, .LCPI10_0@toc@l
501; PWR7-LE-NEXT:    stw 3, -16(1)
502; PWR7-LE-NEXT:    addi 3, 1, -16
503; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
504; PWR7-LE-NEXT:    addi 4, 1, -32
505; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
506; PWR7-LE-NEXT:    xxswapd 34, 0
507; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
508; PWR7-LE-NEXT:    xxswapd 35, 1
509; PWR7-LE-NEXT:    xxswapd 36, 0
510; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
511; PWR7-LE-NEXT:    blr
512;
513; PWR8-LE-LABEL: build_v4i32_load_2:
514; PWR8-LE:       # %bb.0: # %entry
515; PWR8-LE-NEXT:    lwz 3, 0(3)
516; PWR8-LE-NEXT:    li 4, 0
517; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
518; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
519; PWR8-LE-NEXT:    mtfprd 0, 3
520; PWR8-LE-NEXT:    mtfprd 1, 4
521; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
522; PWR8-LE-NEXT:    blr
523entry:
524  %0 = load i32, ptr %p, align 4
525  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 2
526  ret <4 x i32> %vecinit1
527}
528
529define <4 x i32> @build_v4i32_load_3(ptr nocapture noundef readonly %p) {
530; PWR7-BE-LABEL: build_v4i32_load_3:
531; PWR7-BE:       # %bb.0: # %entry
532; PWR7-BE-NEXT:    lwz 3, 0(3)
533; PWR7-BE-NEXT:    li 4, 0
534; PWR7-BE-NEXT:    stw 4, -32(1)
535; PWR7-BE-NEXT:    stw 3, -16(1)
536; PWR7-BE-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
537; PWR7-BE-NEXT:    addi 3, 3, .LCPI11_0@toc@l
538; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
539; PWR7-BE-NEXT:    addi 3, 1, -32
540; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
541; PWR7-BE-NEXT:    addi 3, 1, -16
542; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
543; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
544; PWR7-BE-NEXT:    blr
545;
546; PWR8-BE-LABEL: build_v4i32_load_3:
547; PWR8-BE:       # %bb.0: # %entry
548; PWR8-BE-NEXT:    lwz 3, 0(3)
549; PWR8-BE-NEXT:    li 4, 0
550; PWR8-BE-NEXT:    rldimi 3, 4, 32, 0
551; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
552; PWR8-BE-NEXT:    mtfprd 0, 3
553; PWR8-BE-NEXT:    mtfprd 1, 4
554; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
555; PWR8-BE-NEXT:    blr
556;
557; PWR7-LE-LABEL: build_v4i32_load_3:
558; PWR7-LE:       # %bb.0: # %entry
559; PWR7-LE-NEXT:    li 4, 0
560; PWR7-LE-NEXT:    lwz 3, 0(3)
561; PWR7-LE-NEXT:    stw 4, -32(1)
562; PWR7-LE-NEXT:    addis 4, 2, .LCPI11_0@toc@ha
563; PWR7-LE-NEXT:    addi 4, 4, .LCPI11_0@toc@l
564; PWR7-LE-NEXT:    stw 3, -16(1)
565; PWR7-LE-NEXT:    addi 3, 1, -16
566; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
567; PWR7-LE-NEXT:    addi 4, 1, -32
568; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
569; PWR7-LE-NEXT:    xxswapd 34, 0
570; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
571; PWR7-LE-NEXT:    xxswapd 35, 1
572; PWR7-LE-NEXT:    xxswapd 36, 0
573; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
574; PWR7-LE-NEXT:    blr
575;
576; PWR8-LE-LABEL: build_v4i32_load_3:
577; PWR8-LE:       # %bb.0: # %entry
578; PWR8-LE-NEXT:    lwz 3, 0(3)
579; PWR8-LE-NEXT:    li 4, 0
580; PWR8-LE-NEXT:    li 5, 0
581; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
582; PWR8-LE-NEXT:    rldimi 5, 3, 32, 0
583; PWR8-LE-NEXT:    mtfprd 1, 4
584; PWR8-LE-NEXT:    mtfprd 0, 5
585; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
586; PWR8-LE-NEXT:    blr
587entry:
588  %0 = load i32, ptr %p, align 4
589  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 3
590  ret <4 x i32> %vecinit1
591}
592
593define <4 x float> @build_v4f32_load_0(ptr nocapture noundef readonly %p) {
594; PWR7-BE-LABEL: build_v4f32_load_0:
595; PWR7-BE:       # %bb.0: # %entry
596; PWR7-BE-NEXT:    lwz 3, 0(3)
597; PWR7-BE-NEXT:    li 4, 0
598; PWR7-BE-NEXT:    stw 4, -16(1)
599; PWR7-BE-NEXT:    stw 3, -32(1)
600; PWR7-BE-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
601; PWR7-BE-NEXT:    addi 3, 3, .LCPI12_0@toc@l
602; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
603; PWR7-BE-NEXT:    addi 3, 1, -16
604; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
605; PWR7-BE-NEXT:    addi 3, 1, -32
606; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
607; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
608; PWR7-BE-NEXT:    blr
609;
610; PWR8-BE-LABEL: build_v4f32_load_0:
611; PWR8-BE:       # %bb.0: # %entry
612; PWR8-BE-NEXT:    lfs 0, 0(3)
613; PWR8-BE-NEXT:    xxlxor 1, 1, 1
614; PWR8-BE-NEXT:    xxmrghd 0, 0, 1
615; PWR8-BE-NEXT:    xxspltd 1, 1, 0
616; PWR8-BE-NEXT:    xvcvdpsp 34, 0
617; PWR8-BE-NEXT:    xvcvdpsp 35, 1
618; PWR8-BE-NEXT:    vmrgew 2, 2, 3
619; PWR8-BE-NEXT:    blr
620;
621; PWR7-LE-LABEL: build_v4f32_load_0:
622; PWR7-LE:       # %bb.0: # %entry
623; PWR7-LE-NEXT:    li 4, 0
624; PWR7-LE-NEXT:    lwz 3, 0(3)
625; PWR7-LE-NEXT:    stw 4, -16(1)
626; PWR7-LE-NEXT:    addis 4, 2, .LCPI12_0@toc@ha
627; PWR7-LE-NEXT:    addi 4, 4, .LCPI12_0@toc@l
628; PWR7-LE-NEXT:    stw 3, -32(1)
629; PWR7-LE-NEXT:    addi 3, 1, -32
630; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
631; PWR7-LE-NEXT:    addi 4, 1, -16
632; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
633; PWR7-LE-NEXT:    xxswapd 34, 0
634; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
635; PWR7-LE-NEXT:    xxswapd 35, 1
636; PWR7-LE-NEXT:    xxswapd 36, 0
637; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
638; PWR7-LE-NEXT:    blr
639;
640; PWR8-LE-LABEL: build_v4f32_load_0:
641; PWR8-LE:       # %bb.0: # %entry
642; PWR8-LE-NEXT:    lfs 0, 0(3)
643; PWR8-LE-NEXT:    xxlxor 1, 1, 1
644; PWR8-LE-NEXT:    xxmrghd 0, 1, 0
645; PWR8-LE-NEXT:    xxspltd 1, 1, 0
646; PWR8-LE-NEXT:    xvcvdpsp 34, 0
647; PWR8-LE-NEXT:    xvcvdpsp 35, 1
648; PWR8-LE-NEXT:    vmrgew 2, 3, 2
649; PWR8-LE-NEXT:    blr
650entry:
651  %0 = load float, ptr %p, align 4
652  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 0
653  ret <4 x float> %vecinit1
654}
655
656define <4 x float> @build_v4f32_load_1(ptr nocapture noundef readonly %p) {
657; PWR7-BE-LABEL: build_v4f32_load_1:
658; PWR7-BE:       # %bb.0: # %entry
659; PWR7-BE-NEXT:    lwz 3, 0(3)
660; PWR7-BE-NEXT:    li 4, 0
661; PWR7-BE-NEXT:    stw 4, -32(1)
662; PWR7-BE-NEXT:    stw 3, -16(1)
663; PWR7-BE-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
664; PWR7-BE-NEXT:    addi 3, 3, .LCPI13_0@toc@l
665; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
666; PWR7-BE-NEXT:    addi 3, 1, -32
667; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
668; PWR7-BE-NEXT:    addi 3, 1, -16
669; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
670; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
671; PWR7-BE-NEXT:    blr
672;
673; PWR8-BE-LABEL: build_v4f32_load_1:
674; PWR8-BE:       # %bb.0: # %entry
675; PWR8-BE-NEXT:    lfs 0, 0(3)
676; PWR8-BE-NEXT:    xxlxor 1, 1, 1
677; PWR8-BE-NEXT:    xxmrghd 0, 0, 1
678; PWR8-BE-NEXT:    xxspltd 1, 1, 0
679; PWR8-BE-NEXT:    xvcvdpsp 34, 0
680; PWR8-BE-NEXT:    xvcvdpsp 35, 1
681; PWR8-BE-NEXT:    vmrgew 2, 3, 2
682; PWR8-BE-NEXT:    blr
683;
684; PWR7-LE-LABEL: build_v4f32_load_1:
685; PWR7-LE:       # %bb.0: # %entry
686; PWR7-LE-NEXT:    li 4, 0
687; PWR7-LE-NEXT:    lwz 3, 0(3)
688; PWR7-LE-NEXT:    stw 4, -32(1)
689; PWR7-LE-NEXT:    addis 4, 2, .LCPI13_0@toc@ha
690; PWR7-LE-NEXT:    addi 4, 4, .LCPI13_0@toc@l
691; PWR7-LE-NEXT:    stw 3, -16(1)
692; PWR7-LE-NEXT:    addi 3, 1, -16
693; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
694; PWR7-LE-NEXT:    addi 4, 1, -32
695; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
696; PWR7-LE-NEXT:    xxswapd 34, 0
697; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
698; PWR7-LE-NEXT:    xxswapd 35, 1
699; PWR7-LE-NEXT:    xxswapd 36, 0
700; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
701; PWR7-LE-NEXT:    blr
702;
703; PWR8-LE-LABEL: build_v4f32_load_1:
704; PWR8-LE:       # %bb.0: # %entry
705; PWR8-LE-NEXT:    lfs 0, 0(3)
706; PWR8-LE-NEXT:    xxlxor 1, 1, 1
707; PWR8-LE-NEXT:    xxmrghd 0, 1, 0
708; PWR8-LE-NEXT:    xxspltd 1, 1, 0
709; PWR8-LE-NEXT:    xvcvdpsp 34, 0
710; PWR8-LE-NEXT:    xvcvdpsp 35, 1
711; PWR8-LE-NEXT:    vmrgew 2, 2, 3
712; PWR8-LE-NEXT:    blr
713entry:
714  %0 = load float, ptr %p, align 4
715  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 1
716  ret <4 x float> %vecinit1
717}
718
719define <4 x float> @build_v4f32_load_2(ptr nocapture noundef readonly %p) {
720; PWR7-BE-LABEL: build_v4f32_load_2:
721; PWR7-BE:       # %bb.0: # %entry
722; PWR7-BE-NEXT:    lwz 3, 0(3)
723; PWR7-BE-NEXT:    li 4, 0
724; PWR7-BE-NEXT:    stw 4, -32(1)
725; PWR7-BE-NEXT:    stw 3, -16(1)
726; PWR7-BE-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
727; PWR7-BE-NEXT:    addi 3, 3, .LCPI14_0@toc@l
728; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
729; PWR7-BE-NEXT:    addi 3, 1, -32
730; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
731; PWR7-BE-NEXT:    addi 3, 1, -16
732; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
733; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
734; PWR7-BE-NEXT:    blr
735;
736; PWR8-BE-LABEL: build_v4f32_load_2:
737; PWR8-BE:       # %bb.0: # %entry
738; PWR8-BE-NEXT:    lfs 0, 0(3)
739; PWR8-BE-NEXT:    xxlxor 1, 1, 1
740; PWR8-BE-NEXT:    xxmrghd 0, 1, 0
741; PWR8-BE-NEXT:    xxspltd 1, 1, 0
742; PWR8-BE-NEXT:    xvcvdpsp 34, 0
743; PWR8-BE-NEXT:    xvcvdpsp 35, 1
744; PWR8-BE-NEXT:    vmrgew 2, 2, 3
745; PWR8-BE-NEXT:    blr
746;
747; PWR7-LE-LABEL: build_v4f32_load_2:
748; PWR7-LE:       # %bb.0: # %entry
749; PWR7-LE-NEXT:    li 4, 0
750; PWR7-LE-NEXT:    lwz 3, 0(3)
751; PWR7-LE-NEXT:    stw 4, -32(1)
752; PWR7-LE-NEXT:    addis 4, 2, .LCPI14_0@toc@ha
753; PWR7-LE-NEXT:    addi 4, 4, .LCPI14_0@toc@l
754; PWR7-LE-NEXT:    stw 3, -16(1)
755; PWR7-LE-NEXT:    addi 3, 1, -16
756; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
757; PWR7-LE-NEXT:    addi 4, 1, -32
758; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
759; PWR7-LE-NEXT:    xxswapd 34, 0
760; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
761; PWR7-LE-NEXT:    xxswapd 35, 1
762; PWR7-LE-NEXT:    xxswapd 36, 0
763; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
764; PWR7-LE-NEXT:    blr
765;
766; PWR8-LE-LABEL: build_v4f32_load_2:
767; PWR8-LE:       # %bb.0: # %entry
768; PWR8-LE-NEXT:    lfs 0, 0(3)
769; PWR8-LE-NEXT:    xxlxor 1, 1, 1
770; PWR8-LE-NEXT:    xxmrghd 0, 0, 1
771; PWR8-LE-NEXT:    xxspltd 1, 1, 0
772; PWR8-LE-NEXT:    xvcvdpsp 34, 0
773; PWR8-LE-NEXT:    xvcvdpsp 35, 1
774; PWR8-LE-NEXT:    vmrgew 2, 3, 2
775; PWR8-LE-NEXT:    blr
776entry:
777  %0 = load float, ptr %p, align 4
778  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 2
779  ret <4 x float> %vecinit1
780}
781
782define <4 x float> @build_v4f32_load_3(ptr nocapture noundef readonly %p) {
783; PWR7-BE-LABEL: build_v4f32_load_3:
784; PWR7-BE:       # %bb.0: # %entry
785; PWR7-BE-NEXT:    lwz 3, 0(3)
786; PWR7-BE-NEXT:    li 4, 0
787; PWR7-BE-NEXT:    stw 4, -32(1)
788; PWR7-BE-NEXT:    stw 3, -16(1)
789; PWR7-BE-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
790; PWR7-BE-NEXT:    addi 3, 3, .LCPI15_0@toc@l
791; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
792; PWR7-BE-NEXT:    addi 3, 1, -32
793; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
794; PWR7-BE-NEXT:    addi 3, 1, -16
795; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
796; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
797; PWR7-BE-NEXT:    blr
798;
799; PWR8-BE-LABEL: build_v4f32_load_3:
800; PWR8-BE:       # %bb.0: # %entry
801; PWR8-BE-NEXT:    lfs 0, 0(3)
802; PWR8-BE-NEXT:    xxlxor 1, 1, 1
803; PWR8-BE-NEXT:    xxmrghd 0, 1, 0
804; PWR8-BE-NEXT:    xxspltd 1, 1, 0
805; PWR8-BE-NEXT:    xvcvdpsp 34, 0
806; PWR8-BE-NEXT:    xvcvdpsp 35, 1
807; PWR8-BE-NEXT:    vmrgew 2, 3, 2
808; PWR8-BE-NEXT:    blr
809;
810; PWR7-LE-LABEL: build_v4f32_load_3:
811; PWR7-LE:       # %bb.0: # %entry
812; PWR7-LE-NEXT:    li 4, 0
813; PWR7-LE-NEXT:    lwz 3, 0(3)
814; PWR7-LE-NEXT:    stw 4, -32(1)
815; PWR7-LE-NEXT:    addis 4, 2, .LCPI15_0@toc@ha
816; PWR7-LE-NEXT:    addi 4, 4, .LCPI15_0@toc@l
817; PWR7-LE-NEXT:    stw 3, -16(1)
818; PWR7-LE-NEXT:    addi 3, 1, -16
819; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
820; PWR7-LE-NEXT:    addi 4, 1, -32
821; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
822; PWR7-LE-NEXT:    xxswapd 34, 0
823; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
824; PWR7-LE-NEXT:    xxswapd 35, 1
825; PWR7-LE-NEXT:    xxswapd 36, 0
826; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
827; PWR7-LE-NEXT:    blr
828;
829; PWR8-LE-LABEL: build_v4f32_load_3:
830; PWR8-LE:       # %bb.0: # %entry
831; PWR8-LE-NEXT:    lfs 0, 0(3)
832; PWR8-LE-NEXT:    xxlxor 1, 1, 1
833; PWR8-LE-NEXT:    xxmrghd 0, 0, 1
834; PWR8-LE-NEXT:    xxspltd 1, 1, 0
835; PWR8-LE-NEXT:    xvcvdpsp 34, 0
836; PWR8-LE-NEXT:    xvcvdpsp 35, 1
837; PWR8-LE-NEXT:    vmrgew 2, 2, 3
838; PWR8-LE-NEXT:    blr
839entry:
840  %0 = load float, ptr %p, align 4
841  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 3
842  ret <4 x float> %vecinit1
843}
844