xref: /llvm-project/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll (revision 8b6e9de3dd114db28fde892c67960a87d9870637) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-BE %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-BE %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-LE %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-LE %s
6
7define  <2 x i64> @build_v2i64_extload_0(ptr nocapture noundef readonly %p) {
8; PWR7-BE-LABEL: build_v2i64_extload_0:
9; PWR7-BE:       # %bb.0: # %entry
10; PWR7-BE-NEXT:    lwz 3, 0(3)
11; PWR7-BE-NEXT:    li 4, 0
12; PWR7-BE-NEXT:    std 4, -8(1)
13; PWR7-BE-NEXT:    std 3, -16(1)
14; PWR7-BE-NEXT:    addi 3, 1, -16
15; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
16; PWR7-BE-NEXT:    blr
17;
18; PWR8-BE-LABEL: build_v2i64_extload_0:
19; PWR8-BE:       # %bb.0: # %entry
20; PWR8-BE-NEXT:    lwz 3, 0(3)
21; PWR8-BE-NEXT:    li 4, 0
22; PWR8-BE-NEXT:    mtfprd 0, 4
23; PWR8-BE-NEXT:    mtfprd 1, 3
24; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
25; PWR8-BE-NEXT:    blr
26;
27; PWR7-LE-LABEL: build_v2i64_extload_0:
28; PWR7-LE:       # %bb.0: # %entry
29; PWR7-LE-NEXT:    li 4, 0
30; PWR7-LE-NEXT:    lwz 3, 0(3)
31; PWR7-LE-NEXT:    stw 4, -16(1)
32; PWR7-LE-NEXT:    addis 4, 2, .LCPI0_0@toc@ha
33; PWR7-LE-NEXT:    addi 4, 4, .LCPI0_0@toc@l
34; PWR7-LE-NEXT:    stw 3, -32(1)
35; PWR7-LE-NEXT:    addi 3, 1, -32
36; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
37; PWR7-LE-NEXT:    addi 4, 1, -16
38; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
39; PWR7-LE-NEXT:    xxswapd 34, 0
40; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
41; PWR7-LE-NEXT:    xxswapd 35, 1
42; PWR7-LE-NEXT:    xxswapd 36, 0
43; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
44; PWR7-LE-NEXT:    blr
45;
46; PWR8-LE-LABEL: build_v2i64_extload_0:
47; PWR8-LE:       # %bb.0: # %entry
48; PWR8-LE-NEXT:    lwz 3, 0(3)
49; PWR8-LE-NEXT:    li 4, 0
50; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
51; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
52; PWR8-LE-NEXT:    mtfprd 0, 3
53; PWR8-LE-NEXT:    mtfprd 1, 4
54; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
55; PWR8-LE-NEXT:    blr
56entry:
57  %0 = load i32, ptr %p, align 4
58  %conv = zext i32 %0 to i64
59  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 0
60  ret <2 x i64> %vecinit1
61}
62
63define  <2 x i64> @build_v2i64_extload_1(ptr nocapture noundef readonly %p) {
64; PWR7-BE-LABEL: build_v2i64_extload_1:
65; PWR7-BE:       # %bb.0: # %entry
66; PWR7-BE-NEXT:    lwz 3, 0(3)
67; PWR7-BE-NEXT:    li 4, 0
68; PWR7-BE-NEXT:    std 4, -16(1)
69; PWR7-BE-NEXT:    std 3, -8(1)
70; PWR7-BE-NEXT:    addi 3, 1, -16
71; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
72; PWR7-BE-NEXT:    blr
73;
74; PWR8-BE-LABEL: build_v2i64_extload_1:
75; PWR8-BE:       # %bb.0: # %entry
76; PWR8-BE-NEXT:    lwz 3, 0(3)
77; PWR8-BE-NEXT:    li 4, 0
78; PWR8-BE-NEXT:    mtfprd 0, 4
79; PWR8-BE-NEXT:    mtfprd 1, 3
80; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
81; PWR8-BE-NEXT:    blr
82;
83; PWR7-LE-LABEL: build_v2i64_extload_1:
84; PWR7-LE:       # %bb.0: # %entry
85; PWR7-LE-NEXT:    lwz 3, 0(3)
86; PWR7-LE-NEXT:    li 4, 0
87; PWR7-LE-NEXT:    std 4, -16(1)
88; PWR7-LE-NEXT:    std 3, -8(1)
89; PWR7-LE-NEXT:    addi 3, 1, -16
90; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
91; PWR7-LE-NEXT:    xxswapd 34, 0
92; PWR7-LE-NEXT:    blr
93;
94; PWR8-LE-LABEL: build_v2i64_extload_1:
95; PWR8-LE:       # %bb.0: # %entry
96; PWR8-LE-NEXT:    lwz 3, 0(3)
97; PWR8-LE-NEXT:    li 4, 0
98; PWR8-LE-NEXT:    mtfprd 0, 4
99; PWR8-LE-NEXT:    mtfprd 1, 3
100; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
101; PWR8-LE-NEXT:    blr
102entry:
103  %0 = load i32, ptr %p, align 4
104  %conv = zext i32 %0 to i64
105  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 1
106  ret <2 x i64> %vecinit1
107}
108
109define <2 x double> @build_v2f64_extload_0(ptr nocapture noundef readonly %p) {
110; PWR7-BE-LABEL: build_v2f64_extload_0:
111; PWR7-BE:       # %bb.0: # %entry
112; PWR7-BE-NEXT:    lfs 0, 0(3)
113; PWR7-BE-NEXT:    xxlxor 1, 1, 1
114; PWR7-BE-NEXT:    xxmrghd 34, 0, 1
115; PWR7-BE-NEXT:    blr
116;
117; PWR8-BE-LABEL: build_v2f64_extload_0:
118; PWR8-BE:       # %bb.0: # %entry
119; PWR8-BE-NEXT:    lfs 0, 0(3)
120; PWR8-BE-NEXT:    xxlxor 1, 1, 1
121; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
122; PWR8-BE-NEXT:    blr
123;
124; PWR7-LE-LABEL: build_v2f64_extload_0:
125; PWR7-LE:       # %bb.0: # %entry
126; PWR7-LE-NEXT:    lfs 0, 0(3)
127; PWR7-LE-NEXT:    xxlxor 1, 1, 1
128; PWR7-LE-NEXT:    xxmrghd 34, 1, 0
129; PWR7-LE-NEXT:    blr
130;
131; PWR8-LE-LABEL: build_v2f64_extload_0:
132; PWR8-LE:       # %bb.0: # %entry
133; PWR8-LE-NEXT:    lfs 0, 0(3)
134; PWR8-LE-NEXT:    xxlxor 1, 1, 1
135; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
136; PWR8-LE-NEXT:    blr
137entry:
138  %0 = load float, ptr %p, align 4
139  %conv = fpext float %0 to double
140  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 0
141  ret <2 x double> %vecinit1
142}
143
144define <2 x double> @build_v2f64_extload_1(ptr nocapture noundef readonly %p) {
145; PWR7-BE-LABEL: build_v2f64_extload_1:
146; PWR7-BE:       # %bb.0: # %entry
147; PWR7-BE-NEXT:    lfs 0, 0(3)
148; PWR7-BE-NEXT:    xxlxor 1, 1, 1
149; PWR7-BE-NEXT:    xxmrghd 34, 1, 0
150; PWR7-BE-NEXT:    blr
151;
152; PWR8-BE-LABEL: build_v2f64_extload_1:
153; PWR8-BE:       # %bb.0: # %entry
154; PWR8-BE-NEXT:    lfs 0, 0(3)
155; PWR8-BE-NEXT:    xxlxor 1, 1, 1
156; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
157; PWR8-BE-NEXT:    blr
158;
159; PWR7-LE-LABEL: build_v2f64_extload_1:
160; PWR7-LE:       # %bb.0: # %entry
161; PWR7-LE-NEXT:    lfs 0, 0(3)
162; PWR7-LE-NEXT:    xxlxor 1, 1, 1
163; PWR7-LE-NEXT:    xxmrghd 34, 0, 1
164; PWR7-LE-NEXT:    blr
165;
166; PWR8-LE-LABEL: build_v2f64_extload_1:
167; PWR8-LE:       # %bb.0: # %entry
168; PWR8-LE-NEXT:    lfs 0, 0(3)
169; PWR8-LE-NEXT:    xxlxor 1, 1, 1
170; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
171; PWR8-LE-NEXT:    blr
172entry:
173  %0 = load float, ptr %p, align 4
174  %conv = fpext float %0 to double
175  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 1
176  ret <2 x double> %vecinit1
177}
178
179define <2 x double> @build_v2f64_load_0(ptr nocapture noundef readonly %p) {
180; PWR7-BE-LABEL: build_v2f64_load_0:
181; PWR7-BE:       # %bb.0: # %entry
182; PWR7-BE-NEXT:    lfd 0, 0(3)
183; PWR7-BE-NEXT:    xxlxor 1, 1, 1
184; PWR7-BE-NEXT:    xxmrghd 34, 0, 1
185; PWR7-BE-NEXT:    blr
186;
187; PWR8-BE-LABEL: build_v2f64_load_0:
188; PWR8-BE:       # %bb.0: # %entry
189; PWR8-BE-NEXT:    lfd 0, 0(3)
190; PWR8-BE-NEXT:    xxlxor 1, 1, 1
191; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
192; PWR8-BE-NEXT:    blr
193;
194; PWR7-LE-LABEL: build_v2f64_load_0:
195; PWR7-LE:       # %bb.0: # %entry
196; PWR7-LE-NEXT:    lfd 0, 0(3)
197; PWR7-LE-NEXT:    xxlxor 1, 1, 1
198; PWR7-LE-NEXT:    xxmrghd 34, 1, 0
199; PWR7-LE-NEXT:    blr
200;
201; PWR8-LE-LABEL: build_v2f64_load_0:
202; PWR8-LE:       # %bb.0: # %entry
203; PWR8-LE-NEXT:    lfd 0, 0(3)
204; PWR8-LE-NEXT:    xxlxor 1, 1, 1
205; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
206; PWR8-LE-NEXT:    blr
207entry:
208  %0 = load double, ptr %p, align 8
209  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 0
210  ret <2 x double> %vecinit1
211}
212
213define <2 x double> @build_v2f64_load_1(ptr nocapture noundef readonly %p) {
214; PWR7-BE-LABEL: build_v2f64_load_1:
215; PWR7-BE:       # %bb.0: # %entry
216; PWR7-BE-NEXT:    lfd 0, 0(3)
217; PWR7-BE-NEXT:    xxlxor 1, 1, 1
218; PWR7-BE-NEXT:    xxmrghd 34, 1, 0
219; PWR7-BE-NEXT:    blr
220;
221; PWR8-BE-LABEL: build_v2f64_load_1:
222; PWR8-BE:       # %bb.0: # %entry
223; PWR8-BE-NEXT:    lfd 0, 0(3)
224; PWR8-BE-NEXT:    xxlxor 1, 1, 1
225; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
226; PWR8-BE-NEXT:    blr
227;
228; PWR7-LE-LABEL: build_v2f64_load_1:
229; PWR7-LE:       # %bb.0: # %entry
230; PWR7-LE-NEXT:    lfd 0, 0(3)
231; PWR7-LE-NEXT:    xxlxor 1, 1, 1
232; PWR7-LE-NEXT:    xxmrghd 34, 0, 1
233; PWR7-LE-NEXT:    blr
234;
235; PWR8-LE-LABEL: build_v2f64_load_1:
236; PWR8-LE:       # %bb.0: # %entry
237; PWR8-LE-NEXT:    lfd 0, 0(3)
238; PWR8-LE-NEXT:    xxlxor 1, 1, 1
239; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
240; PWR8-LE-NEXT:    blr
241entry:
242  %0 = load double, ptr %p, align 8
243  %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 1
244  ret <2 x double> %vecinit1
245}
246
247define <2 x i64> @build_v2i64_load_0(ptr nocapture noundef readonly %p) {
248; PWR7-BE-LABEL: build_v2i64_load_0:
249; PWR7-BE:       # %bb.0: # %entry
250; PWR7-BE-NEXT:    ld 3, 0(3)
251; PWR7-BE-NEXT:    li 4, 0
252; PWR7-BE-NEXT:    std 4, -8(1)
253; PWR7-BE-NEXT:    std 3, -16(1)
254; PWR7-BE-NEXT:    addi 3, 1, -16
255; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
256; PWR7-BE-NEXT:    blr
257;
258; PWR8-BE-LABEL: build_v2i64_load_0:
259; PWR8-BE:       # %bb.0: # %entry
260; PWR8-BE-NEXT:    ld 3, 0(3)
261; PWR8-BE-NEXT:    li 4, 0
262; PWR8-BE-NEXT:    mtfprd 0, 4
263; PWR8-BE-NEXT:    mtfprd 1, 3
264; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
265; PWR8-BE-NEXT:    blr
266;
267; PWR7-LE-LABEL: build_v2i64_load_0:
268; PWR7-LE:       # %bb.0: # %entry
269; PWR7-LE-NEXT:    ld 3, 0(3)
270; PWR7-LE-NEXT:    li 4, 0
271; PWR7-LE-NEXT:    std 4, -8(1)
272; PWR7-LE-NEXT:    std 3, -16(1)
273; PWR7-LE-NEXT:    addi 3, 1, -16
274; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
275; PWR7-LE-NEXT:    xxswapd 34, 0
276; PWR7-LE-NEXT:    blr
277;
278; PWR8-LE-LABEL: build_v2i64_load_0:
279; PWR8-LE:       # %bb.0: # %entry
280; PWR8-LE-NEXT:    ld 3, 0(3)
281; PWR8-LE-NEXT:    li 4, 0
282; PWR8-LE-NEXT:    mtfprd 0, 4
283; PWR8-LE-NEXT:    mtfprd 1, 3
284; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
285; PWR8-LE-NEXT:    blr
286entry:
287  %0 = load i64, ptr %p, align 8
288  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 0
289  ret <2 x i64> %vecinit1
290}
291
292define <2 x i64> @build_v2i64_load_1(ptr nocapture noundef readonly %p) {
293; PWR7-BE-LABEL: build_v2i64_load_1:
294; PWR7-BE:       # %bb.0: # %entry
295; PWR7-BE-NEXT:    ld 3, 0(3)
296; PWR7-BE-NEXT:    li 4, 0
297; PWR7-BE-NEXT:    std 4, -16(1)
298; PWR7-BE-NEXT:    std 3, -8(1)
299; PWR7-BE-NEXT:    addi 3, 1, -16
300; PWR7-BE-NEXT:    lxvd2x 34, 0, 3
301; PWR7-BE-NEXT:    blr
302;
303; PWR8-BE-LABEL: build_v2i64_load_1:
304; PWR8-BE:       # %bb.0: # %entry
305; PWR8-BE-NEXT:    ld 3, 0(3)
306; PWR8-BE-NEXT:    li 4, 0
307; PWR8-BE-NEXT:    mtfprd 0, 4
308; PWR8-BE-NEXT:    mtfprd 1, 3
309; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
310; PWR8-BE-NEXT:    blr
311;
312; PWR7-LE-LABEL: build_v2i64_load_1:
313; PWR7-LE:       # %bb.0: # %entry
314; PWR7-LE-NEXT:    ld 3, 0(3)
315; PWR7-LE-NEXT:    li 4, 0
316; PWR7-LE-NEXT:    std 4, -16(1)
317; PWR7-LE-NEXT:    std 3, -8(1)
318; PWR7-LE-NEXT:    addi 3, 1, -16
319; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
320; PWR7-LE-NEXT:    xxswapd 34, 0
321; PWR7-LE-NEXT:    blr
322;
323; PWR8-LE-LABEL: build_v2i64_load_1:
324; PWR8-LE:       # %bb.0: # %entry
325; PWR8-LE-NEXT:    ld 3, 0(3)
326; PWR8-LE-NEXT:    li 4, 0
327; PWR8-LE-NEXT:    mtfprd 0, 4
328; PWR8-LE-NEXT:    mtfprd 1, 3
329; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
330; PWR8-LE-NEXT:    blr
331entry:
332  %0 = load i64, ptr %p, align 8
333  %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 1
334  ret <2 x i64> %vecinit1
335}
336
337define <4 x i32> @build_v4i32_load_0(ptr nocapture noundef readonly %p) {
338; PWR7-BE-LABEL: build_v4i32_load_0:
339; PWR7-BE:       # %bb.0: # %entry
340; PWR7-BE-NEXT:    lwz 3, 0(3)
341; PWR7-BE-NEXT:    xxlxor 36, 36, 36
342; PWR7-BE-NEXT:    sldi 3, 3, 32
343; PWR7-BE-NEXT:    std 3, -32(1)
344; PWR7-BE-NEXT:    std 3, -24(1)
345; PWR7-BE-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
346; PWR7-BE-NEXT:    addi 3, 3, .LCPI8_0@toc@l
347; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
348; PWR7-BE-NEXT:    addi 3, 1, -32
349; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
350; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
351; PWR7-BE-NEXT:    blr
352;
353; PWR8-BE-LABEL: build_v4i32_load_0:
354; PWR8-BE:       # %bb.0: # %entry
355; PWR8-BE-NEXT:    lwz 3, 0(3)
356; PWR8-BE-NEXT:    li 4, 0
357; PWR8-BE-NEXT:    li 5, 0
358; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
359; PWR8-BE-NEXT:    rldimi 5, 3, 32, 0
360; PWR8-BE-NEXT:    mtfprd 1, 4
361; PWR8-BE-NEXT:    mtfprd 0, 5
362; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
363; PWR8-BE-NEXT:    blr
364;
365; PWR7-LE-LABEL: build_v4i32_load_0:
366; PWR7-LE:       # %bb.0: # %entry
367; PWR7-LE-NEXT:    li 4, 0
368; PWR7-LE-NEXT:    lwz 3, 0(3)
369; PWR7-LE-NEXT:    stw 4, -16(1)
370; PWR7-LE-NEXT:    addis 4, 2, .LCPI8_0@toc@ha
371; PWR7-LE-NEXT:    addi 4, 4, .LCPI8_0@toc@l
372; PWR7-LE-NEXT:    stw 3, -32(1)
373; PWR7-LE-NEXT:    addi 3, 1, -32
374; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
375; PWR7-LE-NEXT:    addi 4, 1, -16
376; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
377; PWR7-LE-NEXT:    xxswapd 34, 0
378; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
379; PWR7-LE-NEXT:    xxswapd 35, 1
380; PWR7-LE-NEXT:    xxswapd 36, 0
381; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
382; PWR7-LE-NEXT:    blr
383;
384; PWR8-LE-LABEL: build_v4i32_load_0:
385; PWR8-LE:       # %bb.0: # %entry
386; PWR8-LE-NEXT:    lwz 3, 0(3)
387; PWR8-LE-NEXT:    li 4, 0
388; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
389; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
390; PWR8-LE-NEXT:    mtfprd 0, 3
391; PWR8-LE-NEXT:    mtfprd 1, 4
392; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
393; PWR8-LE-NEXT:    blr
394entry:
395  %0 = load i32, ptr %p, align 4
396  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 0
397  ret <4 x i32> %vecinit1
398}
399
400define <4 x i32> @build_v4i32_load_1(ptr nocapture noundef readonly %p) {
401; PWR7-BE-LABEL: build_v4i32_load_1:
402; PWR7-BE:       # %bb.0: # %entry
403; PWR7-BE-NEXT:    lwz 3, 0(3)
404; PWR7-BE-NEXT:    xxlxor 36, 36, 36
405; PWR7-BE-NEXT:    sldi 3, 3, 32
406; PWR7-BE-NEXT:    std 3, -16(1)
407; PWR7-BE-NEXT:    std 3, -8(1)
408; PWR7-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
409; PWR7-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
410; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
411; PWR7-BE-NEXT:    addi 3, 1, -16
412; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
413; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
414; PWR7-BE-NEXT:    blr
415;
416; PWR8-BE-LABEL: build_v4i32_load_1:
417; PWR8-BE:       # %bb.0: # %entry
418; PWR8-BE-NEXT:    lwz 3, 0(3)
419; PWR8-BE-NEXT:    li 4, 0
420; PWR8-BE-NEXT:    rldimi 3, 4, 32, 0
421; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
422; PWR8-BE-NEXT:    mtfprd 0, 3
423; PWR8-BE-NEXT:    mtfprd 1, 4
424; PWR8-BE-NEXT:    xxmrghd 34, 0, 1
425; PWR8-BE-NEXT:    blr
426;
427; PWR7-LE-LABEL: build_v4i32_load_1:
428; PWR7-LE:       # %bb.0: # %entry
429; PWR7-LE-NEXT:    li 4, 0
430; PWR7-LE-NEXT:    lwz 3, 0(3)
431; PWR7-LE-NEXT:    stw 4, -32(1)
432; PWR7-LE-NEXT:    addis 4, 2, .LCPI9_0@toc@ha
433; PWR7-LE-NEXT:    addi 4, 4, .LCPI9_0@toc@l
434; PWR7-LE-NEXT:    stw 3, -16(1)
435; PWR7-LE-NEXT:    addi 3, 1, -16
436; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
437; PWR7-LE-NEXT:    addi 4, 1, -32
438; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
439; PWR7-LE-NEXT:    xxswapd 34, 0
440; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
441; PWR7-LE-NEXT:    xxswapd 35, 1
442; PWR7-LE-NEXT:    xxswapd 36, 0
443; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
444; PWR7-LE-NEXT:    blr
445;
446; PWR8-LE-LABEL: build_v4i32_load_1:
447; PWR8-LE:       # %bb.0: # %entry
448; PWR8-LE-NEXT:    lwz 3, 0(3)
449; PWR8-LE-NEXT:    li 4, 0
450; PWR8-LE-NEXT:    li 5, 0
451; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
452; PWR8-LE-NEXT:    rldimi 5, 3, 32, 0
453; PWR8-LE-NEXT:    mtfprd 1, 4
454; PWR8-LE-NEXT:    mtfprd 0, 5
455; PWR8-LE-NEXT:    xxmrghd 34, 1, 0
456; PWR8-LE-NEXT:    blr
457entry:
458  %0 = load i32, ptr %p, align 4
459  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 1
460  ret <4 x i32> %vecinit1
461}
462
463define <4 x i32> @build_v4i32_load_2(ptr nocapture noundef readonly %p) {
464; PWR7-BE-LABEL: build_v4i32_load_2:
465; PWR7-BE:       # %bb.0: # %entry
466; PWR7-BE-NEXT:    lwz 3, 0(3)
467; PWR7-BE-NEXT:    xxlxor 36, 36, 36
468; PWR7-BE-NEXT:    sldi 3, 3, 32
469; PWR7-BE-NEXT:    std 3, -16(1)
470; PWR7-BE-NEXT:    std 3, -8(1)
471; PWR7-BE-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
472; PWR7-BE-NEXT:    addi 3, 3, .LCPI10_0@toc@l
473; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
474; PWR7-BE-NEXT:    addi 3, 1, -16
475; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
476; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
477; PWR7-BE-NEXT:    blr
478;
479; PWR8-BE-LABEL: build_v4i32_load_2:
480; PWR8-BE:       # %bb.0: # %entry
481; PWR8-BE-NEXT:    lwz 3, 0(3)
482; PWR8-BE-NEXT:    li 4, 0
483; PWR8-BE-NEXT:    li 5, 0
484; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
485; PWR8-BE-NEXT:    rldimi 5, 3, 32, 0
486; PWR8-BE-NEXT:    mtfprd 1, 4
487; PWR8-BE-NEXT:    mtfprd 0, 5
488; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
489; PWR8-BE-NEXT:    blr
490;
491; PWR7-LE-LABEL: build_v4i32_load_2:
492; PWR7-LE:       # %bb.0: # %entry
493; PWR7-LE-NEXT:    li 4, 0
494; PWR7-LE-NEXT:    lwz 3, 0(3)
495; PWR7-LE-NEXT:    stw 4, -32(1)
496; PWR7-LE-NEXT:    addis 4, 2, .LCPI10_0@toc@ha
497; PWR7-LE-NEXT:    addi 4, 4, .LCPI10_0@toc@l
498; PWR7-LE-NEXT:    stw 3, -16(1)
499; PWR7-LE-NEXT:    addi 3, 1, -16
500; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
501; PWR7-LE-NEXT:    addi 4, 1, -32
502; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
503; PWR7-LE-NEXT:    xxswapd 34, 0
504; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
505; PWR7-LE-NEXT:    xxswapd 35, 1
506; PWR7-LE-NEXT:    xxswapd 36, 0
507; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
508; PWR7-LE-NEXT:    blr
509;
510; PWR8-LE-LABEL: build_v4i32_load_2:
511; PWR8-LE:       # %bb.0: # %entry
512; PWR8-LE-NEXT:    lwz 3, 0(3)
513; PWR8-LE-NEXT:    li 4, 0
514; PWR8-LE-NEXT:    rldimi 3, 4, 32, 0
515; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
516; PWR8-LE-NEXT:    mtfprd 0, 3
517; PWR8-LE-NEXT:    mtfprd 1, 4
518; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
519; PWR8-LE-NEXT:    blr
520entry:
521  %0 = load i32, ptr %p, align 4
522  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 2
523  ret <4 x i32> %vecinit1
524}
525
526define <4 x i32> @build_v4i32_load_3(ptr nocapture noundef readonly %p) {
527; PWR7-BE-LABEL: build_v4i32_load_3:
528; PWR7-BE:       # %bb.0: # %entry
529; PWR7-BE-NEXT:    lwz 3, 0(3)
530; PWR7-BE-NEXT:    xxlxor 36, 36, 36
531; PWR7-BE-NEXT:    sldi 3, 3, 32
532; PWR7-BE-NEXT:    std 3, -16(1)
533; PWR7-BE-NEXT:    std 3, -8(1)
534; PWR7-BE-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
535; PWR7-BE-NEXT:    addi 3, 3, .LCPI11_0@toc@l
536; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
537; PWR7-BE-NEXT:    addi 3, 1, -16
538; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
539; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
540; PWR7-BE-NEXT:    blr
541;
542; PWR8-BE-LABEL: build_v4i32_load_3:
543; PWR8-BE:       # %bb.0: # %entry
544; PWR8-BE-NEXT:    lwz 3, 0(3)
545; PWR8-BE-NEXT:    li 4, 0
546; PWR8-BE-NEXT:    rldimi 3, 4, 32, 0
547; PWR8-BE-NEXT:    rldimi 4, 4, 32, 0
548; PWR8-BE-NEXT:    mtfprd 0, 3
549; PWR8-BE-NEXT:    mtfprd 1, 4
550; PWR8-BE-NEXT:    xxmrghd 34, 1, 0
551; PWR8-BE-NEXT:    blr
552;
553; PWR7-LE-LABEL: build_v4i32_load_3:
554; PWR7-LE:       # %bb.0: # %entry
555; PWR7-LE-NEXT:    li 4, 0
556; PWR7-LE-NEXT:    lwz 3, 0(3)
557; PWR7-LE-NEXT:    stw 4, -32(1)
558; PWR7-LE-NEXT:    addis 4, 2, .LCPI11_0@toc@ha
559; PWR7-LE-NEXT:    addi 4, 4, .LCPI11_0@toc@l
560; PWR7-LE-NEXT:    stw 3, -16(1)
561; PWR7-LE-NEXT:    addi 3, 1, -16
562; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
563; PWR7-LE-NEXT:    addi 4, 1, -32
564; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
565; PWR7-LE-NEXT:    xxswapd 34, 0
566; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
567; PWR7-LE-NEXT:    xxswapd 35, 1
568; PWR7-LE-NEXT:    xxswapd 36, 0
569; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
570; PWR7-LE-NEXT:    blr
571;
572; PWR8-LE-LABEL: build_v4i32_load_3:
573; PWR8-LE:       # %bb.0: # %entry
574; PWR8-LE-NEXT:    lwz 3, 0(3)
575; PWR8-LE-NEXT:    li 4, 0
576; PWR8-LE-NEXT:    li 5, 0
577; PWR8-LE-NEXT:    rldimi 4, 4, 32, 0
578; PWR8-LE-NEXT:    rldimi 5, 3, 32, 0
579; PWR8-LE-NEXT:    mtfprd 1, 4
580; PWR8-LE-NEXT:    mtfprd 0, 5
581; PWR8-LE-NEXT:    xxmrghd 34, 0, 1
582; PWR8-LE-NEXT:    blr
583entry:
584  %0 = load i32, ptr %p, align 4
585  %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 3
586  ret <4 x i32> %vecinit1
587}
588
589define <4 x float> @build_v4f32_load_0(ptr nocapture noundef readonly %p) {
590; PWR7-BE-LABEL: build_v4f32_load_0:
591; PWR7-BE:       # %bb.0: # %entry
592; PWR7-BE-NEXT:    lwz 3, 0(3)
593; PWR7-BE-NEXT:    li 4, 0
594; PWR7-BE-NEXT:    stw 4, -16(1)
595; PWR7-BE-NEXT:    stw 3, -32(1)
596; PWR7-BE-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
597; PWR7-BE-NEXT:    addi 3, 3, .LCPI12_0@toc@l
598; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
599; PWR7-BE-NEXT:    addi 3, 1, -16
600; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
601; PWR7-BE-NEXT:    addi 3, 1, -32
602; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
603; PWR7-BE-NEXT:    vperm 2, 4, 3, 2
604; PWR7-BE-NEXT:    blr
605;
606; PWR8-BE-LABEL: build_v4f32_load_0:
607; PWR8-BE:       # %bb.0: # %entry
608; PWR8-BE-NEXT:    lfs 0, 0(3)
609; PWR8-BE-NEXT:    xxlxor 1, 1, 1
610; PWR8-BE-NEXT:    xxmrghd 0, 0, 1
611; PWR8-BE-NEXT:    xxspltd 1, 1, 0
612; PWR8-BE-NEXT:    xvcvdpsp 34, 0
613; PWR8-BE-NEXT:    xvcvdpsp 35, 1
614; PWR8-BE-NEXT:    vmrgew 2, 2, 3
615; PWR8-BE-NEXT:    blr
616;
617; PWR7-LE-LABEL: build_v4f32_load_0:
618; PWR7-LE:       # %bb.0: # %entry
619; PWR7-LE-NEXT:    li 4, 0
620; PWR7-LE-NEXT:    lwz 3, 0(3)
621; PWR7-LE-NEXT:    stw 4, -16(1)
622; PWR7-LE-NEXT:    addis 4, 2, .LCPI12_0@toc@ha
623; PWR7-LE-NEXT:    addi 4, 4, .LCPI12_0@toc@l
624; PWR7-LE-NEXT:    stw 3, -32(1)
625; PWR7-LE-NEXT:    addi 3, 1, -32
626; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
627; PWR7-LE-NEXT:    addi 4, 1, -16
628; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
629; PWR7-LE-NEXT:    xxswapd 34, 0
630; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
631; PWR7-LE-NEXT:    xxswapd 35, 1
632; PWR7-LE-NEXT:    xxswapd 36, 0
633; PWR7-LE-NEXT:    vperm 2, 3, 4, 2
634; PWR7-LE-NEXT:    blr
635;
636; PWR8-LE-LABEL: build_v4f32_load_0:
637; PWR8-LE:       # %bb.0: # %entry
638; PWR8-LE-NEXT:    lfs 0, 0(3)
639; PWR8-LE-NEXT:    xxlxor 1, 1, 1
640; PWR8-LE-NEXT:    xxmrghd 0, 1, 0
641; PWR8-LE-NEXT:    xxspltd 1, 1, 0
642; PWR8-LE-NEXT:    xvcvdpsp 34, 0
643; PWR8-LE-NEXT:    xvcvdpsp 35, 1
644; PWR8-LE-NEXT:    vmrgew 2, 3, 2
645; PWR8-LE-NEXT:    blr
646entry:
647  %0 = load float, ptr %p, align 4
648  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 0
649  ret <4 x float> %vecinit1
650}
651
652define <4 x float> @build_v4f32_load_1(ptr nocapture noundef readonly %p) {
653; PWR7-BE-LABEL: build_v4f32_load_1:
654; PWR7-BE:       # %bb.0: # %entry
655; PWR7-BE-NEXT:    lwz 3, 0(3)
656; PWR7-BE-NEXT:    li 4, 0
657; PWR7-BE-NEXT:    stw 4, -32(1)
658; PWR7-BE-NEXT:    stw 3, -16(1)
659; PWR7-BE-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
660; PWR7-BE-NEXT:    addi 3, 3, .LCPI13_0@toc@l
661; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
662; PWR7-BE-NEXT:    addi 3, 1, -32
663; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
664; PWR7-BE-NEXT:    addi 3, 1, -16
665; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
666; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
667; PWR7-BE-NEXT:    blr
668;
669; PWR8-BE-LABEL: build_v4f32_load_1:
670; PWR8-BE:       # %bb.0: # %entry
671; PWR8-BE-NEXT:    lfs 0, 0(3)
672; PWR8-BE-NEXT:    xxlxor 1, 1, 1
673; PWR8-BE-NEXT:    xxmrghd 0, 0, 1
674; PWR8-BE-NEXT:    xxspltd 1, 1, 0
675; PWR8-BE-NEXT:    xvcvdpsp 34, 0
676; PWR8-BE-NEXT:    xvcvdpsp 35, 1
677; PWR8-BE-NEXT:    vmrgew 2, 3, 2
678; PWR8-BE-NEXT:    blr
679;
680; PWR7-LE-LABEL: build_v4f32_load_1:
681; PWR7-LE:       # %bb.0: # %entry
682; PWR7-LE-NEXT:    li 4, 0
683; PWR7-LE-NEXT:    lwz 3, 0(3)
684; PWR7-LE-NEXT:    stw 4, -32(1)
685; PWR7-LE-NEXT:    addis 4, 2, .LCPI13_0@toc@ha
686; PWR7-LE-NEXT:    addi 4, 4, .LCPI13_0@toc@l
687; PWR7-LE-NEXT:    stw 3, -16(1)
688; PWR7-LE-NEXT:    addi 3, 1, -16
689; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
690; PWR7-LE-NEXT:    addi 4, 1, -32
691; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
692; PWR7-LE-NEXT:    xxswapd 34, 0
693; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
694; PWR7-LE-NEXT:    xxswapd 35, 1
695; PWR7-LE-NEXT:    xxswapd 36, 0
696; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
697; PWR7-LE-NEXT:    blr
698;
699; PWR8-LE-LABEL: build_v4f32_load_1:
700; PWR8-LE:       # %bb.0: # %entry
701; PWR8-LE-NEXT:    lfs 0, 0(3)
702; PWR8-LE-NEXT:    xxlxor 1, 1, 1
703; PWR8-LE-NEXT:    xxmrghd 0, 1, 0
704; PWR8-LE-NEXT:    xxspltd 1, 1, 0
705; PWR8-LE-NEXT:    xvcvdpsp 34, 0
706; PWR8-LE-NEXT:    xvcvdpsp 35, 1
707; PWR8-LE-NEXT:    vmrgew 2, 2, 3
708; PWR8-LE-NEXT:    blr
709entry:
710  %0 = load float, ptr %p, align 4
711  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 1
712  ret <4 x float> %vecinit1
713}
714
715define <4 x float> @build_v4f32_load_2(ptr nocapture noundef readonly %p) {
716; PWR7-BE-LABEL: build_v4f32_load_2:
717; PWR7-BE:       # %bb.0: # %entry
718; PWR7-BE-NEXT:    lwz 3, 0(3)
719; PWR7-BE-NEXT:    li 4, 0
720; PWR7-BE-NEXT:    stw 4, -32(1)
721; PWR7-BE-NEXT:    stw 3, -16(1)
722; PWR7-BE-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
723; PWR7-BE-NEXT:    addi 3, 3, .LCPI14_0@toc@l
724; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
725; PWR7-BE-NEXT:    addi 3, 1, -32
726; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
727; PWR7-BE-NEXT:    addi 3, 1, -16
728; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
729; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
730; PWR7-BE-NEXT:    blr
731;
732; PWR8-BE-LABEL: build_v4f32_load_2:
733; PWR8-BE:       # %bb.0: # %entry
734; PWR8-BE-NEXT:    lfs 0, 0(3)
735; PWR8-BE-NEXT:    xxlxor 1, 1, 1
736; PWR8-BE-NEXT:    xxmrghd 0, 1, 0
737; PWR8-BE-NEXT:    xxspltd 1, 1, 0
738; PWR8-BE-NEXT:    xvcvdpsp 34, 0
739; PWR8-BE-NEXT:    xvcvdpsp 35, 1
740; PWR8-BE-NEXT:    vmrgew 2, 2, 3
741; PWR8-BE-NEXT:    blr
742;
743; PWR7-LE-LABEL: build_v4f32_load_2:
744; PWR7-LE:       # %bb.0: # %entry
745; PWR7-LE-NEXT:    li 4, 0
746; PWR7-LE-NEXT:    lwz 3, 0(3)
747; PWR7-LE-NEXT:    stw 4, -32(1)
748; PWR7-LE-NEXT:    addis 4, 2, .LCPI14_0@toc@ha
749; PWR7-LE-NEXT:    addi 4, 4, .LCPI14_0@toc@l
750; PWR7-LE-NEXT:    stw 3, -16(1)
751; PWR7-LE-NEXT:    addi 3, 1, -16
752; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
753; PWR7-LE-NEXT:    addi 4, 1, -32
754; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
755; PWR7-LE-NEXT:    xxswapd 34, 0
756; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
757; PWR7-LE-NEXT:    xxswapd 35, 1
758; PWR7-LE-NEXT:    xxswapd 36, 0
759; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
760; PWR7-LE-NEXT:    blr
761;
762; PWR8-LE-LABEL: build_v4f32_load_2:
763; PWR8-LE:       # %bb.0: # %entry
764; PWR8-LE-NEXT:    lfs 0, 0(3)
765; PWR8-LE-NEXT:    xxlxor 1, 1, 1
766; PWR8-LE-NEXT:    xxmrghd 0, 0, 1
767; PWR8-LE-NEXT:    xxspltd 1, 1, 0
768; PWR8-LE-NEXT:    xvcvdpsp 34, 0
769; PWR8-LE-NEXT:    xvcvdpsp 35, 1
770; PWR8-LE-NEXT:    vmrgew 2, 3, 2
771; PWR8-LE-NEXT:    blr
772entry:
773  %0 = load float, ptr %p, align 4
774  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 2
775  ret <4 x float> %vecinit1
776}
777
778define <4 x float> @build_v4f32_load_3(ptr nocapture noundef readonly %p) {
779; PWR7-BE-LABEL: build_v4f32_load_3:
780; PWR7-BE:       # %bb.0: # %entry
781; PWR7-BE-NEXT:    lwz 3, 0(3)
782; PWR7-BE-NEXT:    li 4, 0
783; PWR7-BE-NEXT:    stw 4, -32(1)
784; PWR7-BE-NEXT:    stw 3, -16(1)
785; PWR7-BE-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
786; PWR7-BE-NEXT:    addi 3, 3, .LCPI15_0@toc@l
787; PWR7-BE-NEXT:    lxvw4x 34, 0, 3
788; PWR7-BE-NEXT:    addi 3, 1, -32
789; PWR7-BE-NEXT:    lxvw4x 35, 0, 3
790; PWR7-BE-NEXT:    addi 3, 1, -16
791; PWR7-BE-NEXT:    lxvw4x 36, 0, 3
792; PWR7-BE-NEXT:    vperm 2, 3, 4, 2
793; PWR7-BE-NEXT:    blr
794;
795; PWR8-BE-LABEL: build_v4f32_load_3:
796; PWR8-BE:       # %bb.0: # %entry
797; PWR8-BE-NEXT:    lfs 0, 0(3)
798; PWR8-BE-NEXT:    xxlxor 1, 1, 1
799; PWR8-BE-NEXT:    xxmrghd 0, 1, 0
800; PWR8-BE-NEXT:    xxspltd 1, 1, 0
801; PWR8-BE-NEXT:    xvcvdpsp 34, 0
802; PWR8-BE-NEXT:    xvcvdpsp 35, 1
803; PWR8-BE-NEXT:    vmrgew 2, 3, 2
804; PWR8-BE-NEXT:    blr
805;
806; PWR7-LE-LABEL: build_v4f32_load_3:
807; PWR7-LE:       # %bb.0: # %entry
808; PWR7-LE-NEXT:    li 4, 0
809; PWR7-LE-NEXT:    lwz 3, 0(3)
810; PWR7-LE-NEXT:    stw 4, -32(1)
811; PWR7-LE-NEXT:    addis 4, 2, .LCPI15_0@toc@ha
812; PWR7-LE-NEXT:    addi 4, 4, .LCPI15_0@toc@l
813; PWR7-LE-NEXT:    stw 3, -16(1)
814; PWR7-LE-NEXT:    addi 3, 1, -16
815; PWR7-LE-NEXT:    lxvd2x 0, 0, 4
816; PWR7-LE-NEXT:    addi 4, 1, -32
817; PWR7-LE-NEXT:    lxvd2x 1, 0, 4
818; PWR7-LE-NEXT:    xxswapd 34, 0
819; PWR7-LE-NEXT:    lxvd2x 0, 0, 3
820; PWR7-LE-NEXT:    xxswapd 35, 1
821; PWR7-LE-NEXT:    xxswapd 36, 0
822; PWR7-LE-NEXT:    vperm 2, 4, 3, 2
823; PWR7-LE-NEXT:    blr
824;
825; PWR8-LE-LABEL: build_v4f32_load_3:
826; PWR8-LE:       # %bb.0: # %entry
827; PWR8-LE-NEXT:    lfs 0, 0(3)
828; PWR8-LE-NEXT:    xxlxor 1, 1, 1
829; PWR8-LE-NEXT:    xxmrghd 0, 0, 1
830; PWR8-LE-NEXT:    xxspltd 1, 1, 0
831; PWR8-LE-NEXT:    xvcvdpsp 34, 0
832; PWR8-LE-NEXT:    xvcvdpsp 35, 1
833; PWR8-LE-NEXT:    vmrgew 2, 2, 3
834; PWR8-LE-NEXT:    blr
835entry:
836  %0 = load float, ptr %p, align 4
837  %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 3
838  ret <4 x float> %vecinit1
839}
840