xref: /llvm-project/llvm/test/CodeGen/PowerPC/and-mask.ll (revision 2d9890775f523a7a7ed2d7d064273bf7e28ebf20)
19d1071eaSQingShan Zhang; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
29d1071eaSQingShan Zhang; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
3*2d989077SQiu Chaofan; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s
49d1071eaSQingShan Zhang
59d1071eaSQingShan Zhang; mask 0xFFFFFFFE
69d1071eaSQingShan Zhangdefine i32 @test1(i32 %a) {
79d1071eaSQingShan Zhang; CHECK-LABEL: test1:
89d1071eaSQingShan Zhang; CHECK:       # %bb.0:
9874a8004SQingShan Zhang; CHECK-NEXT:    rlwinm 3, 3, 0, 0, 30
109d1071eaSQingShan Zhang; CHECK-NEXT:    blr
119d1071eaSQingShan Zhang  %and = and i32 %a, -2
129d1071eaSQingShan Zhang  ret i32 %and
139d1071eaSQingShan Zhang}
149d1071eaSQingShan Zhang
159d1071eaSQingShan Zhang; mask 0xFFFFFFFFFFFFFFF9
169d1071eaSQingShan Zhangdefine i64 @test2(i64 %a) {
179d1071eaSQingShan Zhang; CHECK-LABEL: test2:
189d1071eaSQingShan Zhang; CHECK:       # %bb.0:
194bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 61, 2
204bd186c0SQingShan Zhang; CHECK-NEXT:    rotldi 3, 3, 3
219d1071eaSQingShan Zhang; CHECK-NEXT:    blr
229d1071eaSQingShan Zhang  %and = and i64 %a, -7
239d1071eaSQingShan Zhang  ret i64 %and
249d1071eaSQingShan Zhang}
259d1071eaSQingShan Zhang
269d1071eaSQingShan Zhang; mask: 0xFFFFFFC00000
279d1071eaSQingShan Zhangdefine i64 @test3(i64 %a) {
289d1071eaSQingShan Zhang; CHECK-LABEL: test3:
299d1071eaSQingShan Zhang; CHECK:       # %bb.0:
304bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 42, 22
314bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 22, 16
329d1071eaSQingShan Zhang; CHECK-NEXT:    blr
339d1071eaSQingShan Zhang  %and = and i64 %a, 281474972516352
349d1071eaSQingShan Zhang  ret i64 %and
359d1071eaSQingShan Zhang}
369d1071eaSQingShan Zhang
379d1071eaSQingShan Zhang; mask: 0xC000000FF
389d1071eaSQingShan Zhangdefine i64 @test4(i64 %a) {
399d1071eaSQingShan Zhang; CHECK-LABEL: test4:
409d1071eaSQingShan Zhang; CHECK:       # %bb.0:
414bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 30, 26
424bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 34, 28
439d1071eaSQingShan Zhang; CHECK-NEXT:    blr
449d1071eaSQingShan Zhang  %and = and i64 %a, 51539607807
459d1071eaSQingShan Zhang  ret i64 %and
469d1071eaSQingShan Zhang}
479d1071eaSQingShan Zhang
489d1071eaSQingShan Zhang; mask: 0xFFC0FFFF
499d1071eaSQingShan Zhangdefine i64 @test5(i64 %a) {
509d1071eaSQingShan Zhang; CHECK-LABEL: test5:
519d1071eaSQingShan Zhang; CHECK:       # %bb.0:
524bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 42, 6
534bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 22, 32
549d1071eaSQingShan Zhang; CHECK-NEXT:    blr
559d1071eaSQingShan Zhang  %and = and i64 %a, 4290838527
569d1071eaSQingShan Zhang  ret i64 %and
579d1071eaSQingShan Zhang}
589d1071eaSQingShan Zhang
599d1071eaSQingShan Zhang; mask: 0x3FC0FFE0
609d1071eaSQingShan Zhangdefine i64 @test6(i64 %a) {
619d1071eaSQingShan Zhang; CHECK-LABEL: test6:
629d1071eaSQingShan Zhang; CHECK:       # %bb.0:
639d1071eaSQingShan Zhang; CHECK-NEXT:    lis 4, 16320
649d1071eaSQingShan Zhang; CHECK-NEXT:    ori 4, 4, 65504
659d1071eaSQingShan Zhang; CHECK-NEXT:    and 3, 3, 4
669d1071eaSQingShan Zhang; CHECK-NEXT:    blr
679d1071eaSQingShan Zhang  %and = and i64 %a, 1069613024
689d1071eaSQingShan Zhang  ret i64 %and
699d1071eaSQingShan Zhang}
709d1071eaSQingShan Zhang
719d1071eaSQingShan Zhang; mask: 0x3FC000001FFFF
729d1071eaSQingShan Zhangdefine i64 @test7(i64 %a) {
739d1071eaSQingShan Zhang; CHECK-LABEL: test7:
749d1071eaSQingShan Zhang; CHECK:       # %bb.0:
754bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 22, 25
764bd186c0SQingShan Zhang; CHECK-NEXT:    rldicl 3, 3, 42, 14
779d1071eaSQingShan Zhang; CHECK-NEXT:    blr
789d1071eaSQingShan Zhang  %and = and i64 %a, 1121501860462591
799d1071eaSQingShan Zhang  ret i64 %and
809d1071eaSQingShan Zhang}
81