xref: /llvm-project/llvm/test/CodeGen/PowerPC/and-extend-combine.ll (revision 127ed9ae266ead58aa525f74f4c86841f6674793)
1b0e249d5SNemanja Ivanovic; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2b0e249d5SNemanja Ivanovic; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
3b0e249d5SNemanja Ivanovic; RUN:   -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
40ead1faeSNikita Popov
5b0e249d5SNemanja Ivanovicdefine dso_local ptr @foo(i32 noundef zeroext %arg, ptr nocapture noundef readonly %arg1, ptr noundef writeonly %arg2) local_unnamed_addr {
6b0e249d5SNemanja Ivanovic; CHECK-LABEL: foo:
7b0e249d5SNemanja Ivanovic; CHECK:       # %bb.0: # %bb
8b0e249d5SNemanja Ivanovic; CHECK-NEXT:    rlwinm r3, r3, 31, 17, 28
9b922a362SQiu Chaofan; CHECK-NEXT:    ldx r3, r4, r3
10b922a362SQiu Chaofan; CHECK-NEXT:    clrldi r4, r3, 56
11b922a362SQiu Chaofan; CHECK-NEXT:    std r3, 0(r5)
12b922a362SQiu Chaofan; CHECK-NEXT:    add r3, r5, r4
13b0e249d5SNemanja Ivanovic; CHECK-NEXT:    blr
14b0e249d5SNemanja Ivanovicbb:
15b0e249d5SNemanja Ivanovic  %i = lshr i32 %arg, 1
16b0e249d5SNemanja Ivanovic  %i3 = and i32 %i, 32760
17b0e249d5SNemanja Ivanovic  %i4 = zext i32 %i3 to i64
18b0e249d5SNemanja Ivanovic  %i5 = getelementptr inbounds i8, ptr %arg1, i64 %i4
19b0e249d5SNemanja Ivanovic  %i6 = load i64, ptr %i5, align 8
20b0e249d5SNemanja Ivanovic  %i7 = and i64 %i6, 255
21b0e249d5SNemanja Ivanovic  store i64 %i6, ptr %arg2, align 8
22b0e249d5SNemanja Ivanovic  %i8 = getelementptr inbounds i8, ptr %arg2, i64 %i7
23b0e249d5SNemanja Ivanovic  ret ptr %i8
24b0e249d5SNemanja Ivanovic}
250ead1faeSNikita Popov
260ead1faeSNikita Popovdefine void @pr68783(i32 %x, ptr %p) {
270ead1faeSNikita Popov; CHECK-LABEL: pr68783:
280ead1faeSNikita Popov; CHECK:       # %bb.0:
290ead1faeSNikita Popov; CHECK-NEXT:    rlwinm r3, r3, 31, 24, 31
30*127ed9aeSNikita Popov; CHECK-NEXT:    li r5, 0
31*127ed9aeSNikita Popov; CHECK-NEXT:    sth r5, 4(r4)
320ead1faeSNikita Popov; CHECK-NEXT:    stw r3, 0(r4)
330ead1faeSNikita Popov; CHECK-NEXT:    blr
340ead1faeSNikita Popov  %lshr = lshr i32 %x, 1
350ead1faeSNikita Popov  %zext = zext i32 %lshr to i48
360ead1faeSNikita Popov  %and = and i48 %zext, 255
370ead1faeSNikita Popov  store i48 %and, ptr %p
380ead1faeSNikita Popov  ret void
390ead1faeSNikita Popov}
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