xref: /llvm-project/llvm/test/CodeGen/PowerPC/addze.ll (revision abbb894ff58cff160f81954d794d009c3cb92eb9) 
1*abbb894fSQingShan Zhang; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
2*abbb894fSQingShan Zhang; RUN:  -ppc-asm-full-reg-names -mcpu=pwr9 < %s  | FileCheck %s
3*abbb894fSQingShan Zhang; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
4*abbb894fSQingShan Zhang; RUN:  -ppc-asm-full-reg-names -mcpu=pwr9 < %s  | FileCheck %s
5*abbb894fSQingShan Zhang
6*abbb894fSQingShan Zhangdefine i64 @addze1(i64 %X, i64 %Z) {
7*abbb894fSQingShan Zhang; CHECK-LABEL: addze1:
8*abbb894fSQingShan Zhang; CHECK: # %bb.0:
9*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -1
10*abbb894fSQingShan Zhang; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
11*abbb894fSQingShan Zhang; CHECK-NEXT: blr
12*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Z, 0
13*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
14*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
15*abbb894fSQingShan Zhang  ret i64 %add
16*abbb894fSQingShan Zhang}
17*abbb894fSQingShan Zhang
18*abbb894fSQingShan Zhangdefine i64 @addze2(i64 %X, i64 %Z) {
19*abbb894fSQingShan Zhang; CHECK-LABEL: addze2:
20*abbb894fSQingShan Zhang; CHECK: # %bb.0:
21*abbb894fSQingShan Zhang; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 0
22*abbb894fSQingShan Zhang; CHECK-NEXT: addze  [[REG2:r[0-9]+]], [[REG2]]
23*abbb894fSQingShan Zhang; CHECK-NEXT: blr
24*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Z, 0
25*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
26*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
27*abbb894fSQingShan Zhang  ret i64 %add
28*abbb894fSQingShan Zhang}
29*abbb894fSQingShan Zhang
30*abbb894fSQingShan Zhangdefine i64 @addze3(i64 %X, i64 %Z) {
31*abbb894fSQingShan Zhang; CHECK-LABEL: addze3:
32*abbb894fSQingShan Zhang; CHECK: # %bb.0:
33*abbb894fSQingShan Zhang; CHECK-NEXT: addi  [[REG1:r[0-9]+]], [[REG1]], -32768
34*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
35*abbb894fSQingShan Zhang; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
36*abbb894fSQingShan Zhang; CHECK-NEXT: blr
37*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Z, 32768
38*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
39*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
40*abbb894fSQingShan Zhang  ret i64 %add
41*abbb894fSQingShan Zhang}
42*abbb894fSQingShan Zhang
43*abbb894fSQingShan Zhangdefine i64 @addze4(i64 %X, i64 %Z) {
44*abbb894fSQingShan Zhang; CHECK-LABEL: addze4:
45*abbb894fSQingShan Zhang; CHECK: # %bb.0:
46*abbb894fSQingShan Zhang; CHECK-NEXT: addi   [[REG1:r[0-9]+]], [[REG1]], -32768
47*abbb894fSQingShan Zhang; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
48*abbb894fSQingShan Zhang; CHECK-NEXT: addze  [[REG2:r[0-9]+]], [[REG2]]
49*abbb894fSQingShan Zhang; CHECK-NEXT: blr
50*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Z, 32768
51*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
52*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
53*abbb894fSQingShan Zhang  ret i64 %add
54*abbb894fSQingShan Zhang}
55*abbb894fSQingShan Zhang
56*abbb894fSQingShan Zhangdefine i64 @addze5(i64 %X, i64 %Z) {
57*abbb894fSQingShan Zhang; CHECK-LABEL: addze5:
58*abbb894fSQingShan Zhang; CHECK: # %bb.0:
59*abbb894fSQingShan Zhang; CHECK-NEXT: addi  [[REG1:r[0-9]+]], [[REG1]], 32767
60*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
61*abbb894fSQingShan Zhang; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
62*abbb894fSQingShan Zhang; CHECK-NEXT: blr
63*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Z, -32767
64*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
65*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
66*abbb894fSQingShan Zhang  ret i64 %add
67*abbb894fSQingShan Zhang}
68*abbb894fSQingShan Zhang
69*abbb894fSQingShan Zhangdefine i64 @addze6(i64 %X, i64 %Z) {
70*abbb894fSQingShan Zhang; CHECK-LABEL: addze6:
71*abbb894fSQingShan Zhang; CHECK: # %bb.0:
72*abbb894fSQingShan Zhang; CHECK-NEXT: addi   [[REG1:r[0-9]+]], [[REG1]], 32767
73*abbb894fSQingShan Zhang; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
74*abbb894fSQingShan Zhang; CHECK-NEXT: addze  [[REG2:r[0-9]+]], [[REG2]]
75*abbb894fSQingShan Zhang; CHECK-NEXT: blr
76*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Z, -32767
77*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
78*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
79*abbb894fSQingShan Zhang  ret i64 %add
80*abbb894fSQingShan Zhang}
81*abbb894fSQingShan Zhang
82*abbb894fSQingShan Zhang; element is out of range
83*abbb894fSQingShan Zhangdefine i64 @test1(i64 %X, i64 %Z) {
84*abbb894fSQingShan Zhang; CHECK-LABEL: test1:
85*abbb894fSQingShan Zhang; CHECK: # %bb.0:
86*abbb894fSQingShan Zhang; CHECK-NEXT: li    [[REG1:r[0-9]+]], -32768
87*abbb894fSQingShan Zhang; CHECK-NEXT: xor   [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
88*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
89*abbb894fSQingShan Zhang; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
90*abbb894fSQingShan Zhang; CHECK-NEXT: add   [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
91*abbb894fSQingShan Zhang; CHECK-NEXT: blr
92*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Z, -32768
93*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
94*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
95*abbb894fSQingShan Zhang  ret i64 %add
96*abbb894fSQingShan Zhang}
97*abbb894fSQingShan Zhang
98*abbb894fSQingShan Zhangdefine i64 @test2(i64 %X, i64 %Z) {
99*abbb894fSQingShan Zhang; CHECK-LABEL: test2:
100*abbb894fSQingShan Zhang; CHECK: # %bb.0:
101*abbb894fSQingShan Zhang; CHECK-NEXT: li     [[REG1:r[0-9]+]], -32768
102*abbb894fSQingShan Zhang; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
103*abbb894fSQingShan Zhang; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
104*abbb894fSQingShan Zhang; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
105*abbb894fSQingShan Zhang; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
106*abbb894fSQingShan Zhang; CHECK-NEXT: blr
107*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Z, -32768
108*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
109*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
110*abbb894fSQingShan Zhang  ret i64 %add
111*abbb894fSQingShan Zhang}
112*abbb894fSQingShan Zhang
113*abbb894fSQingShan Zhangdefine i64 @test3(i64 %X, i64 %Z) {
114*abbb894fSQingShan Zhang; CHECK-LABEL: test3:
115*abbb894fSQingShan Zhang; CHECK: # %bb.0:
116*abbb894fSQingShan Zhang; CHECK-NEXT: li    [[REG1:r[0-9]+]], 0
117*abbb894fSQingShan Zhang; CHECK-NEXT: ori   [[REG1]], [[REG1]], 32769
118*abbb894fSQingShan Zhang; CHECK-NEXT: xor   [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
119*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
120*abbb894fSQingShan Zhang; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
121*abbb894fSQingShan Zhang; CHECK-NEXT: add   [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
122*abbb894fSQingShan Zhang; CHECK-NEXT: blr
123*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Z, 32769
124*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
125*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
126*abbb894fSQingShan Zhang  ret i64 %add
127*abbb894fSQingShan Zhang}
128*abbb894fSQingShan Zhang
129*abbb894fSQingShan Zhangdefine i64 @test4(i64 %X, i64 %Z) {
130*abbb894fSQingShan Zhang; CHECK-LABEL: test4:
131*abbb894fSQingShan Zhang; CHECK: # %bb.0:
132*abbb894fSQingShan Zhang; CHECK-NEXT: li     [[REG1:r[0-9]+]], 0
133*abbb894fSQingShan Zhang; CHECK-NEXT: ori    [[REG1]], [[REG1]], 32769
134*abbb894fSQingShan Zhang; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
135*abbb894fSQingShan Zhang; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
136*abbb894fSQingShan Zhang; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
137*abbb894fSQingShan Zhang; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
138*abbb894fSQingShan Zhang; CHECK-NEXT: blr
139*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Z, 32769
140*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
141*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
142*abbb894fSQingShan Zhang  ret i64 %add
143*abbb894fSQingShan Zhang}
144*abbb894fSQingShan Zhang
145*abbb894fSQingShan Zhang; comparison of two registers
146*abbb894fSQingShan Zhangdefine i64 @test5(i64 %X, i64 %Y, i64 %Z) {
147*abbb894fSQingShan Zhang; CHECK-LABEL: test5:
148*abbb894fSQingShan Zhang; CHECK: # %bb.0:
149*abbb894fSQingShan Zhang; CHECK-NEXT: xor   [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
150*abbb894fSQingShan Zhang; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
151*abbb894fSQingShan Zhang; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
152*abbb894fSQingShan Zhang; CHECK-NEXT: add   [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
153*abbb894fSQingShan Zhang; CHECK-NEXT: blr
154*abbb894fSQingShan Zhang  %cmp = icmp ne i64 %Y, %Z
155*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
156*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
157*abbb894fSQingShan Zhang  ret i64 %add
158*abbb894fSQingShan Zhang}
159*abbb894fSQingShan Zhang
160*abbb894fSQingShan Zhangdefine i64 @test6(i64 %X, i64 %Y, i64 %Z) {
161*abbb894fSQingShan Zhang; CHECK-LABEL: test6:
162*abbb894fSQingShan Zhang; CHECK: # %bb.0:
163*abbb894fSQingShan Zhang; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
164*abbb894fSQingShan Zhang; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
165*abbb894fSQingShan Zhang; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
166*abbb894fSQingShan Zhang; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
167*abbb894fSQingShan Zhang; CHECK-NEXT: blr
168*abbb894fSQingShan Zhang  %cmp = icmp eq i64 %Y, %Z
169*abbb894fSQingShan Zhang  %conv1 = zext i1 %cmp to i64
170*abbb894fSQingShan Zhang  %add = add nsw i64 %conv1, %X
171*abbb894fSQingShan Zhang  ret i64 %add
172*abbb894fSQingShan Zhang}
173