1*0a9b1c59SChen Zheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*0a9b1c59SChen Zheng 3*0a9b1c59SChen Zheng; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -ppc-vsr-nums-as-vr \ 4*0a9b1c59SChen Zheng; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -o - < %s | FileCheck %s 5*0a9b1c59SChen Zheng 6*0a9b1c59SChen Zhengdefine i64 @fptosi_float_i64(float %i) { 7*0a9b1c59SChen Zheng; CHECK-LABEL: fptosi_float_i64: 8*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 9*0a9b1c59SChen Zheng; CHECK-NEXT: xscvdpsxds f0, f1 10*0a9b1c59SChen Zheng; CHECK-NEXT: mffprd r3, f0 11*0a9b1c59SChen Zheng; CHECK-NEXT: blr 12*0a9b1c59SChen Zhengentry: 13*0a9b1c59SChen Zheng %conv = fptosi float %i to i64 14*0a9b1c59SChen Zheng ret i64 %conv 15*0a9b1c59SChen Zheng} 16*0a9b1c59SChen Zheng 17*0a9b1c59SChen Zhengdefine i64 @fptosi_double_i64(double %i) { 18*0a9b1c59SChen Zheng; CHECK-LABEL: fptosi_double_i64: 19*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 20*0a9b1c59SChen Zheng; CHECK-NEXT: xscvdpsxds f0, f1 21*0a9b1c59SChen Zheng; CHECK-NEXT: mffprd r3, f0 22*0a9b1c59SChen Zheng; CHECK-NEXT: blr 23*0a9b1c59SChen Zhengentry: 24*0a9b1c59SChen Zheng %conv = fptosi double %i to i64 25*0a9b1c59SChen Zheng ret i64 %conv 26*0a9b1c59SChen Zheng} 27*0a9b1c59SChen Zheng 28*0a9b1c59SChen Zhengdefine i64 @fptoui_float_i64(float %i) { 29*0a9b1c59SChen Zheng; CHECK-LABEL: fptoui_float_i64: 30*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 31*0a9b1c59SChen Zheng; CHECK-NEXT: xscvdpuxds f0, f1 32*0a9b1c59SChen Zheng; CHECK-NEXT: mffprd r3, f0 33*0a9b1c59SChen Zheng; CHECK-NEXT: blr 34*0a9b1c59SChen Zhengentry: 35*0a9b1c59SChen Zheng %conv = fptoui float %i to i64 36*0a9b1c59SChen Zheng ret i64 %conv 37*0a9b1c59SChen Zheng} 38*0a9b1c59SChen Zheng 39*0a9b1c59SChen Zhengdefine i64 @fptoui_double_i64(double %i) { 40*0a9b1c59SChen Zheng; CHECK-LABEL: fptoui_double_i64: 41*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 42*0a9b1c59SChen Zheng; CHECK-NEXT: xscvdpuxds f0, f1 43*0a9b1c59SChen Zheng; CHECK-NEXT: mffprd r3, f0 44*0a9b1c59SChen Zheng; CHECK-NEXT: blr 45*0a9b1c59SChen Zhengentry: 46*0a9b1c59SChen Zheng %conv = fptoui double %i to i64 47*0a9b1c59SChen Zheng ret i64 %conv 48*0a9b1c59SChen Zheng} 49*0a9b1c59SChen Zheng 50*0a9b1c59SChen Zhengdefine float @sitofp_i64_float(i64 %i) { 51*0a9b1c59SChen Zheng; CHECK-LABEL: sitofp_i64_float: 52*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 53*0a9b1c59SChen Zheng; CHECK-NEXT: mtfprd f0, r3 54*0a9b1c59SChen Zheng; CHECK-NEXT: xscvsxdsp f1, f0 55*0a9b1c59SChen Zheng; CHECK-NEXT: blr 56*0a9b1c59SChen Zhengentry: 57*0a9b1c59SChen Zheng %conv = sitofp i64 %i to float 58*0a9b1c59SChen Zheng ret float %conv 59*0a9b1c59SChen Zheng} 60*0a9b1c59SChen Zheng 61*0a9b1c59SChen Zhengdefine double @sitofp_i64_double(i64 %i) { 62*0a9b1c59SChen Zheng; CHECK-LABEL: sitofp_i64_double: 63*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 64*0a9b1c59SChen Zheng; CHECK-NEXT: mtfprd f0, r3 65*0a9b1c59SChen Zheng; CHECK-NEXT: xscvsxddp f1, f0 66*0a9b1c59SChen Zheng; CHECK-NEXT: blr 67*0a9b1c59SChen Zhengentry: 68*0a9b1c59SChen Zheng %conv = sitofp i64 %i to double 69*0a9b1c59SChen Zheng ret double %conv 70*0a9b1c59SChen Zheng} 71*0a9b1c59SChen Zheng 72*0a9b1c59SChen Zhengdefine float @uitofp_i64_float(i64 %i) { 73*0a9b1c59SChen Zheng; CHECK-LABEL: uitofp_i64_float: 74*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 75*0a9b1c59SChen Zheng; CHECK-NEXT: mtfprd f0, r3 76*0a9b1c59SChen Zheng; CHECK-NEXT: xscvuxdsp f1, f0 77*0a9b1c59SChen Zheng; CHECK-NEXT: blr 78*0a9b1c59SChen Zhengentry: 79*0a9b1c59SChen Zheng %conv = uitofp i64 %i to float 80*0a9b1c59SChen Zheng ret float %conv 81*0a9b1c59SChen Zheng} 82*0a9b1c59SChen Zheng 83*0a9b1c59SChen Zhengdefine double @uitofp_i64_double(i64 %i) { 84*0a9b1c59SChen Zheng; CHECK-LABEL: uitofp_i64_double: 85*0a9b1c59SChen Zheng; CHECK: # %bb.0: # %entry 86*0a9b1c59SChen Zheng; CHECK-NEXT: mtfprd f0, r3 87*0a9b1c59SChen Zheng; CHECK-NEXT: xscvuxddp f1, f0 88*0a9b1c59SChen Zheng; CHECK-NEXT: blr 89*0a9b1c59SChen Zhengentry: 90*0a9b1c59SChen Zheng %conv = uitofp i64 %i to double 91*0a9b1c59SChen Zheng ret double %conv 92*0a9b1c59SChen Zheng} 93