xref: /llvm-project/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1c88beb41SYunQiang Su; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2*ae26f50aSFangrui Song; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=MIPS32
3*ae26f50aSFangrui Song; RUN: llc -mtriple=mips64 < %s | FileCheck %s --check-prefix=MIPS64
4c88beb41SYunQiang Su
5c88beb41SYunQiang Sudefine dso_local void @read_double(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
6c88beb41SYunQiang Su; MIPS32-LABEL: read_double:
7c88beb41SYunQiang Su; MIPS32:       # %bb.0:
8c88beb41SYunQiang Su; MIPS32-NEXT:    lw $2, 4($4)
9c88beb41SYunQiang Su; MIPS32-NEXT:    lw $3, 0($4)
10c88beb41SYunQiang Su; MIPS32-NEXT:    #APP
11c88beb41SYunQiang Su; MIPS32-NEXT:    #NO_APP
12c88beb41SYunQiang Su; MIPS32-NEXT:    jr $ra
13c88beb41SYunQiang Su; MIPS32-NEXT:    nop
14c88beb41SYunQiang Su;
15c88beb41SYunQiang Su; MIPS64-LABEL: read_double:
16c88beb41SYunQiang Su; MIPS64:       # %bb.0:
17c88beb41SYunQiang Su; MIPS64-NEXT:    ld $2, 0($4)
18c88beb41SYunQiang Su; MIPS64-NEXT:    #APP
19c88beb41SYunQiang Su; MIPS64-NEXT:    #NO_APP
20c88beb41SYunQiang Su; MIPS64-NEXT:    jr $ra
21c88beb41SYunQiang Su; MIPS64-NEXT:    nop
22c88beb41SYunQiang Su  %2 = load double, ptr %0, align 8
23c88beb41SYunQiang Su  tail call void asm sideeffect "", "r,~{$1}"(double %2)
24c88beb41SYunQiang Su  ret void
25c88beb41SYunQiang Su}
26c88beb41SYunQiang Su
27c88beb41SYunQiang Sudefine dso_local void @read_float(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
28c88beb41SYunQiang Su; MIPS32-LABEL: read_float:
29c88beb41SYunQiang Su; MIPS32:       # %bb.0:
30c88beb41SYunQiang Su; MIPS32-NEXT:    lw $2, 0($4)
31c88beb41SYunQiang Su; MIPS32-NEXT:    #APP
32c88beb41SYunQiang Su; MIPS32-NEXT:    #NO_APP
33c88beb41SYunQiang Su; MIPS32-NEXT:    jr $ra
34c88beb41SYunQiang Su; MIPS32-NEXT:    nop
35c88beb41SYunQiang Su;
36c88beb41SYunQiang Su; MIPS64-LABEL: read_float:
37c88beb41SYunQiang Su; MIPS64:       # %bb.0:
38c88beb41SYunQiang Su; MIPS64-NEXT:    lw $2, 0($4)
39c88beb41SYunQiang Su; MIPS64-NEXT:    #APP
40c88beb41SYunQiang Su; MIPS64-NEXT:    #NO_APP
41c88beb41SYunQiang Su; MIPS64-NEXT:    jr $ra
42c88beb41SYunQiang Su; MIPS64-NEXT:    nop
43c88beb41SYunQiang Su  %2 = load float, ptr %0, align 8
44c88beb41SYunQiang Su  tail call void asm sideeffect "", "r,~{$1}"(float %2)
45c88beb41SYunQiang Su  ret void
46c88beb41SYunQiang Su}
47c88beb41SYunQiang Su
48c88beb41SYunQiang Suattributes #0 = { "target-features"="+soft-float" "use-soft-float"="true" }
49