1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32 3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64 4--- | 5 6 define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) { 7 entry: 8 br i1 %cnd, label %cond.true, label %cond.false 9 10 cond.true: ; preds = %entry 11 br label %cond.end 12 13 cond.false: ; preds = %entry 14 br label %cond.end 15 16 cond.end: ; preds = %cond.false, %cond.true 17 %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ] 18 ret i32 %cond 19 } 20 21 define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) { 22 entry: 23 br i1 %cnd, label %cond.true, label %cond.false 24 25 cond.true: ; preds = %entry 26 br label %cond.end 27 28 cond.false: ; preds = %entry 29 br label %cond.end 30 31 cond.end: ; preds = %cond.false, %cond.true 32 %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ] 33 ret i64 %cond 34 } 35 36 define float @phi_float(i1 %cnd, float %a, float %b) { 37 entry: 38 br i1 %cnd, label %cond.true, label %cond.false 39 40 cond.true: ; preds = %entry 41 br label %cond.end 42 43 cond.false: ; preds = %entry 44 br label %cond.end 45 46 cond.end: ; preds = %cond.false, %cond.true 47 %cond = phi float [ %a, %cond.true ], [ %b, %cond.false ] 48 ret float %cond 49 } 50 51 define double @phi_double(double %a, double %b, i1 %cnd) { 52 entry: 53 br i1 %cnd, label %cond.true, label %cond.false 54 55 cond.true: ; preds = %entry 56 br label %cond.end 57 58 cond.false: ; preds = %entry 59 br label %cond.end 60 61 cond.end: ; preds = %cond.false, %cond.true 62 %cond = phi double [ %a, %cond.true ], [ %b, %cond.false ] 63 ret double %cond 64 } 65 66... 67--- 68name: phi_i32 69alignment: 4 70legalized: true 71regBankSelected: true 72tracksRegLiveness: true 73body: | 74 ; MIPS32FP32-LABEL: name: phi_i32 75 ; MIPS32FP32: bb.0.entry: 76 ; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 77 ; MIPS32FP32-NEXT: liveins: $a0, $a1, $a2 78 ; MIPS32FP32-NEXT: {{ $}} 79 ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 80 ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 81 ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 82 ; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 83 ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 84 ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at 85 ; MIPS32FP32-NEXT: {{ $}} 86 ; MIPS32FP32-NEXT: bb.1.cond.true: 87 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 88 ; MIPS32FP32-NEXT: {{ $}} 89 ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at 90 ; MIPS32FP32-NEXT: {{ $}} 91 ; MIPS32FP32-NEXT: bb.2.cond.false: 92 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 93 ; MIPS32FP32-NEXT: {{ $}} 94 ; MIPS32FP32-NEXT: bb.3.cond.end: 95 ; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 96 ; MIPS32FP32-NEXT: $v0 = COPY [[PHI]] 97 ; MIPS32FP32-NEXT: RetRA implicit $v0 98 ; 99 ; MIPS32FP64-LABEL: name: phi_i32 100 ; MIPS32FP64: bb.0.entry: 101 ; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 102 ; MIPS32FP64-NEXT: liveins: $a0, $a1, $a2 103 ; MIPS32FP64-NEXT: {{ $}} 104 ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 105 ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 106 ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 107 ; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 108 ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 109 ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at 110 ; MIPS32FP64-NEXT: {{ $}} 111 ; MIPS32FP64-NEXT: bb.1.cond.true: 112 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 113 ; MIPS32FP64-NEXT: {{ $}} 114 ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at 115 ; MIPS32FP64-NEXT: {{ $}} 116 ; MIPS32FP64-NEXT: bb.2.cond.false: 117 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 118 ; MIPS32FP64-NEXT: {{ $}} 119 ; MIPS32FP64-NEXT: bb.3.cond.end: 120 ; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 121 ; MIPS32FP64-NEXT: $v0 = COPY [[PHI]] 122 ; MIPS32FP64-NEXT: RetRA implicit $v0 123 bb.1.entry: 124 liveins: $a0, $a1, $a2 125 126 %3:gprb(s32) = COPY $a0 127 %1:gprb(s32) = COPY $a1 128 %2:gprb(s32) = COPY $a2 129 %6:gprb(s32) = G_CONSTANT i32 1 130 %7:gprb(s32) = COPY %3(s32) 131 %5:gprb(s32) = G_AND %7, %6 132 G_BRCOND %5(s32), %bb.2 133 G_BR %bb.3 134 135 bb.2.cond.true: 136 G_BR %bb.4 137 138 bb.3.cond.false: 139 140 bb.4.cond.end: 141 %4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3 142 $v0 = COPY %4(s32) 143 RetRA implicit $v0 144 145... 146--- 147name: phi_i64 148alignment: 4 149legalized: true 150regBankSelected: true 151tracksRegLiveness: true 152fixedStack: 153 - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true } 154 - { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true } 155body: | 156 ; MIPS32FP32-LABEL: name: phi_i64 157 ; MIPS32FP32: bb.0.entry: 158 ; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 159 ; MIPS32FP32-NEXT: liveins: $a0, $a2, $a3 160 ; MIPS32FP32-NEXT: {{ $}} 161 ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 162 ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2 163 ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3 164 ; MIPS32FP32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 165 ; MIPS32FP32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8) 166 ; MIPS32FP32-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0 167 ; MIPS32FP32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1) 168 ; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 169 ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 170 ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at 171 ; MIPS32FP32-NEXT: {{ $}} 172 ; MIPS32FP32-NEXT: bb.1.cond.true: 173 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 174 ; MIPS32FP32-NEXT: {{ $}} 175 ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at 176 ; MIPS32FP32-NEXT: {{ $}} 177 ; MIPS32FP32-NEXT: bb.2.cond.false: 178 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 179 ; MIPS32FP32-NEXT: {{ $}} 180 ; MIPS32FP32-NEXT: bb.3.cond.end: 181 ; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2 182 ; MIPS32FP32-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2 183 ; MIPS32FP32-NEXT: $v0 = COPY [[PHI]] 184 ; MIPS32FP32-NEXT: $v1 = COPY [[PHI1]] 185 ; MIPS32FP32-NEXT: RetRA implicit $v0, implicit $v1 186 ; 187 ; MIPS32FP64-LABEL: name: phi_i64 188 ; MIPS32FP64: bb.0.entry: 189 ; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 190 ; MIPS32FP64-NEXT: liveins: $a0, $a2, $a3 191 ; MIPS32FP64-NEXT: {{ $}} 192 ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 193 ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2 194 ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3 195 ; MIPS32FP64-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 196 ; MIPS32FP64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8) 197 ; MIPS32FP64-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0 198 ; MIPS32FP64-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1) 199 ; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 200 ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 201 ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at 202 ; MIPS32FP64-NEXT: {{ $}} 203 ; MIPS32FP64-NEXT: bb.1.cond.true: 204 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 205 ; MIPS32FP64-NEXT: {{ $}} 206 ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at 207 ; MIPS32FP64-NEXT: {{ $}} 208 ; MIPS32FP64-NEXT: bb.2.cond.false: 209 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 210 ; MIPS32FP64-NEXT: {{ $}} 211 ; MIPS32FP64-NEXT: bb.3.cond.end: 212 ; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2 213 ; MIPS32FP64-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2 214 ; MIPS32FP64-NEXT: $v0 = COPY [[PHI]] 215 ; MIPS32FP64-NEXT: $v1 = COPY [[PHI1]] 216 ; MIPS32FP64-NEXT: RetRA implicit $v0, implicit $v1 217 bb.1.entry: 218 liveins: $a0, $a2, $a3 219 220 %3:gprb(s32) = COPY $a0 221 %4:gprb(s32) = COPY $a2 222 %5:gprb(s32) = COPY $a3 223 %8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1 224 %6:gprb(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8) 225 %9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0 226 %7:gprb(s32) = G_LOAD %9(p0) :: (load (s32) from %fixed-stack.0) 227 %14:gprb(s32) = G_CONSTANT i32 1 228 %15:gprb(s32) = COPY %3(s32) 229 %13:gprb(s32) = G_AND %15, %14 230 G_BRCOND %13(s32), %bb.2 231 G_BR %bb.3 232 233 bb.2.cond.true: 234 G_BR %bb.4 235 236 bb.3.cond.false: 237 238 bb.4.cond.end: 239 %20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3 240 %21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3 241 $v0 = COPY %20(s32) 242 $v1 = COPY %21(s32) 243 RetRA implicit $v0, implicit $v1 244 245... 246--- 247name: phi_float 248alignment: 4 249legalized: true 250regBankSelected: true 251tracksRegLiveness: true 252body: | 253 ; MIPS32FP32-LABEL: name: phi_float 254 ; MIPS32FP32: bb.0.entry: 255 ; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 256 ; MIPS32FP32-NEXT: liveins: $a0, $a1, $a2 257 ; MIPS32FP32-NEXT: {{ $}} 258 ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 259 ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 260 ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 261 ; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 262 ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 263 ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at 264 ; MIPS32FP32-NEXT: {{ $}} 265 ; MIPS32FP32-NEXT: bb.1.cond.true: 266 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 267 ; MIPS32FP32-NEXT: {{ $}} 268 ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at 269 ; MIPS32FP32-NEXT: {{ $}} 270 ; MIPS32FP32-NEXT: bb.2.cond.false: 271 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 272 ; MIPS32FP32-NEXT: {{ $}} 273 ; MIPS32FP32-NEXT: bb.3.cond.end: 274 ; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 275 ; MIPS32FP32-NEXT: $f0 = COPY [[PHI]] 276 ; MIPS32FP32-NEXT: RetRA implicit $f0 277 ; 278 ; MIPS32FP64-LABEL: name: phi_float 279 ; MIPS32FP64: bb.0.entry: 280 ; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 281 ; MIPS32FP64-NEXT: liveins: $a0, $a1, $a2 282 ; MIPS32FP64-NEXT: {{ $}} 283 ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 284 ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 285 ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 286 ; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1 287 ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 288 ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at 289 ; MIPS32FP64-NEXT: {{ $}} 290 ; MIPS32FP64-NEXT: bb.1.cond.true: 291 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 292 ; MIPS32FP64-NEXT: {{ $}} 293 ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at 294 ; MIPS32FP64-NEXT: {{ $}} 295 ; MIPS32FP64-NEXT: bb.2.cond.false: 296 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 297 ; MIPS32FP64-NEXT: {{ $}} 298 ; MIPS32FP64-NEXT: bb.3.cond.end: 299 ; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 300 ; MIPS32FP64-NEXT: $f0 = COPY [[PHI]] 301 ; MIPS32FP64-NEXT: RetRA implicit $f0 302 bb.1.entry: 303 liveins: $a0, $a1, $a2 304 305 %3:gprb(s32) = COPY $a0 306 %1:gprb(s32) = COPY $a1 307 %2:gprb(s32) = COPY $a2 308 %6:gprb(s32) = G_CONSTANT i32 1 309 %7:gprb(s32) = COPY %3(s32) 310 %5:gprb(s32) = G_AND %7, %6 311 G_BRCOND %5(s32), %bb.2 312 G_BR %bb.3 313 314 bb.2.cond.true: 315 G_BR %bb.4 316 317 bb.3.cond.false: 318 319 bb.4.cond.end: 320 %4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3 321 $f0 = COPY %4(s32) 322 RetRA implicit $f0 323 324... 325--- 326name: phi_double 327alignment: 4 328legalized: true 329regBankSelected: true 330tracksRegLiveness: true 331fixedStack: 332 - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true } 333body: | 334 ; MIPS32FP32-LABEL: name: phi_double 335 ; MIPS32FP32: bb.0.entry: 336 ; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 337 ; MIPS32FP32-NEXT: liveins: $d6, $d7 338 ; MIPS32FP32-NEXT: {{ $}} 339 ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 340 ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 341 ; MIPS32FP32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 342 ; MIPS32FP32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8) 343 ; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 344 ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 345 ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at 346 ; MIPS32FP32-NEXT: {{ $}} 347 ; MIPS32FP32-NEXT: bb.1.cond.true: 348 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 349 ; MIPS32FP32-NEXT: {{ $}} 350 ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at 351 ; MIPS32FP32-NEXT: {{ $}} 352 ; MIPS32FP32-NEXT: bb.2.cond.false: 353 ; MIPS32FP32-NEXT: successors: %bb.3(0x80000000) 354 ; MIPS32FP32-NEXT: {{ $}} 355 ; MIPS32FP32-NEXT: bb.3.cond.end: 356 ; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2 357 ; MIPS32FP32-NEXT: $d0 = COPY [[PHI]] 358 ; MIPS32FP32-NEXT: RetRA implicit $d0 359 ; 360 ; MIPS32FP64-LABEL: name: phi_double 361 ; MIPS32FP64: bb.0.entry: 362 ; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 363 ; MIPS32FP64-NEXT: liveins: $d6, $d7 364 ; MIPS32FP64-NEXT: {{ $}} 365 ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 366 ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 367 ; MIPS32FP64-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0 368 ; MIPS32FP64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8) 369 ; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1 370 ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at 371 ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at 372 ; MIPS32FP64-NEXT: {{ $}} 373 ; MIPS32FP64-NEXT: bb.1.cond.true: 374 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 375 ; MIPS32FP64-NEXT: {{ $}} 376 ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at 377 ; MIPS32FP64-NEXT: {{ $}} 378 ; MIPS32FP64-NEXT: bb.2.cond.false: 379 ; MIPS32FP64-NEXT: successors: %bb.3(0x80000000) 380 ; MIPS32FP64-NEXT: {{ $}} 381 ; MIPS32FP64-NEXT: bb.3.cond.end: 382 ; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2 383 ; MIPS32FP64-NEXT: $d0 = COPY [[PHI]] 384 ; MIPS32FP64-NEXT: RetRA implicit $d0 385 bb.1.entry: 386 liveins: $d6, $d7 387 388 %0:fprb(s64) = COPY $d6 389 %1:fprb(s64) = COPY $d7 390 %4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0 391 %3:gprb(s32) = G_LOAD %4(p0) :: (load (s32) from %fixed-stack.0, align 8) 392 %7:gprb(s32) = G_CONSTANT i32 1 393 %8:gprb(s32) = COPY %3(s32) 394 %6:gprb(s32) = G_AND %8, %7 395 G_BRCOND %6(s32), %bb.2 396 G_BR %bb.3 397 398 bb.2.cond.true: 399 G_BR %bb.4 400 401 bb.3.cond.false: 402 403 bb.4.cond.end: 404 %5:fprb(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3 405 $d0 = COPY %5(s64) 406 RetRA implicit $d0 407 408... 409