xref: /llvm-project/llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.ll (revision 1c6b0f779f66494cb597884c1a52e377bde4bc54)
139584ae5SXiang1 Zhang; RUN: llc -debugify-check-and-strip-all-safe -o - %s 2>&1 | FileCheck %s
2*1c6b0f77SStephen Tozer; RUN: llc --experimental-debuginfo-iterators=false -debugify-check-and-strip-all-safe -o - %s 2>&1 | FileCheck %s
339584ae5SXiang1 Zhang
439584ae5SXiang1 Zhang; ModuleID = 'main.c'
539584ae5SXiang1 Zhangsource_filename = "main.c"
639584ae5SXiang1 Zhang
739584ae5SXiang1 Zhang@ga = dso_local global i32 2, align 4
839584ae5SXiang1 Zhang
939584ae5SXiang1 Zhangdefine dso_local i32 @foo(i32 %a, i32 %b) {
1039584ae5SXiang1 Zhangentry:
1139584ae5SXiang1 Zhang  %a.addr = alloca i32, align 4
1239584ae5SXiang1 Zhang  %b.addr = alloca i32, align 4
1339584ae5SXiang1 Zhang  %c = alloca i32, align 4
140e8bd5a4SNikita Popov  store i32 %a, ptr %a.addr, align 4
150e8bd5a4SNikita Popov  store i32 %b, ptr %b.addr, align 4
160e8bd5a4SNikita Popov  %0 = load i32, ptr %a.addr, align 4
170e8bd5a4SNikita Popov  %1 = load i32, ptr %b.addr, align 4
1839584ae5SXiang1 Zhang  %add = add nsw i32 %0, %1
190e8bd5a4SNikita Popov  store i32 %add, ptr %c, align 4
200e8bd5a4SNikita Popov  %2 = load i32, ptr %c, align 4
2139584ae5SXiang1 Zhang  %mul = mul nsw i32 %2, 2
220e8bd5a4SNikita Popov  store i32 %mul, ptr @ga, align 4
230e8bd5a4SNikita Popov  %3 = load i32, ptr %c, align 4
2439584ae5SXiang1 Zhang  ret i32 %3
2539584ae5SXiang1 Zhang}
2639584ae5SXiang1 Zhang
2739584ae5SXiang1 Zhang; Different Back-Ends may have different number of passes, here we only
2839584ae5SXiang1 Zhang; check two of them to make sure -debugify-check-and-strip-all-safe works.
2939584ae5SXiang1 Zhang;CHECK: Machine IR debug info check: PASS
3039584ae5SXiang1 Zhang;CHECK: Machine IR debug info check: PASS
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