1*380bb51bSjoaosaffran; RUN: opt -S -dxil-op-lower -dxil-translate-metadata -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s 2*380bb51bSjoaosaffran 3*380bb51bSjoaosaffran; This test make sure LLVM metadata is being translated into DXIL. 4*380bb51bSjoaosaffran 5*380bb51bSjoaosaffran 6*380bb51bSjoaosaffran; CHECK: define i32 @test_branch(i32 %X) 7*380bb51bSjoaosaffran; CHECK-NOT: hlsl.controlflow.hint 8*380bb51bSjoaosaffran; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_BRANCH:![0-9]+]] 9*380bb51bSjoaosaffrandefine i32 @test_branch(i32 %X) { 10*380bb51bSjoaosaffranentry: 11*380bb51bSjoaosaffran %X.addr = alloca i32, align 4 12*380bb51bSjoaosaffran %resp = alloca i32, align 4 13*380bb51bSjoaosaffran store i32 %X, ptr %X.addr, align 4 14*380bb51bSjoaosaffran %0 = load i32, ptr %X.addr, align 4 15*380bb51bSjoaosaffran %cmp = icmp sgt i32 %0, 0 16*380bb51bSjoaosaffran br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0 17*380bb51bSjoaosaffran 18*380bb51bSjoaosaffranif.then: ; preds = %entry 19*380bb51bSjoaosaffran %1 = load i32, ptr %X.addr, align 4 20*380bb51bSjoaosaffran %sub = sub nsw i32 0, %1 21*380bb51bSjoaosaffran store i32 %sub, ptr %resp, align 4 22*380bb51bSjoaosaffran br label %if.end 23*380bb51bSjoaosaffran 24*380bb51bSjoaosaffranif.else: ; preds = %entry 25*380bb51bSjoaosaffran %2 = load i32, ptr %X.addr, align 4 26*380bb51bSjoaosaffran %mul = mul nsw i32 %2, 2 27*380bb51bSjoaosaffran store i32 %mul, ptr %resp, align 4 28*380bb51bSjoaosaffran br label %if.end 29*380bb51bSjoaosaffran 30*380bb51bSjoaosaffranif.end: ; preds = %if.else, %if.then 31*380bb51bSjoaosaffran %3 = load i32, ptr %resp, align 4 32*380bb51bSjoaosaffran ret i32 %3 33*380bb51bSjoaosaffran} 34*380bb51bSjoaosaffran 35*380bb51bSjoaosaffran 36*380bb51bSjoaosaffran; CHECK: define i32 @test_flatten(i32 %X) 37*380bb51bSjoaosaffran; CHECK-NOT: hlsl.controlflow.hint 38*380bb51bSjoaosaffran; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_FLATTEN:![0-9]+]] 39*380bb51bSjoaosaffrandefine i32 @test_flatten(i32 %X) { 40*380bb51bSjoaosaffranentry: 41*380bb51bSjoaosaffran %X.addr = alloca i32, align 4 42*380bb51bSjoaosaffran %resp = alloca i32, align 4 43*380bb51bSjoaosaffran store i32 %X, ptr %X.addr, align 4 44*380bb51bSjoaosaffran %0 = load i32, ptr %X.addr, align 4 45*380bb51bSjoaosaffran %cmp = icmp sgt i32 %0, 0 46*380bb51bSjoaosaffran br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1 47*380bb51bSjoaosaffran 48*380bb51bSjoaosaffranif.then: ; preds = %entry 49*380bb51bSjoaosaffran %1 = load i32, ptr %X.addr, align 4 50*380bb51bSjoaosaffran %sub = sub nsw i32 0, %1 51*380bb51bSjoaosaffran store i32 %sub, ptr %resp, align 4 52*380bb51bSjoaosaffran br label %if.end 53*380bb51bSjoaosaffran 54*380bb51bSjoaosaffranif.else: ; preds = %entry 55*380bb51bSjoaosaffran %2 = load i32, ptr %X.addr, align 4 56*380bb51bSjoaosaffran %mul = mul nsw i32 %2, 2 57*380bb51bSjoaosaffran store i32 %mul, ptr %resp, align 4 58*380bb51bSjoaosaffran br label %if.end 59*380bb51bSjoaosaffran 60*380bb51bSjoaosaffranif.end: ; preds = %if.else, %if.then 61*380bb51bSjoaosaffran %3 = load i32, ptr %resp, align 4 62*380bb51bSjoaosaffran ret i32 %3 63*380bb51bSjoaosaffran} 64*380bb51bSjoaosaffran 65*380bb51bSjoaosaffran 66*380bb51bSjoaosaffran; CHECK: define i32 @test_no_attr(i32 %X) 67*380bb51bSjoaosaffran; CHECK-NOT: hlsl.controlflow.hint 68*380bb51bSjoaosaffran; CHECK-NOT: !dx.controlflow.hints 69*380bb51bSjoaosaffrandefine i32 @test_no_attr(i32 %X) { 70*380bb51bSjoaosaffranentry: 71*380bb51bSjoaosaffran %X.addr = alloca i32, align 4 72*380bb51bSjoaosaffran %resp = alloca i32, align 4 73*380bb51bSjoaosaffran store i32 %X, ptr %X.addr, align 4 74*380bb51bSjoaosaffran %0 = load i32, ptr %X.addr, align 4 75*380bb51bSjoaosaffran %cmp = icmp sgt i32 %0, 0 76*380bb51bSjoaosaffran br i1 %cmp, label %if.then, label %if.else 77*380bb51bSjoaosaffran 78*380bb51bSjoaosaffranif.then: ; preds = %entry 79*380bb51bSjoaosaffran %1 = load i32, ptr %X.addr, align 4 80*380bb51bSjoaosaffran %sub = sub nsw i32 0, %1 81*380bb51bSjoaosaffran store i32 %sub, ptr %resp, align 4 82*380bb51bSjoaosaffran br label %if.end 83*380bb51bSjoaosaffran 84*380bb51bSjoaosaffranif.else: ; preds = %entry 85*380bb51bSjoaosaffran %2 = load i32, ptr %X.addr, align 4 86*380bb51bSjoaosaffran %mul = mul nsw i32 %2, 2 87*380bb51bSjoaosaffran store i32 %mul, ptr %resp, align 4 88*380bb51bSjoaosaffran br label %if.end 89*380bb51bSjoaosaffran 90*380bb51bSjoaosaffranif.end: ; preds = %if.else, %if.then 91*380bb51bSjoaosaffran %3 = load i32, ptr %resp, align 4 92*380bb51bSjoaosaffran ret i32 %3 93*380bb51bSjoaosaffran} 94*380bb51bSjoaosaffran; CHECK-NOT: hlsl.controlflow.hint 95*380bb51bSjoaosaffran; CHECK: [[HINT_BRANCH]] = !{!"dx.controlflow.hints", i32 1} 96*380bb51bSjoaosaffran; CHECK: [[HINT_FLATTEN]] = !{!"dx.controlflow.hints", i32 2} 97*380bb51bSjoaosaffran!0 = !{!"hlsl.controlflow.hint", i32 1} 98*380bb51bSjoaosaffran!1 = !{!"hlsl.controlflow.hint", i32 2} 99