xref: /llvm-project/llvm/test/CodeGen/CSKY/rotl.ll (revision a556ec8861df920bfaee3057df8aac739aa59b24)
1*a556ec88SZi Xuan Wu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2*a556ec88SZi Xuan Wu; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
3*a556ec88SZi Xuan Wu
4*a556ec88SZi Xuan Wudefine i32 @ROTLI32(i32 %x) {
5*a556ec88SZi Xuan Wu; CHECK-LABEL: ROTLI32:
6*a556ec88SZi Xuan Wu; CHECK:       # %bb.0: # %entry
7*a556ec88SZi Xuan Wu; CHECK-NEXT:    rotli32 a0, a0, 4
8*a556ec88SZi Xuan Wu; CHECK-NEXT:    rts16
9*a556ec88SZi Xuan Wuentry:
10*a556ec88SZi Xuan Wu  %shl = shl i32 %x, 4
11*a556ec88SZi Xuan Wu  %shr = lshr i32 %x, 28
12*a556ec88SZi Xuan Wu  %or = or i32 %shl, %shr
13*a556ec88SZi Xuan Wu  ret i32 %or
14*a556ec88SZi Xuan Wu}
15*a556ec88SZi Xuan Wu
16*a556ec88SZi Xuan Wudefine i32 @ROTL32(i32 %x, i32 %y) {
17*a556ec88SZi Xuan Wu; CHECK-LABEL: ROTL32:
18*a556ec88SZi Xuan Wu; CHECK:       # %bb.0: # %entry
19*a556ec88SZi Xuan Wu; CHECK-NEXT:    andi32 a1, a1, 31
20*a556ec88SZi Xuan Wu; CHECK-NEXT:    rotl16 a0, a1
21*a556ec88SZi Xuan Wu; CHECK-NEXT:    rts16
22*a556ec88SZi Xuan Wuentry:
23*a556ec88SZi Xuan Wu  %0 = shl i32 %x, %y
24*a556ec88SZi Xuan Wu  %1 = sub i32 32, %y
25*a556ec88SZi Xuan Wu  %2 = lshr i32 %x, %1
26*a556ec88SZi Xuan Wu  %3 = or i32 %2, %0
27*a556ec88SZi Xuan Wu  ret i32 %3
28*a556ec88SZi Xuan Wu}
29