xref: /llvm-project/llvm/test/CodeGen/CSKY/fpu/select.ll (revision 70b8b738c5794799e9807549e5058d9570176918)
1208f93c1SZi Xuan Wu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2208f93c1SZi Xuan Wu; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
3208f93c1SZi Xuan Wu; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
4*70b8b738SZi Xuan Wu (Zeson); RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
5208f93c1SZi Xuan Wu
6208f93c1SZi Xuan Wudefine float @selectRR_eq_float(i1 %x, float %n, float %m) {
7208f93c1SZi Xuan Wu; CHECK-LABEL: selectRR_eq_float:
8208f93c1SZi Xuan Wu; CHECK:       # %bb.0: # %entry
9*70b8b738SZi Xuan Wu (Zeson); CHECK-NEXT:    btsti16 a0, 0
10208f93c1SZi Xuan Wu; CHECK-NEXT:    bt32 .LBB0_2
11208f93c1SZi Xuan Wu; CHECK-NEXT:  # %bb.1: # %entry
12208f93c1SZi Xuan Wu; CHECK-NEXT:    fmovs vr1, vr0
13208f93c1SZi Xuan Wu; CHECK-NEXT:  .LBB0_2: # %entry
14208f93c1SZi Xuan Wu; CHECK-NEXT:    fmovs vr0, vr1
15208f93c1SZi Xuan Wu; CHECK-NEXT:    rts16
16208f93c1SZi Xuan Wu;
17208f93c1SZi Xuan Wu; CHECK-DF3-LABEL: selectRR_eq_float:
18208f93c1SZi Xuan Wu; CHECK-DF3:       # %bb.0: # %entry
19*70b8b738SZi Xuan Wu (Zeson); CHECK-DF3-NEXT:    btsti16 a0, 0
20208f93c1SZi Xuan Wu; CHECK-DF3-NEXT:    fsel.32 vr0, vr1, vr0
21208f93c1SZi Xuan Wu; CHECK-DF3-NEXT:    rts16
22208f93c1SZi Xuan Wu;
23208f93c1SZi Xuan Wu; GENERIC-LABEL: selectRR_eq_float:
24208f93c1SZi Xuan Wu; GENERIC:       # %bb.0: # %entry
25208f93c1SZi Xuan Wu; GENERIC-NEXT:    .cfi_def_cfa_offset 0
26208f93c1SZi Xuan Wu; GENERIC-NEXT:    subi16 sp, sp, 4
27208f93c1SZi Xuan Wu; GENERIC-NEXT:    .cfi_def_cfa_offset 4
28208f93c1SZi Xuan Wu; GENERIC-NEXT:    btsti16 a0, 0
29208f93c1SZi Xuan Wu; GENERIC-NEXT:    bt16 .LBB0_2
30208f93c1SZi Xuan Wu; GENERIC-NEXT:  # %bb.1: # %entry
31208f93c1SZi Xuan Wu; GENERIC-NEXT:    fmovs vr1, vr0
32208f93c1SZi Xuan Wu; GENERIC-NEXT:  .LBB0_2: # %entry
33208f93c1SZi Xuan Wu; GENERIC-NEXT:    fmovs vr0, vr1
34208f93c1SZi Xuan Wu; GENERIC-NEXT:    addi16 sp, sp, 4
35208f93c1SZi Xuan Wu; GENERIC-NEXT:    rts16
36208f93c1SZi Xuan Wuentry:
37208f93c1SZi Xuan Wu  %ret = select i1 %x, float %m, float %n
38208f93c1SZi Xuan Wu  ret float %ret
39208f93c1SZi Xuan Wu}
40208f93c1SZi Xuan Wu
41208f93c1SZi Xuan Wudefine double @selectRR_eq_double(i1 %x, double %n, double %m) {
42208f93c1SZi Xuan Wu; CHECK-LABEL: selectRR_eq_double:
43208f93c1SZi Xuan Wu; CHECK:       # %bb.0: # %entry
44*70b8b738SZi Xuan Wu (Zeson); CHECK-NEXT:    btsti16 a0, 0
45208f93c1SZi Xuan Wu; CHECK-NEXT:    bt32 .LBB1_2
46208f93c1SZi Xuan Wu; CHECK-NEXT:  # %bb.1: # %entry
47208f93c1SZi Xuan Wu; CHECK-NEXT:    fmovd vr1, vr0
48208f93c1SZi Xuan Wu; CHECK-NEXT:  .LBB1_2: # %entry
49208f93c1SZi Xuan Wu; CHECK-NEXT:    fmovd vr0, vr1
50208f93c1SZi Xuan Wu; CHECK-NEXT:    rts16
51208f93c1SZi Xuan Wu;
52208f93c1SZi Xuan Wu; CHECK-DF3-LABEL: selectRR_eq_double:
53208f93c1SZi Xuan Wu; CHECK-DF3:       # %bb.0: # %entry
54*70b8b738SZi Xuan Wu (Zeson); CHECK-DF3-NEXT:    btsti16 a0, 0
55208f93c1SZi Xuan Wu; CHECK-DF3-NEXT:    fsel.64 vr0, vr1, vr0
56208f93c1SZi Xuan Wu; CHECK-DF3-NEXT:    rts16
57208f93c1SZi Xuan Wu;
58208f93c1SZi Xuan Wu; GENERIC-LABEL: selectRR_eq_double:
59208f93c1SZi Xuan Wu; GENERIC:       # %bb.0: # %entry
60208f93c1SZi Xuan Wu; GENERIC-NEXT:    .cfi_def_cfa_offset 0
61208f93c1SZi Xuan Wu; GENERIC-NEXT:    subi16 sp, sp, 4
62208f93c1SZi Xuan Wu; GENERIC-NEXT:    .cfi_def_cfa_offset 4
63208f93c1SZi Xuan Wu; GENERIC-NEXT:    btsti16 a0, 0
64208f93c1SZi Xuan Wu; GENERIC-NEXT:    bt16 .LBB1_2
65208f93c1SZi Xuan Wu; GENERIC-NEXT:  # %bb.1: # %entry
66208f93c1SZi Xuan Wu; GENERIC-NEXT:    fmovd vr1, vr0
67208f93c1SZi Xuan Wu; GENERIC-NEXT:  .LBB1_2: # %entry
68208f93c1SZi Xuan Wu; GENERIC-NEXT:    fmovd vr0, vr1
69208f93c1SZi Xuan Wu; GENERIC-NEXT:    addi16 sp, sp, 4
70208f93c1SZi Xuan Wu; GENERIC-NEXT:    rts16
71208f93c1SZi Xuan Wuentry:
72208f93c1SZi Xuan Wu  %ret = select i1 %x, double %m, double %n
73208f93c1SZi Xuan Wu  ret double %ret
74208f93c1SZi Xuan Wu}
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