xref: /llvm-project/llvm/test/CodeGen/AVR/pseudo/RORBrd.mir (revision 53a7c254e493499fd2007c9335e4c0d3ee96981c)
1*53a7c254SBen Shi# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
2*53a7c254SBen Shi
3*53a7c254SBen Shi# This test checks the expansion of the 8-bit RORB (rotate) pseudo instruction.
4*53a7c254SBen Shi
5*53a7c254SBen Shi--- |
6*53a7c254SBen Shi  target triple = "avr--"
7*53a7c254SBen Shi  define void @test_rorbrd() {
8*53a7c254SBen Shi  entry:
9*53a7c254SBen Shi    ret void
10*53a7c254SBen Shi  }
11*53a7c254SBen Shi...
12*53a7c254SBen Shi
13*53a7c254SBen Shi---
14*53a7c254SBen Shiname:            test_rorbrd
15*53a7c254SBen Shibody: |
16*53a7c254SBen Shi  bb.0.entry:
17*53a7c254SBen Shi    liveins: $r14
18*53a7c254SBen Shi
19*53a7c254SBen Shi    ; CHECK-LABEL: test_rorbrd
20*53a7c254SBen Shi    ; CHECK:         BST $r14, 0, implicit-def $sreg
21*53a7c254SBen Shi    ; CHECK-NEXT:    $r14 = RORRd $r14, implicit-def $sreg, implicit $sreg
22*53a7c254SBen Shi    ; CHECK-NEXT:    $r14 = BLD $r14, 7, implicit $sreg
23*53a7c254SBen Shi
24*53a7c254SBen Shi    $r14 = RORBRd $r14, implicit-def $sreg
25*53a7c254SBen Shi...
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