1f319c245SBen Shi; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2f319c245SBen Shi; RUN: llc < %s -mtriple=avr -mcpu=avrtiny | FileCheck %s 3f319c245SBen Shi 4f319c245SBen Shi; NOTE: Both %a(i8) and %b(i8) cost two registers. 5f319c245SBen Shidefine i8 @foo0(i8 %a, i8 %b) { 6f319c245SBen Shi; CHECK-LABEL: foo0: 7f319c245SBen Shi; CHECK: ; %bb.0: 8f319c245SBen Shi; CHECK-NEXT: sub r24, r22 9f319c245SBen Shi; CHECK-NEXT: ret 10f319c245SBen Shi %c = sub i8 %a, %b 11f319c245SBen Shi ret i8 %c 12f319c245SBen Shi} 13f319c245SBen Shi 14f319c245SBen Shi; NOTE: Both %a(i16) and %b(i16) cost two registers. 15f319c245SBen Shidefine i16 @foo1(i16 %a, i16 %b) { 16f319c245SBen Shi; CHECK-LABEL: foo1: 17f319c245SBen Shi; CHECK: ; %bb.0: 18f319c245SBen Shi; CHECK-NEXT: sub r24, r22 19f319c245SBen Shi; CHECK-NEXT: sbc r25, r23 20f319c245SBen Shi; CHECK-NEXT: ret 21f319c245SBen Shi %c = sub i16 %a, %b 22f319c245SBen Shi ret i16 %c 23f319c245SBen Shi} 24f319c245SBen Shi 25f319c245SBen Shi; NOTE: %a(i16), %b(i16) and %c(i16) each costs two registers. 26f319c245SBen Shidefine i16 @foo2(i16 %a, i16 %b, i16 %c) { 27f319c245SBen Shi; CHECK-LABEL: foo2: 28f319c245SBen Shi; CHECK: ; %bb.0: 29f319c245SBen Shi; CHECK-NEXT: sub r22, r24 30f319c245SBen Shi; CHECK-NEXT: sbc r23, r25 31f319c245SBen Shi; CHECK-NEXT: add r22, r20 32f319c245SBen Shi; CHECK-NEXT: adc r23, r21 33f319c245SBen Shi; CHECK-NEXT: mov r24, r22 34f319c245SBen Shi; CHECK-NEXT: mov r25, r23 35f319c245SBen Shi; CHECK-NEXT: ret 36f319c245SBen Shi %d = sub i16 %a, %b 37f319c245SBen Shi %e = sub i16 %c, %d 38f319c245SBen Shi ret i16 %e 39f319c245SBen Shi} 40f319c245SBen Shi 41f319c245SBen Shi; NOTE: %a(i16), %b(i16) and %c(i16) each costs two registers, 42f319c245SBen Shi; while %d(i16) is passed via the stack. 43f319c245SBen Shidefine i16 @foo3(i16 %a, i16 %b, i16 %c, i16 %d) { 44f319c245SBen Shi; CHECK-LABEL: foo3: 45f319c245SBen Shi; CHECK: ; %bb.0: 46f319c245SBen Shi; CHECK-NEXT: push r28 47f319c245SBen Shi; CHECK-NEXT: push r29 48f319c245SBen Shi; CHECK-NEXT: in r28, 61 49f319c245SBen Shi; CHECK-NEXT: in r29, 62 50*d1d3005cSAyke van Laethem; CHECK-NEXT: in r16, 63 51*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 251 52*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 255 53*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r30, Y+ 54*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r31, Y+ 55*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 2 56*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 57*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 5 58*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 59*d1d3005cSAyke van Laethem; CHECK-NEXT: out 63, r16 60f319c245SBen Shi; CHECK-NEXT: sub r20, r30 61f319c245SBen Shi; CHECK-NEXT: sbc r21, r31 62f319c245SBen Shi; CHECK-NEXT: sub r24, r22 63f319c245SBen Shi; CHECK-NEXT: sbc r25, r23 64f319c245SBen Shi; CHECK-NEXT: add r24, r20 65f319c245SBen Shi; CHECK-NEXT: adc r25, r21 66f319c245SBen Shi; CHECK-NEXT: pop r29 67f319c245SBen Shi; CHECK-NEXT: pop r28 68f319c245SBen Shi; CHECK-NEXT: ret 69f319c245SBen Shi %e = sub i16 %a, %b 70f319c245SBen Shi %g = sub i16 %c, %d 71f319c245SBen Shi %h = add i16 %e, %g 72f319c245SBen Shi ret i16 %h 73f319c245SBen Shi} 74f319c245SBen Shi 75f319c245SBen Shi; NOTE: %a(i32) costs four registers, while %b(i32) is passed via the stack. 76f319c245SBen Shidefine i32 @foo4(i32 %a, i32 %b) { 77f319c245SBen Shi; CHECK-LABEL: foo4: 78f319c245SBen Shi; CHECK: ; %bb.0: 79f319c245SBen Shi; CHECK-NEXT: push r28 80f319c245SBen Shi; CHECK-NEXT: push r29 81f319c245SBen Shi; CHECK-NEXT: in r28, 61 82f319c245SBen Shi; CHECK-NEXT: in r29, 62 83*d1d3005cSAyke van Laethem; CHECK-NEXT: in r16, 63 84*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 251 85*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 255 86*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r20, Y+ 87*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r21, Y+ 88*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 2 89*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 90*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 5 91*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 92*d1d3005cSAyke van Laethem; CHECK-NEXT: out 63, r16 93*d1d3005cSAyke van Laethem; CHECK-NEXT: in r16, 63 94*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 249 95*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 255 96*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r30, Y+ 97*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r31, Y+ 98*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 2 99*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 100*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r28, 7 101*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r29, 0 102*d1d3005cSAyke van Laethem; CHECK-NEXT: out 63, r16 103f319c245SBen Shi; CHECK-NEXT: sub r20, r22 104f319c245SBen Shi; CHECK-NEXT: sbc r21, r23 105f319c245SBen Shi; CHECK-NEXT: sbc r30, r24 106f319c245SBen Shi; CHECK-NEXT: sbc r31, r25 107f319c245SBen Shi; CHECK-NEXT: mov r22, r20 108f319c245SBen Shi; CHECK-NEXT: mov r23, r21 109f319c245SBen Shi; CHECK-NEXT: mov r24, r30 110f319c245SBen Shi; CHECK-NEXT: mov r25, r31 111f319c245SBen Shi; CHECK-NEXT: pop r29 112f319c245SBen Shi; CHECK-NEXT: pop r28 113f319c245SBen Shi; CHECK-NEXT: ret 114f319c245SBen Shi %c = sub i32 %b, %a 115f319c245SBen Shi ret i32 %c 116f319c245SBen Shi} 117f319c245SBen Shi 118f319c245SBen Shi; NOTE: %0 costs six registers, while %1 is passed via the stack. 119f319c245SBen Shidefine i8 @foo5([5 x i8] %0, i8 %1) { 120f319c245SBen Shi; CHECK-LABEL: foo5: 121f319c245SBen Shi; CHECK: ; %bb.0: 122f319c245SBen Shi; CHECK-NEXT: push r28 123f319c245SBen Shi; CHECK-NEXT: push r29 124f319c245SBen Shi; CHECK-NEXT: in r28, 61 125f319c245SBen Shi; CHECK-NEXT: in r29, 62 126*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 127*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 128*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 251 129*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 130*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r24, X 131f319c245SBen Shi; CHECK-NEXT: add r24, r20 132f319c245SBen Shi; CHECK-NEXT: pop r29 133f319c245SBen Shi; CHECK-NEXT: pop r28 134f319c245SBen Shi; CHECK-NEXT: ret 135f319c245SBen Shi %3 = extractvalue [5 x i8] %0, 0 136f319c245SBen Shi %4 = add i8 %3, %1 137f319c245SBen Shi ret i8 %4 138f319c245SBen Shi} 139f319c245SBen Shi 140f319c245SBen Shi; NOTE: %0 costs two registers and %1 costs four registers. 141f319c245SBen Shidefine i8 @foo6([2 x i8] %0, [4 x i8] %1) { 142f319c245SBen Shi; CHECK-LABEL: foo6: 143f319c245SBen Shi; CHECK: ; %bb.0: 144f319c245SBen Shi; CHECK-NEXT: add r24, r20 145f319c245SBen Shi; CHECK-NEXT: ret 146f319c245SBen Shi %3 = extractvalue [2 x i8] %0, 0 147f319c245SBen Shi %4 = extractvalue [4 x i8] %1, 0 148f319c245SBen Shi %5 = add i8 %3, %4 149f319c245SBen Shi ret i8 %5 150f319c245SBen Shi} 151f319c245SBen Shi 152f319c245SBen Shi; NOTE: %0 cost four registers, while %1 is passed via the stack, 153f319c245SBen Shi; though there are two vacant registers. 154f319c245SBen Shidefine i8 @foo7([3 x i8] %0, [3 x i8] %1) { 155f319c245SBen Shi; CHECK-LABEL: foo7: 156f319c245SBen Shi; CHECK: ; %bb.0: 157f319c245SBen Shi; CHECK-NEXT: push r28 158f319c245SBen Shi; CHECK-NEXT: push r29 159f319c245SBen Shi; CHECK-NEXT: in r28, 61 160f319c245SBen Shi; CHECK-NEXT: in r29, 62 161*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 162*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 163*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 251 164*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 165*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r24, X 166f319c245SBen Shi; CHECK-NEXT: add r24, r22 167f319c245SBen Shi; CHECK-NEXT: pop r29 168f319c245SBen Shi; CHECK-NEXT: pop r28 169f319c245SBen Shi; CHECK-NEXT: ret 170f319c245SBen Shi %3 = extractvalue [3 x i8] %0, 0 171f319c245SBen Shi %4 = extractvalue [3 x i8] %1, 0 172f319c245SBen Shi %5 = add i8 %3, %4 173f319c245SBen Shi ret i8 %5 174f319c245SBen Shi} 175f319c245SBen Shi 176f319c245SBen Shi; NOTE: %0 costs four registers, and %1 costs two registers, while %2 is 177f319c245SBen Shi; passed via the stack, though there is one vacant register. 178f319c245SBen Shidefine i8 @foo8([3 x i8] %0, i8 %1, i8 %2) { 179f319c245SBen Shi; CHECK-LABEL: foo8: 180f319c245SBen Shi; CHECK: ; %bb.0: 181f319c245SBen Shi; CHECK-NEXT: push r28 182f319c245SBen Shi; CHECK-NEXT: push r29 183f319c245SBen Shi; CHECK-NEXT: in r28, 61 184f319c245SBen Shi; CHECK-NEXT: in r29, 62 185f319c245SBen Shi; CHECK-NEXT: add r22, r20 186*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 187*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 188*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 251 189*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 190*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r24, X 191f319c245SBen Shi; CHECK-NEXT: sub r24, r22 192f319c245SBen Shi; CHECK-NEXT: pop r29 193f319c245SBen Shi; CHECK-NEXT: pop r28 194f319c245SBen Shi; CHECK-NEXT: ret 195f319c245SBen Shi %4 = extractvalue [3 x i8] %0, 0 196f319c245SBen Shi %5 = add i8 %4, %1 197f319c245SBen Shi %6 = sub i8 %2, %5 198f319c245SBen Shi ret i8 %6 199f319c245SBen Shi} 200f319c245SBen Shi 201f319c245SBen Shi; NOTE: %0 is passed via registers, though there are 6 vacant registers. 202f319c245SBen Shidefine i8 @foo9([7 x i8] %0) { 203f319c245SBen Shi; CHECK-LABEL: foo9: 204f319c245SBen Shi; CHECK: ; %bb.0: 205f319c245SBen Shi; CHECK-NEXT: push r28 206f319c245SBen Shi; CHECK-NEXT: push r29 207f319c245SBen Shi; CHECK-NEXT: in r28, 61 208f319c245SBen Shi; CHECK-NEXT: in r29, 62 209*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 210*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 211*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 250 212*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 213*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r25, X 214*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 215*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 216*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 251 217*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 218*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r24, X 219f319c245SBen Shi; CHECK-NEXT: add r24, r25 220f319c245SBen Shi; CHECK-NEXT: pop r29 221f319c245SBen Shi; CHECK-NEXT: pop r28 222f319c245SBen Shi; CHECK-NEXT: ret 223f319c245SBen Shi %2 = extractvalue [7 x i8] %0, 0 224f319c245SBen Shi %3 = extractvalue [7 x i8] %0, 1 225f319c245SBen Shi %4 = add i8 %2, %3 226f319c245SBen Shi ret i8 %4 227f319c245SBen Shi} 228f319c245SBen Shi 229f319c245SBen Shi; NOTE: %0 costs six registers, while %1 and %2 are passed via the stack. 230f319c245SBen Shidefine i8 @fooa([6 x i8] %0, i8 %1, i8 %2) { 231f319c245SBen Shi; CHECK-LABEL: fooa: 232f319c245SBen Shi; CHECK: ; %bb.0: 233f319c245SBen Shi; CHECK-NEXT: push r28 234f319c245SBen Shi; CHECK-NEXT: push r29 235f319c245SBen Shi; CHECK-NEXT: in r28, 61 236f319c245SBen Shi; CHECK-NEXT: in r29, 62 237*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 238*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 239*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 251 240*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 241*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r25, X 242*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r26, r28 243*d1d3005cSAyke van Laethem; CHECK-NEXT: mov r27, r29 244*d1d3005cSAyke van Laethem; CHECK-NEXT: subi r26, 250 245*d1d3005cSAyke van Laethem; CHECK-NEXT: sbci r27, 255 246*d1d3005cSAyke van Laethem; CHECK-NEXT: ld r24, X 247f319c245SBen Shi; CHECK-NEXT: sub r24, r25 248f319c245SBen Shi; CHECK-NEXT: sub r24, r20 249f319c245SBen Shi; CHECK-NEXT: pop r29 250f319c245SBen Shi; CHECK-NEXT: pop r28 251f319c245SBen Shi; CHECK-NEXT: ret 252f319c245SBen Shi %4 = extractvalue [6 x i8] %0, 0 253f319c245SBen Shi %5 = sub i8 %2, %1 254f319c245SBen Shi %6 = sub i8 %5, %4 255f319c245SBen Shi ret i8 %6 256f319c245SBen Shi} 257