1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=armv6-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV6 3; RUN: llc < %s -mtriple=armv7-unknown-linux-gnu | FileCheck %s --check-prefixes=ARMV7 4 5define { i64, i8 } @mulodi_test(i64 %l, i64 %r) unnamed_addr #0 { 6; ARMV6-LABEL: mulodi_test: 7; ARMV6: @ %bb.0: @ %start 8; ARMV6-NEXT: push {r4, r5, r11, lr} 9; ARMV6-NEXT: umull r12, lr, r1, r2 10; ARMV6-NEXT: umull r4, r5, r3, r0 11; ARMV6-NEXT: cmp lr, #0 12; ARMV6-NEXT: movne lr, #1 13; ARMV6-NEXT: cmp r3, #0 14; ARMV6-NEXT: movne r3, #1 15; ARMV6-NEXT: cmp r1, #0 16; ARMV6-NEXT: umull r0, r2, r0, r2 17; ARMV6-NEXT: movne r1, #1 18; ARMV6-NEXT: and r1, r1, r3 19; ARMV6-NEXT: cmp r5, #0 20; ARMV6-NEXT: orr r1, r1, lr 21; ARMV6-NEXT: movne r5, #1 22; ARMV6-NEXT: orr r3, r1, r5 23; ARMV6-NEXT: add r1, r12, r4 24; ARMV6-NEXT: adds r1, r2, r1 25; ARMV6-NEXT: mov r5, #0 26; ARMV6-NEXT: adc r2, r5, #0 27; ARMV6-NEXT: orr r2, r3, r2 28; ARMV6-NEXT: pop {r4, r5, r11, pc} 29; 30; ARMV7-LABEL: mulodi_test: 31; ARMV7: @ %bb.0: @ %start 32; ARMV7-NEXT: push {r4, r5, r11, lr} 33; ARMV7-NEXT: umull r12, lr, r3, r0 34; ARMV7-NEXT: cmp r3, #0 35; ARMV7-NEXT: movwne r3, #1 36; ARMV7-NEXT: cmp r1, #0 37; ARMV7-NEXT: umull r0, r4, r0, r2 38; ARMV7-NEXT: umull r2, r5, r1, r2 39; ARMV7-NEXT: movwne r1, #1 40; ARMV7-NEXT: and r1, r1, r3 41; ARMV7-NEXT: cmp r5, #0 42; ARMV7-NEXT: movwne r5, #1 43; ARMV7-NEXT: cmp lr, #0 44; ARMV7-NEXT: orr r1, r1, r5 45; ARMV7-NEXT: movwne lr, #1 46; ARMV7-NEXT: orr r3, r1, lr 47; ARMV7-NEXT: add r1, r2, r12 48; ARMV7-NEXT: mov r2, #0 49; ARMV7-NEXT: adds r1, r4, r1 50; ARMV7-NEXT: adc r2, r2, #0 51; ARMV7-NEXT: orr r2, r3, r2 52; ARMV7-NEXT: pop {r4, r5, r11, pc} 53start: 54 %0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %l, i64 %r) #2 55 %1 = extractvalue { i64, i1 } %0, 0 56 %2 = extractvalue { i64, i1 } %0, 1 57 %3 = zext i1 %2 to i8 58 %4 = insertvalue { i64, i8 } undef, i64 %1, 0 59 %5 = insertvalue { i64, i8 } %4, i8 %3, 1 60 ret { i64, i8 } %5 61} 62 63; Function Attrs: nounwind readnone speculatable 64declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #1 65 66attributes #0 = { nounwind readnone uwtable } 67attributes #1 = { nounwind readnone speculatable } 68attributes #2 = { nounwind } 69