1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s 3 4name: sink-store-load-dep 5tracksRegLiveness: true 6stack: 7 - { id: 0, type: default, size: 8, alignment: 8 } 8body: | 9 bb.0: 10 ; CHECK-LABEL: name: sink-store-load-dep 11 ; CHECK: bb.0: 12 ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32)) 13 ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg 14 ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg 15 ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16)) 16 ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg 17 ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg 18 ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg 19 ; CHECK: bb.2: 20 ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg 21 %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32)) 22 %1:gpr = MOVi 55296, 14, $noreg, $noreg 23 %2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg 24 %3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16)) 25 %4:gpr = MOVi 0, 14, $noreg, $noreg 26 early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg 27 %6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg 28 CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr 29 Bcc %bb.2, 3, $cpsr 30 B %bb.1 31 32 bb.1: 33 %8:gpr = MOVi 0, 14, $noreg, $noreg 34 $r0 = COPY %8:gpr 35 BX_RET 14, $noreg, implicit $r0 36 37 bb.2: 38 %9:gpr = MOVi %3:gpr, 14, $noreg, $noreg 39 $r0 = COPY %9:gpr 40 BX_RET 14, $noreg, implicit $r0 41... 42