xref: /llvm-project/llvm/test/CodeGen/ARM/single-issue-r52.mir (revision da71203e6fc6b8e08c9979204506d385e9cb07b8) 
1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass  machine-scheduler  -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
2# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass  machine-scheduler  -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
3# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass  machine-scheduler  -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
4# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass  machine-scheduler  -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
5# REQUIRES: asserts
6--- |
7  ; ModuleID = 'foo.ll'
8  source_filename = "foo.ll"
9  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
10  target triple = "arm---eabi"
11
12  %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
13  ; Function Attrs: nounwind
14  define <8 x i8> @foo(ptr %A) {
15    %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 8)
16    %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
17    %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1
18    %tmp4 = add <8 x i8> %tmp2, %tmp3
19    ret <8 x i8> %tmp4
20  }
21  declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr, i32)
22
23# CHECK: ********** MI Scheduling **********
24# CHECK: ScheduleDAGMILive::schedule starting
25# CHECK: SU(1):   %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg :: (load (s256) from %ir.A, align 8)
26# CHECK: Latency            : 8
27# CHECK: Single Issue       : true;
28# CHECK: SU(2):   %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg
29# CHECK: Latency            : 5
30# CHECK: Single Issue       : false;
31# CHECK: SU(3):   %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
32# CHECK: Latency            : 4
33# CHECK: Single Issue       : false;
34
35# TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
36# TOPDOWN: Bump cycle to end group
37# TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8
38
39# BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8
40# BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
41# BOTTOMUP: Bump cycle to begin group
42
43...
44---
45name:            foo
46alignment:       4
47exposesReturnsTwice: false
48legalized:       false
49regBankSelected: false
50selected:        false
51tracksRegLiveness: true
52registers:
53  - { id: 0, class: gpr }
54  - { id: 1, class: qqpr }
55  - { id: 2, class: dpr }
56  - { id: 3, class: dpr }
57  - { id: 4, class: dpr }
58  - { id: 5, class: gpr }
59  - { id: 6, class: gpr }
60liveins:
61  - { reg: '$r0', virtual-reg: '%0' }
62frameInfo:
63  isFrameAddressTaken: false
64  isReturnAddressTaken: false
65  hasStackMap:     false
66  hasPatchPoint:   false
67  stackSize:       0
68  offsetAdjustment: 0
69  maxAlignment:    0
70  adjustsStack:    false
71  hasCalls:        false
72  maxCallFrameSize: 0
73  hasOpaqueSPAdjustment: false
74  hasVAStart:      false
75  hasMustTailInVarArgFunc: false
76body:             |
77  bb.0 (%ir-block.0):
78    liveins: $r0
79
80    %0 = COPY $r0
81    %1 = VLD4d8Pseudo %0, 8, 14, $noreg :: (load (s256) from %ir.A, align 8)
82    %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, $noreg
83    %5, %6 = VMOVRRD %4, 14, $noreg
84    $r0 = COPY %5
85    $r1 = COPY %6
86    BX_RET 14, $noreg, implicit $r0, implicit killed $r1
87
88...
89