1; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM 2 3; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ 4; RUN: | FileCheck %s --check-prefix=ARMT2 5 6; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \ 7; RUN: | FileCheck %s --check-prefix=THUMB1 8 9; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ 10; RUN: | FileCheck %s --check-prefix=THUMB2 11 12; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \ 13; RUN: | FileCheck %s --check-prefix=V8MBASE 14 15define i32 @t1(i32 %c) nounwind readnone { 16entry: 17; ARM-LABEL: t1: 18; ARM: mov [[R1:r[0-9]+]], #101 19; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256 20; ARM: movgt {{r[0-1]}}, #123 21 22; ARMT2-LABEL: t1: 23; ARMT2: movw [[R:r[0-1]]], #357 24; ARMT2: movwgt [[R]], #123 25 26; THUMB1-LABEL: t1: 27; THUMB1: cmp r0, #1 28; THUMB1: bgt .LBB0_2 29 30; THUMB2-LABEL: t1: 31; THUMB2: movw [[R:r[0-1]]], #357 32; THUMB2: movgt [[R]], #123 33 34 %0 = icmp sgt i32 %c, 1 35 %1 = select i1 %0, i32 123, i32 357 36 ret i32 %1 37} 38 39define i32 @t2(i32 %c) nounwind readnone { 40entry: 41; ARM-LABEL: t2: 42; ARM: mov [[R:r[0-9]+]], #101 43; ARM: orr [[R]], [[R]], #256 44; ARM: movle [[R]], #123 45 46; ARMT2-LABEL: t2: 47; ARMT2: mov [[R:r[0-1]]], #123 48; ARMT2: movwgt [[R]], #357 49 50; THUMB1-LABEL: t2: 51; THUMB1: cmp r{{[0-9]+}}, #1 52; THUMB1: bgt 53 54; THUMB2-LABEL: t2: 55; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123 56; THUMB2: movwgt [[R]], #357 57 58 %0 = icmp sgt i32 %c, 1 59 %1 = select i1 %0, i32 357, i32 123 60 ret i32 %1 61} 62 63define i32 @t3(i32 %a) nounwind readnone { 64entry: 65; ARM-LABEL: t3: 66; ARM: rsbs r1, r0, #0 67; ARM: adc r0, r0, r1 68 69; ARMT2-LABEL: t3: 70; ARMT2: clz r0, r0 71; ARMT2: lsr r0, r0, #5 72 73; THUMB1-LABEL: t3: 74; THUMB1: rsbs r1, r0, #0 75; THUMB1: adcs r0, r1 76 77; THUMB2-LABEL: t3: 78; THUMB2: clz r0, r0 79; THUMB2: lsrs r0, r0, #5 80 %0 = icmp eq i32 %a, 160 81 %1 = zext i1 %0 to i32 82 ret i32 %1 83} 84 85define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind { 86entry: 87; ARM-LABEL: t4: 88; ARM: mvn [[R0:r[0-9]+]], #170 89; ARM: sub [[R0:r[0-9]+]], [[R0:r[0-9]+]], #11141120 90; ARM: mov{{lt|ge}} 91 92; ARMT2-LABEL: t4: 93; ARMT2: movwlt [[R0:r[0-9]+]], #65365 94; ARMT2: movtlt [[R0]], #65365 95 96; THUMB1-LABEL: t4: 97; THUMB1: cmp r{{[0-9]+}}, r{{[0-9]+}} 98; THUMB1: b{{lt|ge}} 99 100; THUMB2-LABEL: t4: 101; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290 102 %0 = icmp slt i32 %a, %b 103 %1 = select i1 %0, i32 4283826005, i32 %x 104 ret i32 %1 105} 106 107; rdar://9758317 108define i32 @t5(i32 %a) nounwind { 109entry: 110; ARM-LABEL: t5: 111; ARM-NOT: mov 112; ARM: sub r0, r0, #1 113; ARM-NOT: mov 114; ARM: rsbs r1, r0, #0 115; ARM: adc r0, r0, r1 116 117; THUMB1-LABEL: t5: 118; THUMB1-NOT: bne 119; THUMB1: rsbs r0, r1, #0 120; THUMB1: adcs r0, r1 121 122; THUMB2-LABEL: t5: 123; THUMB2-NOT: mov 124; THUMB2: subs r0, #1 125; THUMB2: clz r0, r0 126; THUMB2: lsrs r0, r0, #5 127 128 %cmp = icmp eq i32 %a, 1 129 %conv = zext i1 %cmp to i32 130 ret i32 %conv 131} 132 133define i32 @t6(i32 %a) nounwind { 134entry: 135; ARM-LABEL: t6: 136; ARM-NOT: mov 137; ARM: cmp r0, #0 138; ARM: movne r0, #1 139 140; THUMB1-LABEL: t6: 141; THUMB1: subs r1, r0, #1 142; THUMB1: sbcs r0, r1 143 144; THUMB2-LABEL: t6: 145; THUMB2-NOT: mov 146; THUMB2: cmp r0, #0 147; THUMB2: it ne 148; THUMB2: movne r0, #1 149 %tobool = icmp ne i32 %a, 0 150 %lnot.ext = zext i1 %tobool to i32 151 ret i32 %lnot.ext 152} 153 154define i32 @t7(i32 %a, i32 %b) nounwind readnone { 155entry: 156; ARM-LABEL: t7: 157; ARM: subs r0, r0, r1 158; ARM: movne r0, #1 159; ARM: lsl r0, r0, #2 160 161; ARMT2-LABEL: t7: 162; ARMT2: subs r0, r0, r1 163; ARMT2: movwne r0, #1 164; ARMT2: lsl r0, r0, #2 165 166; THUMB1-LABEL: t7: 167; THUMB1: subs r0, r0, r1 168; THUMB1: subs r1, r0, #1 169; THUMB1: sbcs r0, r1 170; THUMB1: lsls r0, r0, #2 171 172; THUMB2-LABEL: t7: 173; THUMB2: subs r0, r0, r1 174; THUMB2: it ne 175; THUMB2: movne r0, #1 176; THUMB2: lsls r0, r0, #2 177 %0 = icmp ne i32 %a, %b 178 %1 = select i1 %0, i32 4, i32 0 179 ret i32 %1 180} 181 182define void @t8(i32 %a) { 183entry: 184 185; ARM scheduler emits icmp/zext before both calls, so isn't relevant 186 187; ARMT2-LABEL: t8: 188; ARMT2: bl t7 189; ARMT2: mov r1, r0 190; ARMT2: sub r0, r4, #5 191; ARMT2: clz r0, r0 192; ARMT2: lsr r0, r0, #5 193 194; THUMB1-LABEL: t8: 195; THUMB1: bl t7 196; THUMB1: mov r1, r0 197; THUMB1: subs r2, r4, #5 198; THUMB1: rsbs r0, r2, #0 199; THUMB1: adcs r0, r2 200 201; THUMB2-LABEL: t8: 202; THUMB2: bl t7 203; THUMB2: mov r1, r0 204; THUMB2: subs r0, r4, #5 205; THUMB2: clz r0, r0 206; THUMB2: lsrs r0, r0, #5 207 208 %cmp = icmp eq i32 %a, 5 209 %conv = zext i1 %cmp to i32 210 %call = tail call i32 @t7(i32 9, i32 %a) 211 tail call i32 @t7(i32 %conv, i32 %call) 212 ret void 213} 214 215define void @t9(i8* %a, i8 %b) { 216entry: 217 218; ARM scheduler emits icmp/zext before both calls, so isn't relevant 219 220; ARMT2-LABEL: t9: 221; ARMT2: bl f 222; ARMT2: uxtb r0, r4 223; ARMT2: cmp r0, r0 224; ARMT2: add r1, r4, #1 225; ARMT2: mov r2, r0 226; ARMT2: add r2, r2, #1 227; ARMT2: add r1, r1, #1 228; ARMT2: uxtb r3, r2 229; ARMT2: cmp r3, r0 230 231; THUMB1-LABEL: t9: 232; THUMB1: bl f 233; THUMB1: uxtb r0, r4 234; THUMB1: cmp r0, r0 235; THUMB1: adds r1, r4, #1 236; THUMB1: mov r2, r0 237; THUMB1: adds r1, r1, #1 238; THUMB1: adds r2, r2, #1 239; THUMB1: uxtb r3, r2 240; THUMB1: cmp r3, r0 241 242; THUMB2-LABEL: t9: 243; THUMB2: bl f 244; THUMB2: uxtb r0, r4 245; THUMB2: cmp r0, r0 246; THUMB2: adds r1, r4, #1 247; THUMB2: mov r2, r0 248; THUMB2: adds r2, #1 249; THUMB2: adds r1, #1 250; THUMB2: uxtb r3, r2 251; THUMB2: cmp r3, r0 252 253 %0 = load i8, i8* %a 254 %conv = sext i8 %0 to i32 255 %conv119 = zext i8 %0 to i32 256 %conv522 = and i32 %conv, 255 257 %cmp723 = icmp eq i32 %conv522, %conv119 258 tail call void @f(i1 zeroext %cmp723) 259 br i1 %cmp723, label %while.body, label %while.end 260 261while.body: ; preds = %entry, %while.body 262 %ref.025 = phi i8 [ %inc9, %while.body ], [ %0, %entry ] 263 %in.024 = phi i32 [ %inc, %while.body ], [ %conv, %entry ] 264 %inc = add i32 %in.024, 1 265 %inc9 = add i8 %ref.025, 1 266 %conv1 = zext i8 %inc9 to i32 267 %cmp = icmp slt i32 %conv1, %conv119 268 %conv5 = and i32 %inc, 255 269 br i1 %cmp, label %while.body, label %while.end 270 271while.end: 272 ret void 273} 274 275declare void @f(i1 zeroext) 276 277 278define i1 @t10() { 279entry: 280 %q = alloca i32 281 %p = alloca i32 282 store i32 -3, i32* %q 283 store i32 -8, i32* %p 284 %0 = load i32, i32* %q 285 %1 = load i32, i32* %p 286 %div = sdiv i32 %0, %1 287 %mul = mul nsw i32 %div, %1 288 %rem = srem i32 %0, %1 289 %add = add nsw i32 %mul, %rem 290 %cmp = icmp eq i32 %add, %0 291 ret i1 %cmp 292 293; ARM-LABEL: t10: 294; ARM: rsbs r1, r0, #0 295; ARM: adc r0, r0, r1 296 297; ARMT2-LABEL: t10: 298; ARMT2: clz r0, r0 299; ARMT2: lsr r0, r0, #5 300 301; THUMB1-LABEL: t10: 302; THUMB1: rsbs r0, r1, #0 303; THUMB1: adcs r0, r1 304 305; THUMB2-LABEL: t10: 306; THUMB2: clz r0, r0 307; THUMB2: lsrs r0, r0, #5 308 309; V8MBASE-LABEL: t10: 310; V8MBASE-NOT: movs r0, #0 311; V8MBASE: movs r0, #7 312} 313 314define i1 @t11() { 315entry: 316 %bit = alloca i32 317 %load = load i32, i32* %bit 318 %clear = and i32 %load, -4096 319 %set = or i32 %clear, 33 320 store i32 %set, i32* %bit 321 %load1 = load i32, i32* %bit 322 %clear2 = and i32 %load1, -33550337 323 %set3 = or i32 %clear2, 40960 324 %clear5 = and i32 %set3, 4095 325 %rem = srem i32 %clear5, 10 326 %clear9 = and i32 %set3, -4096 327 %set10 = or i32 %clear9, %rem 328 store i32 %set10, i32* %bit 329 %clear12 = and i32 %set10, 4095 330 %cmp = icmp eq i32 %clear12, 3 331 ret i1 %cmp 332 333; ARM-LABEL: t11: 334; ARM: rsbs r1, r0, #0 335; ARM: adc r0, r0, r1 336 337; ARMT2-LABEL: t11: 338; ARMT2: clz r0, r0 339; ARMT2: lsr r0, r0, #5 340 341; THUMB1-LABEL: t11: 342; THUMB1-NOT: movs r0, #0 343; THUMB1: movs r0, #5 344 345; THUMB2-LABEL: t11: 346; THUMB2: clz r0, r0 347; THUMB2: lsrs r0, r0, #5 348 349; V8MBASE-LABEL: t11: 350; V8MBASE-NOT: movs r0, #0 351; V8MBASE: movw r0, #40960 352} 353 354define i32 @t12(i32 %a) nounwind { 355entry: 356; ARM-LABEL: t12: 357; ARM-NOT: mov 358; ARM: cmp r0, #0 359; ARM: movne r0, #1 360 361; THUMB1-LABEL: t12: 362; THUMB1: subs r1, r0, #1 363; THUMB1: sbcs r0, r1 364; THUMB1: lsls r0, r0, #1 365 366; THUMB2-LABEL: t12: 367; THUMB2-NOT: mov 368; THUMB2: cmp r0, #0 369; THUMB2: it ne 370; THUMB2: movne r0, #1 371 %tobool = icmp ne i32 %a, 0 372 %lnot.ext = select i1 %tobool, i32 2, i32 0 373 ret i32 %lnot.ext 374} 375 376define i32 @t13(i32 %a) nounwind { 377entry: 378; ARM-LABEL: t13: 379; ARM-NOT: mov 380; ARM: cmp r0, #0 381; ARM: movne r0, #3 382 383; THUMB1-LABEL: t13: 384; THUMB1: cmp r0, #0 385; THUMB1: beq 386; THUMB1: movs r0, #3 387 388; THUMB2-LABEL: t13: 389; THUMB2-NOT: mov 390; THUMB2: cmp r0, #0 391; THUMB2: it ne 392; THUMB2: movne r0, #3 393 %tobool = icmp ne i32 %a, 0 394 %lnot.ext = select i1 %tobool, i32 3, i32 0 395 ret i32 %lnot.ext 396} 397