xref: /llvm-project/llvm/test/CodeGen/ARM/reg_sequence.ll (revision 14364200821f7b2d97edf6e78160c514800d3ec6) 
1; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s --check-prefixes=CHECK,DEFAULT
2; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 -regalloc=basic | FileCheck %s --check-prefixes=CHECK,BASIC
3; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
4
5%struct.int16x8_t = type { <8 x i16> }
6%struct.int32x4_t = type { <4 x i32> }
7%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
8%struct.__neon_int8x8x3_t = type { <8 x i8>,  <8 x i8>,  <8 x i8> }
9%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
10%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
11
12define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
13; DEFAULT-LABEL: t1:
14; DEFAULT:       @ %bb.0: @ %entry
15; DEFAULT-NEXT:    vld1.16 {d16, d17}, [r0]
16; DEFAULT-NEXT:    vmovl.s16 q9, d17
17; DEFAULT-NEXT:    vld1.64 {d20, d21}, [r3:128]
18; DEFAULT-NEXT:    vmovl.s16 q8, d16
19; DEFAULT-NEXT:    vld1.64 {d22, d23}, [r2:128]
20; DEFAULT-NEXT:    vmul.i32 q9, q10, q9
21; DEFAULT-NEXT:    vmul.i32 q8, q11, q8
22; DEFAULT-NEXT:    vshrn.i32 d19, q9, #12
23; DEFAULT-NEXT:    vshrn.i32 d18, q8, #12
24; DEFAULT-NEXT:    vst1.16 {d18, d19}, [r1]
25; DEFAULT-NEXT:    bx lr
26;
27; BASIC-LABEL: t1:
28; BASIC:       @ %bb.0: @ %entry
29; BASIC-NEXT:    vld1.16 {d16, d17}, [r0]
30; BASIC-NEXT:    vmovl.s16 q12, d17
31; BASIC-NEXT:    vld1.64 {d22, d23}, [r3:128]
32; BASIC-NEXT:    vmovl.s16 q10, d16
33; BASIC-NEXT:    vld1.64 {d18, d19}, [r2:128]
34; BASIC-NEXT:    vmul.i32 q8, q11, q12
35; BASIC-NEXT:    vmul.i32 q9, q9, q10
36; BASIC-NEXT:    vshrn.i32 d17, q8, #12
37; BASIC-NEXT:    vshrn.i32 d16, q9, #12
38; BASIC-NEXT:    vst1.16 {d16, d17}, [r1]
39; BASIC-NEXT:    bx lr
40entry:
41  %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
42  %1 = load <4 x i32>, <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
43  %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
44  %3 = load <4 x i32>, <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
45  %4 = bitcast i16* %i_ptr to i8*                 ; <i8*> [#uses=1]
46  %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
47  %6 = bitcast <8 x i16> %5 to <2 x double>       ; <<2 x double>> [#uses=2]
48  %7 = extractelement <2 x double> %6, i32 0      ; <double> [#uses=1]
49  %8 = bitcast double %7 to <4 x i16>             ; <<4 x i16>> [#uses=1]
50  %9 = sext <4 x i16> %8 to <4 x i32>             ; <<4 x i32>> [#uses=1]
51  %10 = extractelement <2 x double> %6, i32 1     ; <double> [#uses=1]
52  %11 = bitcast double %10 to <4 x i16>           ; <<4 x i16>> [#uses=1]
53  %12 = sext <4 x i16> %11 to <4 x i32>           ; <<4 x i32>> [#uses=1]
54  %13 = mul <4 x i32> %1, %9                      ; <<4 x i32>> [#uses=1]
55  %14 = mul <4 x i32> %3, %12                     ; <<4 x i32>> [#uses=1]
56  %15 = lshr <4 x i32> %13, <i32 12, i32 12, i32 12, i32 12>
57  %trunc_15 = trunc <4 x i32> %15 to <4 x i16>
58  %16 = lshr <4 x i32> %14, <i32 12, i32 12, i32 12, i32 12>
59  %trunc_16 = trunc <4 x i32> %16 to <4 x i16>
60  %17 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]
61  %18 = bitcast i16* %o_ptr to i8*                ; <i8*> [#uses=1]
62  tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %18, <8 x i16> %17, i32 1)
63  ret void
64}
65
66define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
67; DEFAULT-LABEL: t2:
68; DEFAULT:       @ %bb.0: @ %entry
69; DEFAULT-NEXT:    vld1.16 {d16, d17}, [r0]!
70; DEFAULT-NEXT:    vld1.64 {d18, d19}, [r2:128]
71; DEFAULT-NEXT:    vmul.i16 q8, q9, q8
72; DEFAULT-NEXT:    vld1.64 {d18, d19}, [r3:128]
73; DEFAULT-NEXT:    vld1.16 {d20, d21}, [r0]
74; DEFAULT-NEXT:    vmul.i16 q9, q9, q10
75; DEFAULT-NEXT:    vst1.16 {d16, d17}, [r1]!
76; DEFAULT-NEXT:    vst1.16 {d18, d19}, [r1]
77; DEFAULT-NEXT:    bx lr
78;
79; BASIC-LABEL: t2:
80; BASIC:       @ %bb.0: @ %entry
81; BASIC-NEXT:    vld1.16 {d18, d19}, [r0]!
82; BASIC-NEXT:    vld1.64 {d16, d17}, [r2:128]
83; BASIC-NEXT:    vmul.i16 q10, q8, q9
84; BASIC-NEXT:    vld1.64 {d18, d19}, [r3:128]
85; BASIC-NEXT:    vld1.16 {d16, d17}, [r0]
86; BASIC-NEXT:    vmul.i16 q8, q9, q8
87; BASIC-NEXT:    vst1.16 {d20, d21}, [r1]!
88; BASIC-NEXT:    vst1.16 {d16, d17}, [r1]
89; BASIC-NEXT:    bx lr
90entry:
91  %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
92  %1 = load <8 x i16>, <8 x i16>* %0, align 16               ; <<8 x i16>> [#uses=1]
93  %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
94  %3 = load <8 x i16>, <8 x i16>* %2, align 16               ; <<8 x i16>> [#uses=1]
95  %4 = bitcast i16* %i_ptr to i8*                 ; <i8*> [#uses=1]
96  %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
97  %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8  ; <i16*> [#uses=1]
98  %7 = bitcast i16* %6 to i8*                     ; <i8*> [#uses=1]
99  %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
100  %9 = mul <8 x i16> %1, %5                       ; <<8 x i16>> [#uses=1]
101  %10 = mul <8 x i16> %3, %8                      ; <<8 x i16>> [#uses=1]
102  %11 = bitcast i16* %o_ptr to i8*                ; <i8*> [#uses=1]
103  tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %11, <8 x i16> %9, i32 1)
104  %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
105  %13 = bitcast i16* %12 to i8*                   ; <i8*> [#uses=1]
106  tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %13, <8 x i16> %10, i32 1)
107  ret void
108}
109
110define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
111; DEFAULT-LABEL: t3:
112; DEFAULT:       @ %bb.0:
113; DEFAULT-NEXT:    vld3.8 {d16, d17, d18}, [r0]
114; DEFAULT-NEXT:    vmul.i8 d22, d17, d16
115; DEFAULT-NEXT:    vmov r0, r2, d17
116; DEFAULT-NEXT:    vadd.i8 d21, d16, d18
117; DEFAULT-NEXT:    vsub.i8 d20, d18, d17
118; DEFAULT-NEXT:    vst3.8 {d20, d21, d22}, [r1]
119; DEFAULT-NEXT:    mov r1, r2
120; DEFAULT-NEXT:    bx lr
121;
122; BASIC-LABEL: t3:
123; BASIC:       @ %bb.0:
124; BASIC-NEXT:    vld3.8 {d20, d21, d22}, [r0]
125; BASIC-NEXT:    mov r2, r1
126; BASIC-NEXT:    vmul.i8 d18, d21, d20
127; BASIC-NEXT:    vmov r0, r1, d21
128; BASIC-NEXT:    vadd.i8 d17, d20, d22
129; BASIC-NEXT:    vsub.i8 d16, d22, d21
130; BASIC-NEXT:    vst3.8 {d16, d17, d18}, [r2]
131; BASIC-NEXT:    bx lr
132  %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
133  %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
134  %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1]
135  %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]
136  %tmp5 = sub <8 x i8> %tmp3, %tmp4
137  %tmp6 = add <8 x i8> %tmp2, %tmp3               ; <<8 x i8>> [#uses=1]
138  %tmp7 = mul <8 x i8> %tmp4, %tmp2
139  tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
140  ret <8 x i8> %tmp4
141}
142
143define void @t4(i32* %in, i32* %out) nounwind {
144; DEFAULT-LABEL: t4:
145; DEFAULT:       @ %bb.0: @ %entry
146; DEFAULT-NEXT:    vld2.32 {d20, d21, d22, d23}, [r0]!
147; DEFAULT-NEXT:    vld2.32 {d16, d17, d18, d19}, [r0]
148; DEFAULT-NEXT:    mov r0, #0
149; DEFAULT-NEXT:    cmp r0, #0
150; DEFAULT-NEXT:    bne LBB3_2
151; DEFAULT-NEXT:  @ %bb.1: @ %return1
152; DEFAULT-NEXT:    vadd.i32 q12, q10, q8
153; DEFAULT-NEXT:    vadd.i32 q13, q11, q9
154; DEFAULT-NEXT:    vst2.32 {d24, d25, d26, d27}, [r1]
155; DEFAULT-NEXT:    bx lr
156; DEFAULT-NEXT:  LBB3_2: @ %return2
157; DEFAULT-NEXT:    vadd.i32 q8, q10, q9
158; DEFAULT-NEXT:    vst2.32 {d16, d17, d18, d19}, [r1]
159; DEFAULT-NEXT:    trap
160;
161; BASIC-LABEL: t4:
162; BASIC:       @ %bb.0: @ %entry
163; BASIC-NEXT:    vld2.32 {d20, d21, d22, d23}, [r0]!
164; BASIC-NEXT:    vld2.32 {d24, d25, d26, d27}, [r0]
165; BASIC-NEXT:    mov r0, #0
166; BASIC-NEXT:    cmp r0, #0
167; BASIC-NEXT:    bne LBB3_2
168; BASIC-NEXT:  @ %bb.1: @ %return1
169; BASIC-NEXT:    vadd.i32 q8, q10, q12
170; BASIC-NEXT:    vadd.i32 q9, q11, q13
171; BASIC-NEXT:    vst2.32 {d16, d17, d18, d19}, [r1]
172; BASIC-NEXT:    bx lr
173; BASIC-NEXT:  LBB3_2: @ %return2
174; BASIC-NEXT:    vadd.i32 q12, q10, q13
175; BASIC-NEXT:    vst2.32 {d24, d25, d26, d27}, [r1]
176; BASIC-NEXT:    trap
177entry:
178  %tmp1 = bitcast i32* %in to i8*                 ; <i8*> [#uses=1]
179  %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
180  %tmp3 = getelementptr inbounds i32, i32* %in, i32 8  ; <i32*> [#uses=1]
181  %tmp4 = bitcast i32* %tmp3 to i8*               ; <i8*> [#uses=1]
182  %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
183  %tmp8 = bitcast i32* %out to i8*                ; <i8*> [#uses=1]
184  br i1 undef, label %return1, label %return2
185
186return1:
187  %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
188  %tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1]
189  %tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1]
190  %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
191  %tmp6 = add <4 x i32> %tmp52, %tmp              ; <<4 x i32>> [#uses=1]
192  %tmp7 = add <4 x i32> %tmp57, %tmp39            ; <<4 x i32>> [#uses=1]
193  tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)
194  ret void
195
196return2:
197  %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
198  %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
199  %tmp102 = add <4 x i32> %tmp100, %tmp101              ; <<4 x i32>> [#uses=1]
200  tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)
201  call void @llvm.trap()
202  unreachable
203}
204
205define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
206; CHECK-LABEL: t5:
207; CHECK:       @ %bb.0:
208; CHECK-NEXT:    vld1.32 {d16, d17}, [r1]
209; CHECK-NEXT:    vorr q9, q8, q8
210; CHECK-NEXT:    vld2.16 {d16[1], d18[1]}, [r0]
211; CHECK-NEXT:    vadd.i16 q8, q8, q9
212; CHECK-NEXT:    vmov r0, r1, d16
213; CHECK-NEXT:    vmov r2, r3, d17
214; CHECK-NEXT:    bx lr
215  %tmp0 = bitcast i16* %A to i8*                  ; <i8*> [#uses=1]
216  %tmp1 = load <8 x i16>, <8 x i16>* %B                      ; <<8 x i16>> [#uses=2]
217  %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
218  %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]
219  %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]
220  %tmp5 = add <8 x i16> %tmp3, %tmp4              ; <<8 x i16>> [#uses=1]
221  ret <8 x i16> %tmp5
222}
223
224define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
225; CHECK-LABEL: t6:
226; CHECK:       @ %bb.0:
227; CHECK-NEXT:    vldr d16, [r1]
228; CHECK-NEXT:    vorr d17, d16, d16
229; CHECK-NEXT:    vld2.8 {d16[1], d17[1]}, [r0]
230; CHECK-NEXT:    vadd.i8 d16, d16, d17
231; CHECK-NEXT:    vmov r0, r1, d16
232; CHECK-NEXT:    bx lr
233  %tmp1 = load <8 x i8>, <8 x i8>* %B                       ; <<8 x i8>> [#uses=2]
234  %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
235  %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]
236  %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1]
237  %tmp5 = add <8 x i8> %tmp3, %tmp4               ; <<8 x i8>> [#uses=1]
238  ret <8 x i8> %tmp5
239}
240
241define void @t7(i32* %iptr, i32* %optr) nounwind {
242; DEFAULT-LABEL: t7:
243; DEFAULT:       @ %bb.0: @ %entry
244; DEFAULT-NEXT:    vld2.32 {d16, d17, d18, d19}, [r0]
245; DEFAULT-NEXT:    vst2.32 {d16, d17, d18, d19}, [r1]
246; DEFAULT-NEXT:    vld1.32 {d16, d17}, [r0]
247; DEFAULT-NEXT:    vorr q9, q8, q8
248; DEFAULT-NEXT:    vuzp.32 q8, q9
249; DEFAULT-NEXT:    vst1.32 {d16, d17}, [r1]
250; DEFAULT-NEXT:    bx lr
251;
252; BASIC-LABEL: t7:
253; BASIC:       @ %bb.0: @ %entry
254; BASIC-NEXT:    vld2.32 {d16, d17, d18, d19}, [r0]
255; BASIC-NEXT:    vst2.32 {d16, d17, d18, d19}, [r1]
256; BASIC-NEXT:    vld1.32 {d18, d19}, [r0]
257; BASIC-NEXT:    vorr q8, q9, q9
258; BASIC-NEXT:    vuzp.32 q9, q8
259; BASIC-NEXT:    vst1.32 {d18, d19}, [r1]
260; BASIC-NEXT:    bx lr
261entry:
262  %0 = bitcast i32* %iptr to i8*                  ; <i8*> [#uses=2]
263  %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
264  %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1]
265  %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1]
266  %2 = bitcast i32* %optr to i8*                  ; <i8*> [#uses=2]
267  tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
268  %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %0, i32 1) ; <<4 x i32>> [#uses=1]
269  %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]
270  tail call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %2, <4 x i32> %4, i32 1)
271  ret void
272}
273
274; PR7156
275define arm_aapcs_vfpcc i32 @t8() nounwind {
276; CHECK-LABEL: t8:
277; CHECK:       @ %bb.0: @ %bb.nph55.bb.nph55.split_crit_edge
278; CHECK-NEXT:    vrsqrte.f32 q8, q8
279; CHECK-NEXT:    vmul.f32 q8, q8, q8
280; CHECK-NEXT:    vmul.f32 q8, q8, q8
281; CHECK-NEXT:    vst1.32 {d16[1]}, [r0:32]
282; CHECK-NEXT:    mov r0, #0
283; CHECK-NEXT:    cmp r0, #0
284; CHECK-NEXT:    movne r0, #0
285; CHECK-NEXT:    bxne lr
286; CHECK-NEXT:  LBB7_1: @ %bb7
287bb.nph55.bb.nph55.split_crit_edge:
288  br label %bb3
289
290bb3:                                              ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
291  br i1 undef, label %bb5, label %bb3
292
293bb5:                                              ; preds = %bb3
294  br label %bb.i25
295
296bb.i25:                                           ; preds = %bb.i25, %bb5
297  %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
298  %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1]
299  %2 = fmul <4 x float> %1, %1                 ; <<4 x float>> [#uses=1]
300  %3 = fmul <4 x float> %2, %2                 ; <<4 x float>> [#uses=1]
301  %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]
302  %4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1]
303  %5 = bitcast double %4 to <2 x float>           ; <<2 x float>> [#uses=1]
304  %6 = extractelement <2 x float> %5, i32 1       ; <float> [#uses=1]
305  store float %6, float* undef, align 4
306  br i1 undef, label %bb6, label %bb.i25
307
308bb6:                                              ; preds = %bb.i25
309  br i1 undef, label %bb7, label %bb14
310
311bb7:                                              ; preds = %bb6
312  br label %bb.i49
313
314bb.i49:                                           ; preds = %bb.i49, %bb7
315  br i1 undef, label %bb.i19, label %bb.i49
316
317bb.i19:                                           ; preds = %bb.i19, %bb.i49
318  br i1 undef, label %exit, label %bb.i19
319
320exit:          ; preds = %bb.i19
321  unreachable
322
323bb14:                                             ; preds = %bb6
324  ret i32 0
325}
326
327%0 = type { %1, %1, %1, %1 }
328%1 = type { %2 }
329%2 = type { <4 x float> }
330%3 = type { %0, %1 }
331
332; PR7157
333define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
334; CHECK-LABEL: t9:
335; CHECK:       @ %bb.0:
336; CHECK-NEXT:    vmov.i32 d16, #0x0
337; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
338; CHECK-NEXT:    vorr d17, d16, d16
339; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
340; CHECK-NEXT:  LBB8_1: @ =>This Inner Loop Header: Depth=1
341; CHECK-NEXT:    b LBB8_1
342  %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
343  %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
344  store <4 x float> %4, <4 x float>* undef, align 16
345  %5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
346  store <4 x float> %5, <4 x float>* undef, align 16
347  br label %8
348
349; <label>:6                                       ; preds = %8
350  br label %7
351
352; <label>:7                                       ; preds = %6
353  br label %8
354
355; <label>:8                                       ; preds = %7, %2
356  br label %6
357
358; <label>:9                                       ; preds = %8
359  ret float undef
360
361; <label>:10                                      ; preds = %6
362  ret float 9.990000e+02
363}
364
365; PR7162
366define arm_aapcs_vfpcc i32 @t10(float %x) nounwind {
367; DEFAULT-LABEL: t10:
368; DEFAULT:       @ %bb.0: @ %entry
369; DEFAULT-NEXT:    vmov.i32 d2, #0x0
370; DEFAULT-NEXT:    @ kill: def $s0 killed $s0 def $d0
371; DEFAULT-NEXT:    vdup.32 q0, d0[0]
372; DEFAULT-NEXT:    vmov.i32 q9, #0x3f000000
373; DEFAULT-NEXT:    vmov.f32 s0, s4
374; DEFAULT-NEXT:    vmul.f32 q8, q0, q0
375; DEFAULT-NEXT:    vadd.f32 q8, q8, q8
376; DEFAULT-NEXT:    vadd.f32 q0, q8, q8
377; DEFAULT-NEXT:    vmul.f32 q8, q9, d1[0]
378; DEFAULT-NEXT:    vmul.f32 q8, q8, q8
379; DEFAULT-NEXT:    vadd.f32 q8, q8, q8
380; DEFAULT-NEXT:    vmul.f32 q8, q8, q8
381; DEFAULT-NEXT:    vst1.32 {d17[1]}, [r0:32]
382; DEFAULT-NEXT:    mov r0, #0
383; DEFAULT-NEXT:    cmp r0, #0
384; DEFAULT-NEXT:    movne r0, #0
385; DEFAULT-NEXT:    bxne lr
386; DEFAULT-NEXT:  LBB9_1: @ %exit
387; DEFAULT-NEXT:    trap
388;
389; BASIC-LABEL: t10:
390; BASIC:       @ %bb.0: @ %entry
391; BASIC-NEXT:    @ kill: def $s0 killed $s0 def $d0
392; BASIC-NEXT:    vdup.32 q1, d0[0]
393; BASIC-NEXT:    vmov.i32 q9, #0x3f000000
394; BASIC-NEXT:    vmov.i32 d0, #0x0
395; BASIC-NEXT:    vmov.f32 s4, s0
396; BASIC-NEXT:    vmul.f32 q8, q1, q1
397; BASIC-NEXT:    vadd.f32 q8, q8, q8
398; BASIC-NEXT:    vadd.f32 q0, q8, q8
399; BASIC-NEXT:    vmul.f32 q8, q9, d1[0]
400; BASIC-NEXT:    vmul.f32 q8, q8, q8
401; BASIC-NEXT:    vadd.f32 q8, q8, q8
402; BASIC-NEXT:    vmul.f32 q8, q8, q8
403; BASIC-NEXT:    vst1.32 {d17[1]}, [r0:32]
404; BASIC-NEXT:    mov r0, #0
405; BASIC-NEXT:    cmp r0, #0
406; BASIC-NEXT:    movne r0, #0
407; BASIC-NEXT:    bxne lr
408; BASIC-NEXT:  LBB9_1: @ %exit
409; BASIC-NEXT:    trap
410entry:
411  %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
412  %1 = insertelement <4 x float> %0, float %x, i32 1 ; <<4 x float>> [#uses=1]
413  %2 = insertelement <4 x float> %1, float %x, i32 2 ; <<4 x float>> [#uses=1]
414  %3 = insertelement <4 x float> %2, float %x, i32 3 ; <<4 x float>> [#uses=1]
415  %tmp54.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]
416  %4 = extractelement <2 x double> %tmp54.i, i32 1 ; <double> [#uses=1]
417  %5 = bitcast double %4 to <2 x float>           ; <<2 x float>> [#uses=1]
418  %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
419  %7 = fmul <4 x float> %6, %6
420  %8 = fadd <4 x float> %7, %7
421  %9 = fadd <4 x float> %8, %8
422  %10 = shufflevector <4 x float> undef, <4 x float> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1]
423  %11 = fmul <4 x float> %10, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
424  %12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
425  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
426  %14 = fmul <4 x float> %13, %13
427  %15 = fadd <4 x float> %14, %14
428  %16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
429  %17 = fmul <4 x float> %16, %16
430  %18 = extractelement <4 x float> %17, i32 2     ; <float> [#uses=1]
431  store float %18, float* undef, align 4
432  br i1 undef, label %exit, label %bb14
433
434exit:          ; preds = %bb.i19
435  unreachable
436
437bb14:                                             ; preds = %bb6
438  ret i32 0
439}
440
441; This test crashes the coalescer because live variables were not updated properly.
442define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind {
443; CHECK-LABEL: t11:
444; CHECK:       @ %bb.0:
445; CHECK-NEXT:    vmov r0, r2, d16
446; CHECK-NEXT:    ldr r3, [sp, #16]
447; CHECK-NEXT:    vmov.i32 d18, #0x0
448; CHECK-NEXT:    vst3.8 {d16, d17, d18}, [r1]
449; CHECK-NEXT:    vst3.8 {d16, d17, d18}, [r3]
450; CHECK-NEXT:    mov r1, r2
451; CHECK-NEXT:    bx lr
452  %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
453  %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1]
454  %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
455  %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1]
456  %tmp2bd = add <8 x i8> zeroinitializer, %tmp2d  ; <<8 x i8>> [#uses=1]
457  %tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1]
458  %tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f  ; <<8 x i8>> [#uses=1]
459  %tmp2efgh = mul <8 x i8> %tmp2ef, undef         ; <<8 x i8>> [#uses=2]
460  call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1)
461  %tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd       ; <<8 x i8>> [#uses=1]
462  %tmp7 = mul <8 x i8> undef, %tmp2               ; <<8 x i8>> [#uses=1]
463  tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1)
464  ret <8 x i8> undef
465}
466
467declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly
468
469declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
470
471declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
472
473declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind
474
475declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
476
477declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
478nounwind
479
480declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
481
482declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly
483
484declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
485
486declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
487
488declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
489
490declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
491
492declare void @llvm.trap() nounwind
493