1*94cddcfcSSimon Pilgrim; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2*94cddcfcSSimon Pilgrim; RUN: llc < %s -mtriple=armv7-- | FileCheck %s 3*94cddcfcSSimon Pilgrim 4*94cddcfcSSimon Pilgrim; Reduced regression test for infinite-loop due to #112710 5*94cddcfcSSimon Pilgrimdefine void @test(i32 %bf.load.i) { 6*94cddcfcSSimon Pilgrim; CHECK-LABEL: test: 7*94cddcfcSSimon Pilgrim; CHECK: @ %bb.0: @ %entry 8*94cddcfcSSimon Pilgrim; CHECK-NEXT: push {r11, lr} 9*94cddcfcSSimon Pilgrim; CHECK-NEXT: vldr d16, .LCPI0_0 10*94cddcfcSSimon Pilgrim; CHECK-NEXT: vmov.i64 q9, #0xffff 11*94cddcfcSSimon Pilgrim; CHECK-NEXT: vdup.32 d17, r0 12*94cddcfcSSimon Pilgrim; CHECK-NEXT: vneg.s32 d16, d16 13*94cddcfcSSimon Pilgrim; CHECK-NEXT: vshl.u32 d16, d17, d16 14*94cddcfcSSimon Pilgrim; CHECK-NEXT: vldr d17, .LCPI0_1 15*94cddcfcSSimon Pilgrim; CHECK-NEXT: vand d16, d16, d17 16*94cddcfcSSimon Pilgrim; CHECK-NEXT: vmovl.u32 q8, d16 17*94cddcfcSSimon Pilgrim; CHECK-NEXT: vand q8, q8, q9 18*94cddcfcSSimon Pilgrim; CHECK-NEXT: vst1.64 {d16, d17}, [r0] 19*94cddcfcSSimon Pilgrim; CHECK-NEXT: bl use 20*94cddcfcSSimon Pilgrim; CHECK-NEXT: .p2align 3 21*94cddcfcSSimon Pilgrim; CHECK-NEXT: @ %bb.1: 22*94cddcfcSSimon Pilgrim; CHECK-NEXT: .LCPI0_0: 23*94cddcfcSSimon Pilgrim; CHECK-NEXT: .long 8 @ 0x8 24*94cddcfcSSimon Pilgrim; CHECK-NEXT: .long 24 @ 0x18 25*94cddcfcSSimon Pilgrim; CHECK-NEXT: .LCPI0_1: 26*94cddcfcSSimon Pilgrim; CHECK-NEXT: .long 4095 @ 0xfff 27*94cddcfcSSimon Pilgrim; CHECK-NEXT: .long 1 @ 0x1 28*94cddcfcSSimon Pilgrimentry: 29*94cddcfcSSimon Pilgrim %0 = insertelement <2 x i32> poison, i32 %bf.load.i, i64 0 30*94cddcfcSSimon Pilgrim %1 = shufflevector <2 x i32> %0, <2 x i32> poison, <2 x i32> zeroinitializer 31*94cddcfcSSimon Pilgrim %2 = lshr <2 x i32> %1, <i32 8, i32 24> 32*94cddcfcSSimon Pilgrim %arrayinit.element1.i = getelementptr inbounds i8, ptr poison, i32 16 33*94cddcfcSSimon Pilgrim %3 = trunc <2 x i32> %2 to <2 x i16> 34*94cddcfcSSimon Pilgrim %4 = and <2 x i16> %3, <i16 4095, i16 1> 35*94cddcfcSSimon Pilgrim %5 = zext nneg <2 x i16> %4 to <2 x i64> 36*94cddcfcSSimon Pilgrim store <2 x i64> %5, ptr %arrayinit.element1.i, align 8 37*94cddcfcSSimon Pilgrim call void @use() 38*94cddcfcSSimon Pilgrim unreachable 39*94cddcfcSSimon Pilgrim} 40*94cddcfcSSimon Pilgrimdeclare void @use() 41