xref: /llvm-project/llvm/test/CodeGen/ARM/neon_vshl_minint.ll (revision b5c627aba864517300df961027dbc85a9d3c142e) 
1*b5c627abSLuke Cheeseman; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
2*b5c627abSLuke Cheeseman; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
3*b5c627abSLuke Cheeseman
4*b5c627abSLuke Cheesemandefine <1 x i64> @vshl_minint() #0 {
5*b5c627abSLuke Cheeseman  entry:
6*b5c627abSLuke Cheeseman    ; CHECK-LABEL: vshl_minint
7*b5c627abSLuke Cheeseman    ; CHECK: vldr
8*b5c627abSLuke Cheeseman    ; CHECK: vshl.u64
9*b5c627abSLuke Cheeseman    %vshl.i = tail call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> undef, <1 x i64> <i64 -9223372036854775808>)
10*b5c627abSLuke Cheeseman    ret <1 x i64> %vshl.i
11*b5c627abSLuke Cheeseman}
12*b5c627abSLuke Cheeseman
13*b5c627abSLuke Cheesemandeclare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
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