1*dcf11c5eSVictor Campos; RUN: llc %s -mtriple=arm -mattr=+armv8.3-a,+fullfp16 -o - | FileCheck %s 2*dcf11c5eSVictor Campos 3*dcf11c5eSVictor Camposdefine <4 x half> @foo16x4_rot(<4 x half> %a, <4 x half> %b) { 4*dcf11c5eSVictor Camposentry: 5*dcf11c5eSVictor Campos; CHECK-LABEL: foo16x4_rot 6*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, #90 7*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, #270 8*dcf11c5eSVictor Campos %vcadd_rot90_v2.i = tail call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %a, <4 x half> %b) 9*dcf11c5eSVictor Campos %vcadd_rot270_v2.i = tail call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %a, <4 x half> %b) 10*dcf11c5eSVictor Campos %add = fadd <4 x half> %vcadd_rot90_v2.i, %vcadd_rot270_v2.i 11*dcf11c5eSVictor Campos ret <4 x half> %add 12*dcf11c5eSVictor Campos} 13*dcf11c5eSVictor Campos 14*dcf11c5eSVictor Camposdefine <2 x float> @foo32x2_rot(<2 x float> %a, <2 x float> %b) { 15*dcf11c5eSVictor Camposentry: 16*dcf11c5eSVictor Campos; CHECK-LABEL: foo32x2_rot 17*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, #90 18*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, #270 19*dcf11c5eSVictor Campos %vcadd_rot90_v2.i = tail call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %a, <2 x float> %b) 20*dcf11c5eSVictor Campos %vcadd_rot270_v2.i = tail call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %a, <2 x float> %b) 21*dcf11c5eSVictor Campos %add = fadd <2 x float> %vcadd_rot90_v2.i, %vcadd_rot270_v2.i 22*dcf11c5eSVictor Campos ret <2 x float> %add 23*dcf11c5eSVictor Campos} 24*dcf11c5eSVictor Campos 25*dcf11c5eSVictor Camposdefine <8 x half> @foo16x8_rot(<8 x half> %a, <8 x half> %b) { 26*dcf11c5eSVictor Camposentry: 27*dcf11c5eSVictor Campos; CHECK-LABEL: foo16x8_rot 28*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #90 29*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270 30*dcf11c5eSVictor Campos %vcaddq_rot90_v2.i = tail call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %a, <8 x half> %b) 31*dcf11c5eSVictor Campos %vcaddq_rot270_v2.i = tail call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %a, <8 x half> %b) 32*dcf11c5eSVictor Campos %add = fadd <8 x half> %vcaddq_rot90_v2.i, %vcaddq_rot270_v2.i 33*dcf11c5eSVictor Campos ret <8 x half> %add 34*dcf11c5eSVictor Campos} 35*dcf11c5eSVictor Campos 36*dcf11c5eSVictor Camposdefine <4 x float> @foo32x4_rot(<4 x float> %a, <4 x float> %b) { 37*dcf11c5eSVictor Camposentry: 38*dcf11c5eSVictor Campos; CHECK-LABEL: foo32x4_rot 39*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #90 40*dcf11c5eSVictor Campos; CHECK-DAG: vcadd.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270 41*dcf11c5eSVictor Campos %vcaddq_rot90_v2.i = tail call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %a, <4 x float> %b) 42*dcf11c5eSVictor Campos %vcaddq_rot270_v2.i = tail call <4 x float> @llvm.arm.neon.vcadd.rot270.v4f32(<4 x float> %a, <4 x float> %b) 43*dcf11c5eSVictor Campos %add = fadd <4 x float> %vcaddq_rot90_v2.i, %vcaddq_rot270_v2.i 44*dcf11c5eSVictor Campos ret <4 x float> %add 45*dcf11c5eSVictor Campos} 46*dcf11c5eSVictor Campos 47*dcf11c5eSVictor Camposdeclare <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half>, <4 x half>) 48*dcf11c5eSVictor Camposdeclare <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half>, <4 x half>) 49*dcf11c5eSVictor Camposdeclare <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float>, <2 x float>) 50*dcf11c5eSVictor Camposdeclare <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float>, <2 x float>) 51*dcf11c5eSVictor Camposdeclare <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half>, <8 x half>) 52*dcf11c5eSVictor Camposdeclare <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half>, <8 x half>) 53*dcf11c5eSVictor Camposdeclare <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float>, <4 x float>) 54*dcf11c5eSVictor Camposdeclare <4 x float> @llvm.arm.neon.vcadd.rot270.v4f32(<4 x float>, <4 x float>) 55