1# Basic machine sched model test for Thumb2 int instructions 2# RUN: llc -o /dev/null %s -mtriple=thumbv7-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \ 3# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT 4# RUN: llc -o /dev/null %s -mtriple=thumbv7--eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \ 5# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 6# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ 7# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 8# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \ 9# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 10# REQUIRES: asserts 11--- | 12 ; ModuleID = 'foo.ll' 13 source_filename = "foo.ll" 14 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 15 target triple = "thumbv7---eabi" 16 17 @g1 = common global i32 0, align 4 18 @g2 = common global i32 0, align 4 19 20 define i64 @foo(i16 signext %a, i16 signext %b) { 21 entry: 22 %0 = load i32, ptr @g1, align 4 23 %1 = load i32, ptr @g2, align 4 24 %2 = add nuw nsw i32 %0, %0 25 %3 = sdiv i32 %2, %1 26 store i32 %3, ptr @g1, align 4 27 %d = mul nsw i16 %a, %a 28 %e = mul nsw i16 %b, %b 29 %f = add nuw nsw i16 %e, %d 30 %c = zext i16 %f to i32 31 %mul8 = mul nsw i32 %c, %3 32 %mul9 = mul nsw i32 %mul8, %mul8 33 %add10 = add nuw nsw i32 %mul9, %mul8 34 %conv1130 = zext i32 %add10 to i64 35 %mul12 = mul nuw nsw i64 %conv1130, %conv1130 36 %mul13 = mul nsw i64 %mul12, %mul12 37 %add14 = add nuw nsw i64 %mul13, %mul12 38 ret i64 %add14 39 } 40# 41# CHECK: ********** MI Scheduling ********** 42# CHECK: SU(2): %2:rgpr = t2MOVi32imm @g1 43# CHECK_A9: Latency : 2 44# CHECK_SWIFT: Latency : 2 45# CHECK_R52: Latency : 2 46# 47# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg :: (dereferenceable load (s32) from @g1) 48# CHECK_A9: Latency : 1 49# CHECK_SWIFT: Latency : 3 50# CHECK_R52: Latency : 4 51# 52# CHECK: SU(6): %6:rgpr = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg 53# CHECK_A9: Latency : 1 54# CHECK_SWIFT: Latency : 1 55# CHECK_R52: Latency : 3 56 57# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, $noreg 58# CHECK_A9: Latency : 0 59# CHECK_SWIFT: Latency : 14 60# CHECK_R52: Latency : 8 61 62# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg :: (store (s32) into @g1) 63# CHECK_A9: Latency : 1 64# CHECK_SWIFT: Latency : 0 65# CHECK_R52: Latency : 4 66# 67# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, $noreg 68# CHECK_A9: Latency : 2 69# CHECK_SWIFT: Latency : 4 70# CHECK_R52: Latency : 4 71# 72# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, $noreg 73# CHECK_A9: Latency : 2 74# CHECK_SWIFT: Latency : 4 75# CHECK_R52: Latency : 4 76# 77# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, $noreg 78# CHECK_A9: Latency : 1 79# CHECK_SWIFT: Latency : 1 80# CHECK_R52: Latency : 3 81# 82# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, $noreg 83# CHECK_A9: Latency : 2 84# CHECK_SWIFT: Latency : 4 85# CHECK_R52: Latency : 4 86# 87# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, $noreg 88# CHECK_A9: Latency : 2 89# CHECK_SWIFT: Latency : 4 90# CHECK_R52: Latency : 4 91# 92# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, $noreg 93# CHECK_A9: Latency : 3 94# CHECK_SWIFT: Latency : 5 95# CHECK_R52: Latency : 4 96# 97# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr(tied-def 0), %20:rgpr(tied-def 1), 14, $noreg 98# CHECK_A9: Latency : 3 99# CHECK_SWIFT: Latency : 7 100# CHECK_R52: Latency : 4 101# CHECK: ** ScheduleDAGMILive::schedule picking next node 102... 103--- 104name: foo 105alignment: 2 106exposesReturnsTwice: false 107legalized: false 108regBankSelected: false 109selected: false 110tracksRegLiveness: true 111registers: 112 - { id: 0, class: rgpr } 113 - { id: 1, class: rgpr } 114 - { id: 2, class: rgpr } 115 - { id: 3, class: rgpr } 116 - { id: 4, class: rgpr } 117 - { id: 5, class: rgpr } 118 - { id: 6, class: rgpr } 119 - { id: 7, class: rgpr } 120 - { id: 8, class: rgpr } 121 - { id: 9, class: rgpr } 122 - { id: 10, class: rgpr } 123 - { id: 11, class: rgpr } 124 - { id: 12, class: rgpr } 125 - { id: 13, class: rgpr } 126 - { id: 14, class: rgpr } 127 - { id: 15, class: rgpr } 128 - { id: 16, class: rgpr } 129 - { id: 17, class: rgpr } 130 - { id: 18, class: rgpr } 131 - { id: 19, class: rgpr } 132 - { id: 20, class: rgpr } 133liveins: 134 - { reg: '$r0', virtual-reg: '%0' } 135 - { reg: '$r1', virtual-reg: '%1' } 136frameInfo: 137 isFrameAddressTaken: false 138 isReturnAddressTaken: false 139 hasStackMap: false 140 hasPatchPoint: false 141 stackSize: 0 142 offsetAdjustment: 0 143 maxAlignment: 0 144 adjustsStack: false 145 hasCalls: false 146 maxCallFrameSize: 0 147 hasOpaqueSPAdjustment: false 148 hasVAStart: false 149 hasMustTailInVarArgFunc: false 150body: | 151 bb.0.entry: 152 liveins: $r0, $r1 153 154 %1 = COPY $r1 155 %0 = COPY $r0 156 %2 = t2MOVi32imm @g1 157 %3 = t2LDRi12 %2, 0, 14, $noreg :: (dereferenceable load (s32) from @g1) 158 %4 = t2MOVi32imm @g2 159 %5 = t2LDRi12 %4, 0, 14, $noreg :: (dereferenceable load (s32) from @g2) 160 %6 = t2ADDrr %3, %3, 14, $noreg, $noreg 161 %7 = t2SDIV %6, %5, 14, $noreg 162 t2STRi12 %7, %2, 0, 14, $noreg :: (store (s32) into @g1) 163 %8 = t2SMULBB %1, %1, 14, $noreg 164 %9 = t2SMLABB %0, %0, %8, 14, $noreg 165 %10 = t2UXTH %9, 0, 14, $noreg 166 %11 = t2MUL %10, %7, 14, $noreg 167 %12 = t2MLA %11, %11, %11, 14, $noreg 168 %13, %14 = t2UMULL %12, %12, 14, $noreg 169 %19, %16 = t2UMULL %13, %13, 14, $noreg 170 %17 = t2MLA %13, %14, %16, 14, $noreg 171 %20 = t2MLA %13, %14, %17, 14, $noreg 172 %19, %20 = t2UMLAL %12, %12, %19, %20, 14, $noreg 173 $r0 = COPY %19 174 $r1 = COPY %20 175 tBX_RET 14, $noreg, implicit $r0, implicit $r1 176 177... 178