1; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s 2 3define void @t1(i8* nocapture %c) nounwind optsize { 4entry: 5; CHECK-LABEL: t1: 6 7;; FIXME: like with arm64-memset-inline.ll, learning how to merge 8;; stores made this code worse, since it now uses a vector move, 9;; instead of just using an strd instruction taking two registers. 10 11; CHECK: vmov.i32 d16, #0x0 12; CHECK: vst1.32 {d16}, [r0:64]! 13; CHECK: movs r1, #0 14; CHECK: str r1, [r0] 15 call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false) 16 ret void 17} 18 19define void @t2() nounwind ssp { 20entry: 21; CHECK-LABEL: t2: 22; CHECK: add.w r1, r0, #10 23; CHECK: vmov.i32 {{q[0-9]+}}, #0x0 24; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] 25; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] 26 %buf = alloca [26 x i8], align 1 27 %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 28 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) 29 call void @something(i8* %0) nounwind 30 ret void 31} 32 33declare void @something(i8*) nounwind 34declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind 35declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind 36