1*4b7239ebSOliver Stannard; RUN: llc -mtriple armv7a--none-eabi < %s | FileCheck %s 2*4b7239ebSOliver Stannard; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s 3*4b7239ebSOliver Stannard 4*4b7239ebSOliver Stannard; Other targets disable callee-saved registers for internal functions when 5*4b7239ebSOliver Stannard; using IPRA, but that isn't profitable for ARM because the PUSH/POP 6*4b7239ebSOliver Stannard; instructions can more efficiently save registers than using individual 7*4b7239ebSOliver Stannard; LDR/STRs in the caller. 8*4b7239ebSOliver Stannard 9*4b7239ebSOliver Stannarddefine internal void @callee() norecurse { 10*4b7239ebSOliver Stannard; CHECK-LABEL: callee: 11*4b7239ebSOliver Stannardentry: 12*4b7239ebSOliver Stannard; CHECK: push {r4, lr} 13*4b7239ebSOliver Stannard; CHECK: pop {r4, pc} 14*4b7239ebSOliver Stannard tail call void asm sideeffect "", "~{r4}"() 15*4b7239ebSOliver Stannard ret void 16*4b7239ebSOliver Stannard} 17*4b7239ebSOliver Stannard 18*4b7239ebSOliver Stannarddefine void @caller() { 19*4b7239ebSOliver Stannardentry: 20*4b7239ebSOliver Stannard call void @callee() 21*4b7239ebSOliver Stannard ret void 22*4b7239ebSOliver Stannard} 23