1; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM 2; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6 3; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7 4 5define i32 @uadd_overflow(i32 %a, i32 %b) #0 { 6 %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) 7 %1 = extractvalue { i32, i1 } %sadd, 1 8 %2 = zext i1 %1 to i32 9 ret i32 %2 10 11 ; CHECK-LABEL: uadd_overflow: 12 13 ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 14 ; ARM: mov r[[R2:[0-9]+]], #0 15 ; ARM: adc r[[R0]], r[[R2]], #0 16 17 ; THUMBV6: movs r[[R2:[0-9]+]], #0 18 ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 19 ; THUMBV6: adcs r[[R2]], r[[R2]] 20 ; THUMBV6: mov r[[R0]], r[[R2]] 21 22 ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 23 ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 24 ; THUMBV7: adc r[[R0]], r[[R2]], #0 25} 26 27 28define i32 @sadd_overflow(i32 %a, i32 %b) #0 { 29 %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) 30 %1 = extractvalue { i32, i1 } %sadd, 1 31 %2 = zext i1 %1 to i32 32 ret i32 %2 33 34 ; CHECK-LABEL: sadd_overflow: 35 36 ; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] 37 ; ARM: mov r[[R0]], #1 38 ; ARM: movvc r[[R0]], #0 39 ; ARM: mov pc, lr 40 41 ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]] 42 ; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]] 43 ; THUMBV6: movs r[[R0]], #0 44 ; THUMBV6: movs r[[R1]], #1 45 ; THUMBV6: cmp r[[R3]], r[[R2]] 46 ; THUMBV6: bvc .L[[LABEL:.*]] 47 ; THUMBV6: mov r[[R0]], r[[R1]] 48 ; THUMBV6: .L[[LABEL]]: 49 50 ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 51 ; THUMBV7: mov.w r[[R0:[0-9]+]], #1 52 ; THUMBV7: it vc 53 ; THUMBV7: movvc r[[R0]], #0 54} 55 56define i32 @usub_overflow(i32 %a, i32 %b) #0 { 57 %sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) 58 %1 = extractvalue { i32, i1 } %sadd, 1 59 %2 = zext i1 %1 to i32 60 ret i32 %2 61 62 ; CHECK-LABEL: usub_overflow: 63 64 ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 65 ; ARM: mov r[[R2:[0-9]+]], #0 66 ; ARM: adc r[[R0]], r[[R2]], #0 67 ; ARM: rsb r[[R0]], r[[R0]], #1 68 69 ; THUMBV6: movs r[[R2:[0-9]+]], #0 70 ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 71 ; THUMBV6: adcs r[[R2]], r[[R2]] 72 ; THUMBV6: movs r[[R0]], #1 73 ; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]] 74 75 ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 76 ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 77 ; THUMBV7: adc r[[R0]], r[[R2]], #0 78 ; THUMBV7: rsb.w r[[R0]], r[[R0]], #1 79 80 ; We should know that the overflow is just 1 bit, 81 ; no need to clear any other bit 82 ; CHECK-NOT: and 83} 84 85define i32 @ssub_overflow(i32 %a, i32 %b) #0 { 86 %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) 87 %1 = extractvalue { i32, i1 } %sadd, 1 88 %2 = zext i1 %1 to i32 89 ret i32 %2 90 91 ; CHECK-LABEL: ssub_overflow: 92 93 ; ARM: mov r[[R2]], #1 94 ; ARM: cmp r[[R0]], r[[R1]] 95 ; ARM: movvc r[[R2]], #0 96 97 ; THUMBV6: movs r[[R0]], #0 98 ; THUMBV6: movs r[[R3:[0-9]+]], #1 99 ; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]] 100 ; THUMBV6: bvc .L[[LABEL:.*]] 101 ; THUMBV6: mov r[[R0]], r[[R3]] 102 ; THUMBV6: .L[[LABEL]]: 103 104 ; THUMBV7: movs r[[R2:[0-9]+]], #1 105 ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]] 106 ; THUMBV7: it vc 107 ; THUMBV7: movvc r[[R2]], #0 108 ; THUMBV7: mov r[[R0]], r[[R2]] 109} 110 111declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 112declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2 113declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3 114declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4 115