1; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM 2; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6 3; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7 4 5define i32 @uadd_overflow(i32 %a, i32 %b) #0 { 6 %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) 7 %1 = extractvalue { i32, i1 } %sadd, 1 8 %2 = zext i1 %1 to i32 9 ret i32 %2 10 11 ; CHECK-LABEL: uadd_overflow: 12 13 ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 14 ; ARM: mov r[[R2:[0-9]+]], #0 15 ; ARM: adc r[[R0]], r[[R2]], #0 16 17 ; THUMBV6: movs r[[R2:[0-9]+]], #0 18 ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 19 ; THUMBV6: adcs r[[R2]], r[[R2]] 20 ; THUMBV6: mov r[[R0]], r[[R2]] 21 22 ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 23 ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 24 ; THUMBV7: adc r[[R0]], r[[R2]], #0 25} 26 27 28define i32 @sadd_overflow(i32 %a, i32 %b) #0 { 29 %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) 30 %1 = extractvalue { i32, i1 } %sadd, 1 31 %2 = zext i1 %1 to i32 32 ret i32 %2 33 34 ; CHECK-LABEL: sadd_overflow: 35 36 ; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] 37 ; ARM: mov r[[R0]], #1 38 ; ARM: movvc r[[R0]], #0 39 ; ARM: mov pc, lr 40 41 ; THUMBV6: adds r1, r0, r1 42 ; THUMBV6: cmp r1, r0 43 ; THUMBV6: bvc .LBB1_2 44 45 ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 46 ; THUMBV7: mov.w r[[R0:[0-9]+]], #1 47 ; THUMBV7: it vc 48 ; THUMBV7: movvc r[[R0]], #0 49} 50 51define i32 @usub_overflow(i32 %a, i32 %b) #0 { 52 %sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) 53 %1 = extractvalue { i32, i1 } %sadd, 1 54 %2 = zext i1 %1 to i32 55 ret i32 %2 56 57 ; CHECK-LABEL: usub_overflow: 58 59 ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 60 ; ARM: mov r[[R2:[0-9]+]], #0 61 ; ARM: adc r[[R0]], r[[R2]], #0 62 ; ARM: rsb r[[R0]], r[[R0]], #1 63 64 ; THUMBV6: movs r[[R2:[0-9]+]], #0 65 ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 66 ; THUMBV6: adcs r[[R2]], r[[R2]] 67 ; THUMBV6: movs r[[R0]], #1 68 ; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]] 69 70 ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] 71 ; THUMBV7: mov.w r[[R2:[0-9]+]], #0 72 ; THUMBV7: adc r[[R0]], r[[R2]], #0 73 ; THUMBV7: rsb.w r[[R0]], r[[R0]], #1 74 75 ; We should know that the overflow is just 1 bit, 76 ; no need to clear any other bit 77 ; CHECK-NOT: and 78} 79 80define i32 @ssub_overflow(i32 %a, i32 %b) #0 { 81 %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) 82 %1 = extractvalue { i32, i1 } %sadd, 1 83 %2 = zext i1 %1 to i32 84 ret i32 %2 85 86 ; CHECK-LABEL: ssub_overflow: 87 88 ; ARM: mov r[[R2]], #1 89 ; ARM: cmp r[[R0]], r[[R1]] 90 ; ARM: movvc r[[R2]], #0 91 92 ; THUMBV6: cmp r0, r1 93 ; THUMBV6: bvc .LBB3_2 94 95 ; THUMBV7: movs r[[R2:[0-9]+]], #1 96 ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]] 97 ; THUMBV7: it vc 98 ; THUMBV7: movvc r[[R2]], #0 99 ; THUMBV7: mov r[[R0]], r[[R2]] 100} 101 102declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 103declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2 104declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3 105declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4 106