1; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as %s -o - \ 2; RUN: | FileCheck %s 3 4; Radar 7449043 5%struct.int32x4_t = type { <4 x i32> } 6 7define void @t() nounwind { 8entry: 9; CHECK-LABEL: t 10; CHECK: vmov.I64 q15, #0 11; CHECK: vmov.32 d30[0], 12; CHECK: vmov q8, q15 13 %tmp = alloca %struct.int32x4_t, align 16 14 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind 15 ret void 16} 17 18; Radar 7457110 19%struct.int32x2_t = type { <4 x i32> } 20 21define void @t2() nounwind { 22entry: 23; CHECK-LABEL: t2 24; CHECK: vmov d30, d16 25; CHECK: vmov.32 r0, d30[0] 26 %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind 27 ret void 28} 29 30; Radar 9306086 31 32%0 = type { <8 x i8>, <16 x i8>* } 33 34define hidden void @conv4_8_E() nounwind { 35entry: 36%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind 37unreachable 38} 39 40; Radar 9037836 & 9119939 41 42define i32 @t3() nounwind { 43entry: 44tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind 45ret i32 0 46} 47 48; Radar 9037836 & 9119939 49 50@k.2126 = internal unnamed_addr global float 1.000000e+00 51define i32 @t4() nounwind { 52entry: 53call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind 54ret i32 0 55} 56 57; Radar 9037836 & 9119939 58 59define i32 @t5() nounwind { 60entry: 61call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind 62ret i32 0 63} 64 65; Radar 9307836 & 9119939 66 67define float @t6(float %y) nounwind { 68entry: 69; CHECK-LABEL: t6 70; CHECK: flds s15, s0 71 %0 = tail call float asm "flds s15, $0", "=x"() nounwind 72 ret float %0 73} 74 75; Radar 9307836 & 9119939 76 77define double @t7(double %y) nounwind { 78entry: 79; CHECK-LABEL: t7 80; CHECK: flds s15, d0 81 %0 = tail call double asm "flds s15, $0", "=x"() nounwind 82 ret double %0 83} 84 85; Radar 9307836 & 9119939 86 87define float @t8(float %y) nounwind { 88entry: 89; CHECK-LABEL: t8 90; CHECK: flds s15, s0 91 %0 = tail call float asm "flds s15, $0", "=t"() nounwind 92 ret float %0 93} 94 95; Radar 9307836 & 9119939 96 97define i32 @t9(i32 %r0) nounwind { 98entry: 99; CHECK-LABEL: t9 100; CHECK: movw r0, #27182 101 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind 102 ret i32 %0 103} 104 105; Radar 9866494 106 107define void @t10(i8* %f, i32 %g) nounwind { 108entry: 109; CHECK-LABEL: t10 110; CHECK: str r1, [r0] 111 %f.addr = alloca i8*, align 4 112 store i8* %f, i8** %f.addr, align 4 113 call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 114 ret void 115} 116 117; Radar 10551006 118 119define <4 x i32> @t11(i32* %p) nounwind { 120entry: 121; CHECK-LABEL: t11 122; CHECK: vld1.s32 {d16[], d17[]}, [r0] 123 %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind 124 ret <4 x i32> %0 125} 126 127; Bugzilla PR26038 128 129define i32 @fn1() local_unnamed_addr nounwind { 130; CHECK-LABEL: fn1 131entry: 132; CHECK: mov [[addr:r[0-9]+]], #5 133; CHECK: ldrh {{.*}}[[addr]] 134 %0 = tail call i32 asm "ldrh $0, $1", "=r,*Q"(i8* inttoptr (i32 5 to i8*)) nounwind 135 ret i32 %0 136} 137