1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM6 3; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM78 4; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM78 5; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB,THUMB6 6; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB,THUMB78 7; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB,THUMB78 8 9; We are looking for the following pattern here: 10; (X & (C l>> Y)) ==/!= 0 11; It may be optimal to hoist the constant: 12; ((X << Y) & C) ==/!= 0 13 14;------------------------------------------------------------------------------; 15; A few scalar test 16;------------------------------------------------------------------------------; 17 18; i8 scalar 19 20define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind { 21; ARM-LABEL: scalar_i8_signbit_eq: 22; ARM: @ %bb.0: 23; ARM-NEXT: uxtb r1, r1 24; ARM-NEXT: lsl r0, r0, r1 25; ARM-NEXT: mov r1, #1 26; ARM-NEXT: uxtb r0, r0 27; ARM-NEXT: eor r0, r1, r0, lsr #7 28; ARM-NEXT: bx lr 29; 30; THUMB6-LABEL: scalar_i8_signbit_eq: 31; THUMB6: @ %bb.0: 32; THUMB6-NEXT: uxtb r1, r1 33; THUMB6-NEXT: lsls r0, r1 34; THUMB6-NEXT: movs r1, #128 35; THUMB6-NEXT: ands r0, r1 36; THUMB6-NEXT: rsbs r1, r0, #0 37; THUMB6-NEXT: adcs r0, r1 38; THUMB6-NEXT: bx lr 39; 40; THUMB78-LABEL: scalar_i8_signbit_eq: 41; THUMB78: @ %bb.0: 42; THUMB78-NEXT: uxtb r1, r1 43; THUMB78-NEXT: lsls r0, r1 44; THUMB78-NEXT: movs r1, #1 45; THUMB78-NEXT: uxtb r0, r0 46; THUMB78-NEXT: eor.w r0, r1, r0, lsr #7 47; THUMB78-NEXT: bx lr 48 %t0 = lshr i8 128, %y 49 %t1 = and i8 %t0, %x 50 %res = icmp eq i8 %t1, 0 51 ret i1 %res 52} 53 54define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind { 55; ARM-LABEL: scalar_i8_lowestbit_eq: 56; ARM: @ %bb.0: 57; ARM-NEXT: uxtb r1, r1 58; ARM-NEXT: mov r2, #1 59; ARM-NEXT: bic r0, r2, r0, lsl r1 60; ARM-NEXT: bx lr 61; 62; THUMB6-LABEL: scalar_i8_lowestbit_eq: 63; THUMB6: @ %bb.0: 64; THUMB6-NEXT: uxtb r1, r1 65; THUMB6-NEXT: lsls r0, r1 66; THUMB6-NEXT: movs r1, #1 67; THUMB6-NEXT: ands r0, r1 68; THUMB6-NEXT: rsbs r1, r0, #0 69; THUMB6-NEXT: adcs r0, r1 70; THUMB6-NEXT: bx lr 71; 72; THUMB78-LABEL: scalar_i8_lowestbit_eq: 73; THUMB78: @ %bb.0: 74; THUMB78-NEXT: uxtb r1, r1 75; THUMB78-NEXT: lsls r0, r1 76; THUMB78-NEXT: movs r1, #1 77; THUMB78-NEXT: bic.w r0, r1, r0 78; THUMB78-NEXT: bx lr 79 %t0 = lshr i8 1, %y 80 %t1 = and i8 %t0, %x 81 %res = icmp eq i8 %t1, 0 82 ret i1 %res 83} 84 85define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind { 86; ARM-LABEL: scalar_i8_bitsinmiddle_eq: 87; ARM: @ %bb.0: 88; ARM-NEXT: uxtb r1, r1 89; ARM-NEXT: mov r2, #24 90; ARM-NEXT: and r0, r2, r0, lsl r1 91; ARM-NEXT: clz r0, r0 92; ARM-NEXT: lsr r0, r0, #5 93; ARM-NEXT: bx lr 94; 95; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq: 96; THUMB6: @ %bb.0: 97; THUMB6-NEXT: uxtb r1, r1 98; THUMB6-NEXT: lsls r0, r1 99; THUMB6-NEXT: movs r1, #24 100; THUMB6-NEXT: ands r0, r1 101; THUMB6-NEXT: rsbs r1, r0, #0 102; THUMB6-NEXT: adcs r0, r1 103; THUMB6-NEXT: bx lr 104; 105; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq: 106; THUMB78: @ %bb.0: 107; THUMB78-NEXT: uxtb r1, r1 108; THUMB78-NEXT: lsls r0, r1 109; THUMB78-NEXT: and r0, r0, #24 110; THUMB78-NEXT: clz r0, r0 111; THUMB78-NEXT: lsrs r0, r0, #5 112; THUMB78-NEXT: bx lr 113 %t0 = lshr i8 24, %y 114 %t1 = and i8 %t0, %x 115 %res = icmp eq i8 %t1, 0 116 ret i1 %res 117} 118 119; i16 scalar 120 121define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind { 122; ARM-LABEL: scalar_i16_signbit_eq: 123; ARM: @ %bb.0: 124; ARM-NEXT: uxth r1, r1 125; ARM-NEXT: lsl r0, r0, r1 126; ARM-NEXT: mov r1, #1 127; ARM-NEXT: uxth r0, r0 128; ARM-NEXT: eor r0, r1, r0, lsr #15 129; ARM-NEXT: bx lr 130; 131; THUMB6-LABEL: scalar_i16_signbit_eq: 132; THUMB6: @ %bb.0: 133; THUMB6-NEXT: uxth r1, r1 134; THUMB6-NEXT: lsls r0, r1 135; THUMB6-NEXT: movs r1, #1 136; THUMB6-NEXT: lsls r1, r1, #15 137; THUMB6-NEXT: ands r0, r1 138; THUMB6-NEXT: rsbs r1, r0, #0 139; THUMB6-NEXT: adcs r0, r1 140; THUMB6-NEXT: bx lr 141; 142; THUMB78-LABEL: scalar_i16_signbit_eq: 143; THUMB78: @ %bb.0: 144; THUMB78-NEXT: uxth r1, r1 145; THUMB78-NEXT: lsls r0, r1 146; THUMB78-NEXT: movs r1, #1 147; THUMB78-NEXT: uxth r0, r0 148; THUMB78-NEXT: eor.w r0, r1, r0, lsr #15 149; THUMB78-NEXT: bx lr 150 %t0 = lshr i16 32768, %y 151 %t1 = and i16 %t0, %x 152 %res = icmp eq i16 %t1, 0 153 ret i1 %res 154} 155 156define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind { 157; ARM-LABEL: scalar_i16_lowestbit_eq: 158; ARM: @ %bb.0: 159; ARM-NEXT: uxth r1, r1 160; ARM-NEXT: mov r2, #1 161; ARM-NEXT: bic r0, r2, r0, lsl r1 162; ARM-NEXT: bx lr 163; 164; THUMB6-LABEL: scalar_i16_lowestbit_eq: 165; THUMB6: @ %bb.0: 166; THUMB6-NEXT: uxth r1, r1 167; THUMB6-NEXT: lsls r0, r1 168; THUMB6-NEXT: movs r1, #1 169; THUMB6-NEXT: ands r0, r1 170; THUMB6-NEXT: rsbs r1, r0, #0 171; THUMB6-NEXT: adcs r0, r1 172; THUMB6-NEXT: bx lr 173; 174; THUMB78-LABEL: scalar_i16_lowestbit_eq: 175; THUMB78: @ %bb.0: 176; THUMB78-NEXT: uxth r1, r1 177; THUMB78-NEXT: lsls r0, r1 178; THUMB78-NEXT: movs r1, #1 179; THUMB78-NEXT: bic.w r0, r1, r0 180; THUMB78-NEXT: bx lr 181 %t0 = lshr i16 1, %y 182 %t1 = and i16 %t0, %x 183 %res = icmp eq i16 %t1, 0 184 ret i1 %res 185} 186 187define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind { 188; ARM-LABEL: scalar_i16_bitsinmiddle_eq: 189; ARM: @ %bb.0: 190; ARM-NEXT: uxth r1, r1 191; ARM-NEXT: mov r2, #4080 192; ARM-NEXT: and r0, r2, r0, lsl r1 193; ARM-NEXT: clz r0, r0 194; ARM-NEXT: lsr r0, r0, #5 195; ARM-NEXT: bx lr 196; 197; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq: 198; THUMB6: @ %bb.0: 199; THUMB6-NEXT: uxth r1, r1 200; THUMB6-NEXT: lsls r0, r1 201; THUMB6-NEXT: movs r1, #255 202; THUMB6-NEXT: lsls r1, r1, #4 203; THUMB6-NEXT: ands r0, r1 204; THUMB6-NEXT: rsbs r1, r0, #0 205; THUMB6-NEXT: adcs r0, r1 206; THUMB6-NEXT: bx lr 207; 208; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq: 209; THUMB78: @ %bb.0: 210; THUMB78-NEXT: uxth r1, r1 211; THUMB78-NEXT: lsls r0, r1 212; THUMB78-NEXT: and r0, r0, #4080 213; THUMB78-NEXT: clz r0, r0 214; THUMB78-NEXT: lsrs r0, r0, #5 215; THUMB78-NEXT: bx lr 216 %t0 = lshr i16 4080, %y 217 %t1 = and i16 %t0, %x 218 %res = icmp eq i16 %t1, 0 219 ret i1 %res 220} 221 222; i32 scalar 223 224define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind { 225; ARM-LABEL: scalar_i32_signbit_eq: 226; ARM: @ %bb.0: 227; ARM-NEXT: mvn r0, r0, lsl r1 228; ARM-NEXT: lsr r0, r0, #31 229; ARM-NEXT: bx lr 230; 231; THUMB6-LABEL: scalar_i32_signbit_eq: 232; THUMB6: @ %bb.0: 233; THUMB6-NEXT: lsls r0, r1 234; THUMB6-NEXT: movs r1, #1 235; THUMB6-NEXT: lsls r1, r1, #31 236; THUMB6-NEXT: ands r0, r1 237; THUMB6-NEXT: rsbs r1, r0, #0 238; THUMB6-NEXT: adcs r0, r1 239; THUMB6-NEXT: bx lr 240; 241; THUMB78-LABEL: scalar_i32_signbit_eq: 242; THUMB78: @ %bb.0: 243; THUMB78-NEXT: lsls r0, r1 244; THUMB78-NEXT: mvns r0, r0 245; THUMB78-NEXT: lsrs r0, r0, #31 246; THUMB78-NEXT: bx lr 247 %t0 = lshr i32 2147483648, %y 248 %t1 = and i32 %t0, %x 249 %res = icmp eq i32 %t1, 0 250 ret i1 %res 251} 252 253define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind { 254; ARM-LABEL: scalar_i32_lowestbit_eq: 255; ARM: @ %bb.0: 256; ARM-NEXT: mov r2, #1 257; ARM-NEXT: bic r0, r2, r0, lsl r1 258; ARM-NEXT: bx lr 259; 260; THUMB6-LABEL: scalar_i32_lowestbit_eq: 261; THUMB6: @ %bb.0: 262; THUMB6-NEXT: lsls r0, r1 263; THUMB6-NEXT: movs r1, #1 264; THUMB6-NEXT: ands r0, r1 265; THUMB6-NEXT: rsbs r1, r0, #0 266; THUMB6-NEXT: adcs r0, r1 267; THUMB6-NEXT: bx lr 268; 269; THUMB78-LABEL: scalar_i32_lowestbit_eq: 270; THUMB78: @ %bb.0: 271; THUMB78-NEXT: lsls r0, r1 272; THUMB78-NEXT: movs r1, #1 273; THUMB78-NEXT: bic.w r0, r1, r0 274; THUMB78-NEXT: bx lr 275 %t0 = lshr i32 1, %y 276 %t1 = and i32 %t0, %x 277 %res = icmp eq i32 %t1, 0 278 ret i1 %res 279} 280 281define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind { 282; ARM6-LABEL: scalar_i32_bitsinmiddle_eq: 283; ARM6: @ %bb.0: 284; ARM6-NEXT: mov r2, #65280 285; ARM6-NEXT: orr r2, r2, #16711680 286; ARM6-NEXT: and r0, r2, r0, lsl r1 287; ARM6-NEXT: clz r0, r0 288; ARM6-NEXT: lsr r0, r0, #5 289; ARM6-NEXT: bx lr 290; 291; ARM78-LABEL: scalar_i32_bitsinmiddle_eq: 292; ARM78: @ %bb.0: 293; ARM78-NEXT: movw r2, #65280 294; ARM78-NEXT: movt r2, #255 295; ARM78-NEXT: and r0, r2, r0, lsl r1 296; ARM78-NEXT: clz r0, r0 297; ARM78-NEXT: lsr r0, r0, #5 298; ARM78-NEXT: bx lr 299; 300; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq: 301; THUMB6: @ %bb.0: 302; THUMB6-NEXT: lsls r0, r1 303; THUMB6-NEXT: ldr r1, .LCPI8_0 304; THUMB6-NEXT: ands r0, r1 305; THUMB6-NEXT: rsbs r1, r0, #0 306; THUMB6-NEXT: adcs r0, r1 307; THUMB6-NEXT: bx lr 308; THUMB6-NEXT: .p2align 2 309; THUMB6-NEXT: @ %bb.1: 310; THUMB6-NEXT: .LCPI8_0: 311; THUMB6-NEXT: .long 16776960 @ 0xffff00 312; 313; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq: 314; THUMB78: @ %bb.0: 315; THUMB78-NEXT: lsls r0, r1 316; THUMB78-NEXT: movw r1, #65280 317; THUMB78-NEXT: movt r1, #255 318; THUMB78-NEXT: ands r0, r1 319; THUMB78-NEXT: clz r0, r0 320; THUMB78-NEXT: lsrs r0, r0, #5 321; THUMB78-NEXT: bx lr 322 %t0 = lshr i32 16776960, %y 323 %t1 = and i32 %t0, %x 324 %res = icmp eq i32 %t1, 0 325 ret i1 %res 326} 327 328; i64 scalar 329 330define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind { 331; ARM-LABEL: scalar_i64_signbit_eq: 332; ARM: @ %bb.0: 333; ARM-NEXT: rsb r3, r2, #32 334; ARM-NEXT: lsr r3, r0, r3 335; ARM-NEXT: orr r1, r3, r1, lsl r2 336; ARM-NEXT: subs r2, r2, #32 337; ARM-NEXT: lslpl r1, r0, r2 338; ARM-NEXT: mvn r0, r1 339; ARM-NEXT: lsr r0, r0, #31 340; ARM-NEXT: bx lr 341; 342; THUMB6-LABEL: scalar_i64_signbit_eq: 343; THUMB6: @ %bb.0: 344; THUMB6-NEXT: push {r7, lr} 345; THUMB6-NEXT: bl __ashldi3 346; THUMB6-NEXT: movs r0, #1 347; THUMB6-NEXT: lsls r2, r0, #31 348; THUMB6-NEXT: ands r2, r1 349; THUMB6-NEXT: rsbs r0, r2, #0 350; THUMB6-NEXT: adcs r0, r2 351; THUMB6-NEXT: pop {r7, pc} 352; 353; THUMB78-LABEL: scalar_i64_signbit_eq: 354; THUMB78: @ %bb.0: 355; THUMB78-NEXT: rsb.w r3, r2, #32 356; THUMB78-NEXT: lsls r1, r2 357; THUMB78-NEXT: subs r2, #32 358; THUMB78-NEXT: lsr.w r3, r0, r3 359; THUMB78-NEXT: orr.w r1, r1, r3 360; THUMB78-NEXT: it pl 361; THUMB78-NEXT: lslpl.w r1, r0, r2 362; THUMB78-NEXT: mvns r0, r1 363; THUMB78-NEXT: lsrs r0, r0, #31 364; THUMB78-NEXT: bx lr 365 %t0 = lshr i64 9223372036854775808, %y 366 %t1 = and i64 %t0, %x 367 %res = icmp eq i64 %t1, 0 368 ret i1 %res 369} 370 371define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind { 372; ARM6-LABEL: scalar_i64_lowestbit_eq: 373; ARM6: @ %bb.0: 374; ARM6-NEXT: subs r1, r2, #32 375; ARM6-NEXT: lsl r0, r0, r2 376; ARM6-NEXT: movpl r0, #0 377; ARM6-NEXT: mov r1, #1 378; ARM6-NEXT: bic r0, r1, r0 379; ARM6-NEXT: bx lr 380; 381; ARM78-LABEL: scalar_i64_lowestbit_eq: 382; ARM78: @ %bb.0: 383; ARM78-NEXT: subs r1, r2, #32 384; ARM78-NEXT: lsl r0, r0, r2 385; ARM78-NEXT: movwpl r0, #0 386; ARM78-NEXT: mov r1, #1 387; ARM78-NEXT: bic r0, r1, r0 388; ARM78-NEXT: bx lr 389; 390; THUMB6-LABEL: scalar_i64_lowestbit_eq: 391; THUMB6: @ %bb.0: 392; THUMB6-NEXT: push {r7, lr} 393; THUMB6-NEXT: bl __ashldi3 394; THUMB6-NEXT: movs r1, #1 395; THUMB6-NEXT: ands r0, r1 396; THUMB6-NEXT: rsbs r1, r0, #0 397; THUMB6-NEXT: adcs r0, r1 398; THUMB6-NEXT: pop {r7, pc} 399; 400; THUMB78-LABEL: scalar_i64_lowestbit_eq: 401; THUMB78: @ %bb.0: 402; THUMB78-NEXT: lsls r0, r2 403; THUMB78-NEXT: subs.w r1, r2, #32 404; THUMB78-NEXT: it pl 405; THUMB78-NEXT: movpl r0, #0 406; THUMB78-NEXT: movs r1, #1 407; THUMB78-NEXT: bic.w r0, r1, r0 408; THUMB78-NEXT: bx lr 409 %t0 = lshr i64 1, %y 410 %t1 = and i64 %t0, %x 411 %res = icmp eq i64 %t1, 0 412 ret i1 %res 413} 414 415define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind { 416; ARM6-LABEL: scalar_i64_bitsinmiddle_eq: 417; ARM6: @ %bb.0: 418; ARM6-NEXT: rsb r3, r2, #32 419; ARM6-NEXT: lsr r3, r0, r3 420; ARM6-NEXT: orr r1, r3, r1, lsl r2 421; ARM6-NEXT: subs r3, r2, #32 422; ARM6-NEXT: lslpl r1, r0, r3 423; ARM6-NEXT: lsl r0, r0, r2 424; ARM6-NEXT: movpl r0, #0 425; ARM6-NEXT: pkhbt r0, r1, r0 426; ARM6-NEXT: clz r0, r0 427; ARM6-NEXT: lsr r0, r0, #5 428; ARM6-NEXT: bx lr 429; 430; ARM78-LABEL: scalar_i64_bitsinmiddle_eq: 431; ARM78: @ %bb.0: 432; ARM78-NEXT: rsb r3, r2, #32 433; ARM78-NEXT: lsr r3, r0, r3 434; ARM78-NEXT: orr r1, r3, r1, lsl r2 435; ARM78-NEXT: subs r3, r2, #32 436; ARM78-NEXT: lslpl r1, r0, r3 437; ARM78-NEXT: lsl r0, r0, r2 438; ARM78-NEXT: movwpl r0, #0 439; ARM78-NEXT: pkhbt r0, r1, r0 440; ARM78-NEXT: clz r0, r0 441; ARM78-NEXT: lsr r0, r0, #5 442; ARM78-NEXT: bx lr 443; 444; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq: 445; THUMB6: @ %bb.0: 446; THUMB6-NEXT: push {r7, lr} 447; THUMB6-NEXT: bl __ashldi3 448; THUMB6-NEXT: ldr r2, .LCPI11_0 449; THUMB6-NEXT: ands r2, r0 450; THUMB6-NEXT: uxth r0, r1 451; THUMB6-NEXT: adds r1, r2, r0 452; THUMB6-NEXT: rsbs r0, r1, #0 453; THUMB6-NEXT: adcs r0, r1 454; THUMB6-NEXT: pop {r7, pc} 455; THUMB6-NEXT: .p2align 2 456; THUMB6-NEXT: @ %bb.1: 457; THUMB6-NEXT: .LCPI11_0: 458; THUMB6-NEXT: .long 4294901760 @ 0xffff0000 459; 460; THUMB78-LABEL: scalar_i64_bitsinmiddle_eq: 461; THUMB78: @ %bb.0: 462; THUMB78-NEXT: rsb.w r3, r2, #32 463; THUMB78-NEXT: lsls r1, r2 464; THUMB78-NEXT: lsr.w r3, r0, r3 465; THUMB78-NEXT: orrs r1, r3 466; THUMB78-NEXT: subs.w r3, r2, #32 467; THUMB78-NEXT: it pl 468; THUMB78-NEXT: lslpl.w r1, r0, r3 469; THUMB78-NEXT: lsl.w r0, r0, r2 470; THUMB78-NEXT: it pl 471; THUMB78-NEXT: movpl r0, #0 472; THUMB78-NEXT: pkhbt r0, r1, r0 473; THUMB78-NEXT: clz r0, r0 474; THUMB78-NEXT: lsrs r0, r0, #5 475; THUMB78-NEXT: bx lr 476 %t0 = lshr i64 281474976645120, %y 477 %t1 = and i64 %t0, %x 478 %res = icmp eq i64 %t1, 0 479 ret i1 %res 480} 481 482;------------------------------------------------------------------------------; 483; A few trivial vector tests 484;------------------------------------------------------------------------------; 485 486define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { 487; ARM6-LABEL: vec_4xi32_splat_eq: 488; ARM6: @ %bb.0: 489; ARM6-NEXT: push {r11, lr} 490; ARM6-NEXT: ldr r12, [sp, #8] 491; ARM6-NEXT: mov lr, #1 492; ARM6-NEXT: bic r0, lr, r0, lsl r12 493; ARM6-NEXT: ldr r12, [sp, #12] 494; ARM6-NEXT: bic r1, lr, r1, lsl r12 495; ARM6-NEXT: ldr r12, [sp, #16] 496; ARM6-NEXT: bic r2, lr, r2, lsl r12 497; ARM6-NEXT: ldr r12, [sp, #20] 498; ARM6-NEXT: bic r3, lr, r3, lsl r12 499; ARM6-NEXT: pop {r11, pc} 500; 501; ARM78-LABEL: vec_4xi32_splat_eq: 502; ARM78: @ %bb.0: 503; ARM78-NEXT: vmov d17, r2, r3 504; ARM78-NEXT: mov r12, sp 505; ARM78-NEXT: vld1.64 {d18, d19}, [r12] 506; ARM78-NEXT: vmov d16, r0, r1 507; ARM78-NEXT: vmov.i32 q10, #0x1 508; ARM78-NEXT: vshl.u32 q8, q8, q9 509; ARM78-NEXT: vtst.32 q8, q8, q10 510; ARM78-NEXT: vmvn q8, q8 511; ARM78-NEXT: vmovn.i32 d16, q8 512; ARM78-NEXT: vmov r0, r1, d16 513; ARM78-NEXT: bx lr 514; 515; THUMB6-LABEL: vec_4xi32_splat_eq: 516; THUMB6: @ %bb.0: 517; THUMB6-NEXT: push {r4, r5, r7, lr} 518; THUMB6-NEXT: ldr r4, [sp, #16] 519; THUMB6-NEXT: lsls r0, r4 520; THUMB6-NEXT: movs r4, #1 521; THUMB6-NEXT: ands r0, r4 522; THUMB6-NEXT: rsbs r5, r0, #0 523; THUMB6-NEXT: adcs r0, r5 524; THUMB6-NEXT: ldr r5, [sp, #20] 525; THUMB6-NEXT: lsls r1, r5 526; THUMB6-NEXT: ands r1, r4 527; THUMB6-NEXT: rsbs r5, r1, #0 528; THUMB6-NEXT: adcs r1, r5 529; THUMB6-NEXT: ldr r5, [sp, #24] 530; THUMB6-NEXT: lsls r2, r5 531; THUMB6-NEXT: ands r2, r4 532; THUMB6-NEXT: rsbs r5, r2, #0 533; THUMB6-NEXT: adcs r2, r5 534; THUMB6-NEXT: ldr r5, [sp, #28] 535; THUMB6-NEXT: lsls r3, r5 536; THUMB6-NEXT: ands r3, r4 537; THUMB6-NEXT: rsbs r4, r3, #0 538; THUMB6-NEXT: adcs r3, r4 539; THUMB6-NEXT: pop {r4, r5, r7, pc} 540; 541; THUMB78-LABEL: vec_4xi32_splat_eq: 542; THUMB78: @ %bb.0: 543; THUMB78-NEXT: vmov d17, r2, r3 544; THUMB78-NEXT: mov r12, sp 545; THUMB78-NEXT: vld1.64 {d18, d19}, [r12] 546; THUMB78-NEXT: vmov d16, r0, r1 547; THUMB78-NEXT: vmov.i32 q10, #0x1 548; THUMB78-NEXT: vshl.u32 q8, q8, q9 549; THUMB78-NEXT: vtst.32 q8, q8, q10 550; THUMB78-NEXT: vmvn q8, q8 551; THUMB78-NEXT: vmovn.i32 d16, q8 552; THUMB78-NEXT: vmov r0, r1, d16 553; THUMB78-NEXT: bx lr 554 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y 555 %t1 = and <4 x i32> %t0, %x 556 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> 557 ret <4 x i1> %res 558} 559 560define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { 561; ARM6-LABEL: vec_4xi32_nonsplat_eq: 562; ARM6: @ %bb.0: 563; ARM6-NEXT: ldr r12, [sp, #4] 564; ARM6-NEXT: mov r0, #1 565; ARM6-NEXT: bic r1, r0, r1, lsl r12 566; ARM6-NEXT: ldr r12, [sp, #8] 567; ARM6-NEXT: mov r0, #65280 568; ARM6-NEXT: orr r0, r0, #16711680 569; ARM6-NEXT: and r0, r0, r2, lsl r12 570; ARM6-NEXT: clz r0, r0 571; ARM6-NEXT: lsr r2, r0, #5 572; ARM6-NEXT: ldr r0, [sp, #12] 573; ARM6-NEXT: mvn r0, r3, lsl r0 574; ARM6-NEXT: lsr r3, r0, #31 575; ARM6-NEXT: mov r0, #1 576; ARM6-NEXT: bx lr 577; 578; ARM78-LABEL: vec_4xi32_nonsplat_eq: 579; ARM78: @ %bb.0: 580; ARM78-NEXT: mov r12, sp 581; ARM78-NEXT: vld1.64 {d16, d17}, [r12] 582; ARM78-NEXT: adr r12, .LCPI13_0 583; ARM78-NEXT: vneg.s32 q8, q8 584; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128] 585; ARM78-NEXT: vshl.u32 q8, q9, q8 586; ARM78-NEXT: vmov d19, r2, r3 587; ARM78-NEXT: vmov d18, r0, r1 588; ARM78-NEXT: vtst.32 q8, q8, q9 589; ARM78-NEXT: vmvn q8, q8 590; ARM78-NEXT: vmovn.i32 d16, q8 591; ARM78-NEXT: vmov r0, r1, d16 592; ARM78-NEXT: bx lr 593; ARM78-NEXT: .p2align 4 594; ARM78-NEXT: @ %bb.1: 595; ARM78-NEXT: .LCPI13_0: 596; ARM78-NEXT: .long 0 @ 0x0 597; ARM78-NEXT: .long 1 @ 0x1 598; ARM78-NEXT: .long 16776960 @ 0xffff00 599; ARM78-NEXT: .long 2147483648 @ 0x80000000 600; 601; THUMB6-LABEL: vec_4xi32_nonsplat_eq: 602; THUMB6: @ %bb.0: 603; THUMB6-NEXT: push {r4, lr} 604; THUMB6-NEXT: ldr r0, [sp, #12] 605; THUMB6-NEXT: lsls r1, r0 606; THUMB6-NEXT: movs r0, #1 607; THUMB6-NEXT: ands r1, r0 608; THUMB6-NEXT: rsbs r4, r1, #0 609; THUMB6-NEXT: adcs r1, r4 610; THUMB6-NEXT: ldr r4, [sp, #16] 611; THUMB6-NEXT: lsls r2, r4 612; THUMB6-NEXT: ldr r4, .LCPI13_0 613; THUMB6-NEXT: ands r2, r4 614; THUMB6-NEXT: rsbs r4, r2, #0 615; THUMB6-NEXT: adcs r2, r4 616; THUMB6-NEXT: ldr r4, [sp, #20] 617; THUMB6-NEXT: lsls r3, r4 618; THUMB6-NEXT: lsls r4, r0, #31 619; THUMB6-NEXT: ands r3, r4 620; THUMB6-NEXT: rsbs r4, r3, #0 621; THUMB6-NEXT: adcs r3, r4 622; THUMB6-NEXT: pop {r4, pc} 623; THUMB6-NEXT: .p2align 2 624; THUMB6-NEXT: @ %bb.1: 625; THUMB6-NEXT: .LCPI13_0: 626; THUMB6-NEXT: .long 16776960 @ 0xffff00 627; 628; THUMB78-LABEL: vec_4xi32_nonsplat_eq: 629; THUMB78: @ %bb.0: 630; THUMB78-NEXT: mov r12, sp 631; THUMB78-NEXT: vld1.64 {d16, d17}, [r12] 632; THUMB78-NEXT: adr.w r12, .LCPI13_0 633; THUMB78-NEXT: vneg.s32 q8, q8 634; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128] 635; THUMB78-NEXT: vshl.u32 q8, q9, q8 636; THUMB78-NEXT: vmov d19, r2, r3 637; THUMB78-NEXT: vmov d18, r0, r1 638; THUMB78-NEXT: vtst.32 q8, q8, q9 639; THUMB78-NEXT: vmvn q8, q8 640; THUMB78-NEXT: vmovn.i32 d16, q8 641; THUMB78-NEXT: vmov r0, r1, d16 642; THUMB78-NEXT: bx lr 643; THUMB78-NEXT: .p2align 4 644; THUMB78-NEXT: @ %bb.1: 645; THUMB78-NEXT: .LCPI13_0: 646; THUMB78-NEXT: .long 0 @ 0x0 647; THUMB78-NEXT: .long 1 @ 0x1 648; THUMB78-NEXT: .long 16776960 @ 0xffff00 649; THUMB78-NEXT: .long 2147483648 @ 0x80000000 650 %t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y 651 %t1 = and <4 x i32> %t0, %x 652 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> 653 ret <4 x i1> %res 654} 655 656define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { 657; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq: 658; ARM6: @ %bb.0: 659; ARM6-NEXT: push {r11, lr} 660; ARM6-NEXT: ldr r2, [sp, #12] 661; ARM6-NEXT: mov lr, #1 662; ARM6-NEXT: ldr r12, [sp, #8] 663; ARM6-NEXT: bic r1, lr, r1, lsl r2 664; ARM6-NEXT: ldr r2, [sp, #20] 665; ARM6-NEXT: bic r0, lr, r0, lsl r12 666; ARM6-NEXT: bic r3, lr, r3, lsl r2 667; ARM6-NEXT: mov r2, #1 668; ARM6-NEXT: pop {r11, pc} 669; 670; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq: 671; ARM78: @ %bb.0: 672; ARM78-NEXT: vmov d17, r2, r3 673; ARM78-NEXT: mov r12, sp 674; ARM78-NEXT: vld1.64 {d18, d19}, [r12] 675; ARM78-NEXT: vmov d16, r0, r1 676; ARM78-NEXT: vmov.i32 q10, #0x1 677; ARM78-NEXT: vshl.u32 q8, q8, q9 678; ARM78-NEXT: vtst.32 q8, q8, q10 679; ARM78-NEXT: vmvn q8, q8 680; ARM78-NEXT: vmovn.i32 d16, q8 681; ARM78-NEXT: vmov r0, r1, d16 682; ARM78-NEXT: bx lr 683; 684; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq: 685; THUMB6: @ %bb.0: 686; THUMB6-NEXT: push {r4, lr} 687; THUMB6-NEXT: ldr r2, [sp, #8] 688; THUMB6-NEXT: lsls r0, r2 689; THUMB6-NEXT: movs r2, #1 690; THUMB6-NEXT: ands r0, r2 691; THUMB6-NEXT: rsbs r4, r0, #0 692; THUMB6-NEXT: adcs r0, r4 693; THUMB6-NEXT: ldr r4, [sp, #12] 694; THUMB6-NEXT: lsls r1, r4 695; THUMB6-NEXT: ands r1, r2 696; THUMB6-NEXT: rsbs r4, r1, #0 697; THUMB6-NEXT: adcs r1, r4 698; THUMB6-NEXT: ldr r4, [sp, #20] 699; THUMB6-NEXT: lsls r3, r4 700; THUMB6-NEXT: ands r3, r2 701; THUMB6-NEXT: rsbs r4, r3, #0 702; THUMB6-NEXT: adcs r3, r4 703; THUMB6-NEXT: pop {r4, pc} 704; 705; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq: 706; THUMB78: @ %bb.0: 707; THUMB78-NEXT: vmov d17, r2, r3 708; THUMB78-NEXT: mov r12, sp 709; THUMB78-NEXT: vld1.64 {d18, d19}, [r12] 710; THUMB78-NEXT: vmov d16, r0, r1 711; THUMB78-NEXT: vmov.i32 q10, #0x1 712; THUMB78-NEXT: vshl.u32 q8, q8, q9 713; THUMB78-NEXT: vtst.32 q8, q8, q10 714; THUMB78-NEXT: vmvn q8, q8 715; THUMB78-NEXT: vmovn.i32 d16, q8 716; THUMB78-NEXT: vmov r0, r1, d16 717; THUMB78-NEXT: bx lr 718 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y 719 %t1 = and <4 x i32> %t0, %x 720 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> 721 ret <4 x i1> %res 722} 723define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind { 724; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq: 725; ARM6: @ %bb.0: 726; ARM6-NEXT: push {r11, lr} 727; ARM6-NEXT: ldr r2, [sp, #12] 728; ARM6-NEXT: mov lr, #1 729; ARM6-NEXT: ldr r12, [sp, #8] 730; ARM6-NEXT: bic r1, lr, r1, lsl r2 731; ARM6-NEXT: ldr r2, [sp, #20] 732; ARM6-NEXT: bic r0, lr, r0, lsl r12 733; ARM6-NEXT: bic r3, lr, r3, lsl r2 734; ARM6-NEXT: pop {r11, pc} 735; 736; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq: 737; ARM78: @ %bb.0: 738; ARM78-NEXT: mov r12, sp 739; ARM78-NEXT: vld1.64 {d16, d17}, [r12] 740; ARM78-NEXT: vmov.i32 q9, #0x1 741; ARM78-NEXT: vneg.s32 q8, q8 742; ARM78-NEXT: vshl.u32 q8, q9, q8 743; ARM78-NEXT: vmov d19, r2, r3 744; ARM78-NEXT: vmov d18, r0, r1 745; ARM78-NEXT: vtst.32 q8, q8, q9 746; ARM78-NEXT: vmvn q8, q8 747; ARM78-NEXT: vmovn.i32 d16, q8 748; ARM78-NEXT: vmov r0, r1, d16 749; ARM78-NEXT: bx lr 750; 751; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq: 752; THUMB6: @ %bb.0: 753; THUMB6-NEXT: push {r4, lr} 754; THUMB6-NEXT: ldr r2, [sp, #8] 755; THUMB6-NEXT: lsls r0, r2 756; THUMB6-NEXT: movs r2, #1 757; THUMB6-NEXT: ands r0, r2 758; THUMB6-NEXT: rsbs r4, r0, #0 759; THUMB6-NEXT: adcs r0, r4 760; THUMB6-NEXT: ldr r4, [sp, #12] 761; THUMB6-NEXT: lsls r1, r4 762; THUMB6-NEXT: ands r1, r2 763; THUMB6-NEXT: rsbs r4, r1, #0 764; THUMB6-NEXT: adcs r1, r4 765; THUMB6-NEXT: ldr r4, [sp, #20] 766; THUMB6-NEXT: lsls r3, r4 767; THUMB6-NEXT: ands r3, r2 768; THUMB6-NEXT: rsbs r2, r3, #0 769; THUMB6-NEXT: adcs r3, r2 770; THUMB6-NEXT: pop {r4, pc} 771; 772; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq: 773; THUMB78: @ %bb.0: 774; THUMB78-NEXT: mov r12, sp 775; THUMB78-NEXT: vld1.64 {d16, d17}, [r12] 776; THUMB78-NEXT: vmov.i32 q9, #0x1 777; THUMB78-NEXT: vneg.s32 q8, q8 778; THUMB78-NEXT: vshl.u32 q8, q9, q8 779; THUMB78-NEXT: vmov d19, r2, r3 780; THUMB78-NEXT: vmov d18, r0, r1 781; THUMB78-NEXT: vtst.32 q8, q8, q9 782; THUMB78-NEXT: vmvn q8, q8 783; THUMB78-NEXT: vmovn.i32 d16, q8 784; THUMB78-NEXT: vmov r0, r1, d16 785; THUMB78-NEXT: bx lr 786 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y 787 %t1 = and <4 x i32> %t0, %x 788 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0> 789 ret <4 x i1> %res 790} 791define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind { 792; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq: 793; ARM6: @ %bb.0: 794; ARM6-NEXT: push {r11, lr} 795; ARM6-NEXT: ldr r2, [sp, #12] 796; ARM6-NEXT: mov lr, #1 797; ARM6-NEXT: ldr r12, [sp, #8] 798; ARM6-NEXT: bic r1, lr, r1, lsl r2 799; ARM6-NEXT: ldr r2, [sp, #20] 800; ARM6-NEXT: bic r0, lr, r0, lsl r12 801; ARM6-NEXT: bic r3, lr, r3, lsl r2 802; ARM6-NEXT: pop {r11, pc} 803; 804; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq: 805; ARM78: @ %bb.0: 806; ARM78-NEXT: mov r12, sp 807; ARM78-NEXT: vld1.64 {d16, d17}, [r12] 808; ARM78-NEXT: vmov.i32 q9, #0x1 809; ARM78-NEXT: vneg.s32 q8, q8 810; ARM78-NEXT: vshl.u32 q8, q9, q8 811; ARM78-NEXT: vmov d19, r2, r3 812; ARM78-NEXT: vmov d18, r0, r1 813; ARM78-NEXT: vtst.32 q8, q8, q9 814; ARM78-NEXT: vmvn q8, q8 815; ARM78-NEXT: vmovn.i32 d16, q8 816; ARM78-NEXT: vmov r0, r1, d16 817; ARM78-NEXT: bx lr 818; 819; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq: 820; THUMB6: @ %bb.0: 821; THUMB6-NEXT: push {r4, lr} 822; THUMB6-NEXT: ldr r2, [sp, #8] 823; THUMB6-NEXT: lsls r0, r2 824; THUMB6-NEXT: movs r2, #1 825; THUMB6-NEXT: ands r0, r2 826; THUMB6-NEXT: rsbs r4, r0, #0 827; THUMB6-NEXT: adcs r0, r4 828; THUMB6-NEXT: ldr r4, [sp, #12] 829; THUMB6-NEXT: lsls r1, r4 830; THUMB6-NEXT: ands r1, r2 831; THUMB6-NEXT: rsbs r4, r1, #0 832; THUMB6-NEXT: adcs r1, r4 833; THUMB6-NEXT: ldr r4, [sp, #20] 834; THUMB6-NEXT: lsls r3, r4 835; THUMB6-NEXT: ands r3, r2 836; THUMB6-NEXT: rsbs r2, r3, #0 837; THUMB6-NEXT: adcs r3, r2 838; THUMB6-NEXT: pop {r4, pc} 839; 840; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq: 841; THUMB78: @ %bb.0: 842; THUMB78-NEXT: mov r12, sp 843; THUMB78-NEXT: vld1.64 {d16, d17}, [r12] 844; THUMB78-NEXT: vmov.i32 q9, #0x1 845; THUMB78-NEXT: vneg.s32 q8, q8 846; THUMB78-NEXT: vshl.u32 q8, q9, q8 847; THUMB78-NEXT: vmov d19, r2, r3 848; THUMB78-NEXT: vmov d18, r0, r1 849; THUMB78-NEXT: vtst.32 q8, q8, q9 850; THUMB78-NEXT: vmvn q8, q8 851; THUMB78-NEXT: vmovn.i32 d16, q8 852; THUMB78-NEXT: vmov r0, r1, d16 853; THUMB78-NEXT: bx lr 854 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y 855 %t1 = and <4 x i32> %t0, %x 856 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0> 857 ret <4 x i1> %res 858} 859 860;------------------------------------------------------------------------------; 861; A special tests 862;------------------------------------------------------------------------------; 863 864define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind { 865; ARM-LABEL: scalar_i8_signbit_ne: 866; ARM: @ %bb.0: 867; ARM-NEXT: uxtb r1, r1 868; ARM-NEXT: lsl r0, r0, r1 869; ARM-NEXT: uxtb r0, r0 870; ARM-NEXT: lsr r0, r0, #7 871; ARM-NEXT: bx lr 872; 873; THUMB-LABEL: scalar_i8_signbit_ne: 874; THUMB: @ %bb.0: 875; THUMB-NEXT: uxtb r1, r1 876; THUMB-NEXT: lsls r0, r1 877; THUMB-NEXT: uxtb r0, r0 878; THUMB-NEXT: lsrs r0, r0, #7 879; THUMB-NEXT: bx lr 880 %t0 = lshr i8 128, %y 881 %t1 = and i8 %t0, %x 882 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate 883 ret i1 %res 884} 885 886;------------------------------------------------------------------------------; 887; What if X is a constant too? 888;------------------------------------------------------------------------------; 889 890define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind { 891; ARM6-LABEL: scalar_i32_x_is_const_eq: 892; ARM6: @ %bb.0: 893; ARM6-NEXT: ldr r1, .LCPI18_0 894; ARM6-NEXT: mov r2, #1 895; ARM6-NEXT: bic r0, r2, r1, lsr r0 896; ARM6-NEXT: bx lr 897; ARM6-NEXT: .p2align 2 898; ARM6-NEXT: @ %bb.1: 899; ARM6-NEXT: .LCPI18_0: 900; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55 901; 902; ARM78-LABEL: scalar_i32_x_is_const_eq: 903; ARM78: @ %bb.0: 904; ARM78-NEXT: movw r1, #43605 905; ARM78-NEXT: mov r2, #1 906; ARM78-NEXT: movt r1, #43605 907; ARM78-NEXT: bic r0, r2, r1, lsr r0 908; ARM78-NEXT: bx lr 909; 910; THUMB6-LABEL: scalar_i32_x_is_const_eq: 911; THUMB6: @ %bb.0: 912; THUMB6-NEXT: ldr r1, .LCPI18_0 913; THUMB6-NEXT: lsrs r1, r0 914; THUMB6-NEXT: movs r2, #1 915; THUMB6-NEXT: ands r2, r1 916; THUMB6-NEXT: rsbs r0, r2, #0 917; THUMB6-NEXT: adcs r0, r2 918; THUMB6-NEXT: bx lr 919; THUMB6-NEXT: .p2align 2 920; THUMB6-NEXT: @ %bb.1: 921; THUMB6-NEXT: .LCPI18_0: 922; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55 923; 924; THUMB78-LABEL: scalar_i32_x_is_const_eq: 925; THUMB78: @ %bb.0: 926; THUMB78-NEXT: movw r1, #43605 927; THUMB78-NEXT: movt r1, #43605 928; THUMB78-NEXT: lsr.w r0, r1, r0 929; THUMB78-NEXT: movs r1, #1 930; THUMB78-NEXT: bic.w r0, r1, r0 931; THUMB78-NEXT: bx lr 932 %t0 = lshr i32 2857740885, %y 933 %t1 = and i32 %t0, 1 934 %res = icmp eq i32 %t1, 0 935 ret i1 %res 936} 937define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind { 938; ARM-LABEL: scalar_i32_x_is_const2_eq: 939; ARM: @ %bb.0: 940; ARM-NEXT: mov r1, #1 941; ARM-NEXT: eor r0, r1, r1, lsr r0 942; ARM-NEXT: bx lr 943; 944; THUMB6-LABEL: scalar_i32_x_is_const2_eq: 945; THUMB6: @ %bb.0: 946; THUMB6-NEXT: movs r1, #1 947; THUMB6-NEXT: lsrs r1, r0 948; THUMB6-NEXT: rsbs r0, r1, #0 949; THUMB6-NEXT: adcs r0, r1 950; THUMB6-NEXT: bx lr 951; 952; THUMB78-LABEL: scalar_i32_x_is_const2_eq: 953; THUMB78: @ %bb.0: 954; THUMB78-NEXT: movs r1, #1 955; THUMB78-NEXT: lsr.w r0, r1, r0 956; THUMB78-NEXT: eor r0, r0, #1 957; THUMB78-NEXT: bx lr 958 %t0 = lshr i32 1, %y 959 %t1 = and i32 %t0, 2857740885 960 %res = icmp eq i32 %t1, 0 961 ret i1 %res 962} 963 964;------------------------------------------------------------------------------; 965; A few negative tests 966;------------------------------------------------------------------------------; 967 968define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind { 969; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt: 970; ARM6: @ %bb.0: 971; ARM6-NEXT: uxtb r1, r1 972; ARM6-NEXT: mov r2, #24 973; ARM6-NEXT: ands r0, r0, r2, lsr r1 974; ARM6-NEXT: mov r0, #0 975; ARM6-NEXT: movmi r0, #1 976; ARM6-NEXT: bx lr 977; 978; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt: 979; ARM78: @ %bb.0: 980; ARM78-NEXT: uxtb r1, r1 981; ARM78-NEXT: mov r2, #24 982; ARM78-NEXT: ands r0, r0, r2, lsr r1 983; ARM78-NEXT: mov r0, #0 984; ARM78-NEXT: movwmi r0, #1 985; ARM78-NEXT: bx lr 986; 987; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt: 988; THUMB6: @ %bb.0: 989; THUMB6-NEXT: uxtb r1, r1 990; THUMB6-NEXT: movs r2, #24 991; THUMB6-NEXT: lsrs r2, r1 992; THUMB6-NEXT: ands r2, r0 993; THUMB6-NEXT: bmi .LBB20_2 994; THUMB6-NEXT: @ %bb.1: 995; THUMB6-NEXT: movs r0, #0 996; THUMB6-NEXT: bx lr 997; THUMB6-NEXT: .LBB20_2: 998; THUMB6-NEXT: movs r0, #1 999; THUMB6-NEXT: bx lr 1000; 1001; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt: 1002; THUMB78: @ %bb.0: 1003; THUMB78-NEXT: uxtb r1, r1 1004; THUMB78-NEXT: movs r2, #24 1005; THUMB78-NEXT: lsr.w r1, r2, r1 1006; THUMB78-NEXT: ands r0, r1 1007; THUMB78-NEXT: mov.w r0, #0 1008; THUMB78-NEXT: it mi 1009; THUMB78-NEXT: movmi r0, #1 1010; THUMB78-NEXT: bx lr 1011 %t0 = lshr i8 24, %y 1012 %t1 = and i8 %t0, %x 1013 %res = icmp slt i8 %t1, 0 1014 ret i1 %res 1015} 1016 1017define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind { 1018; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero: 1019; ARM: @ %bb.0: 1020; ARM-NEXT: uxtb r1, r1 1021; ARM-NEXT: mov r2, #128 1022; ARM-NEXT: and r0, r0, r2, lsr r1 1023; ARM-NEXT: sub r0, r0, #1 1024; ARM-NEXT: clz r0, r0 1025; ARM-NEXT: lsr r0, r0, #5 1026; ARM-NEXT: bx lr 1027; 1028; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero: 1029; THUMB6: @ %bb.0: 1030; THUMB6-NEXT: uxtb r1, r1 1031; THUMB6-NEXT: movs r2, #128 1032; THUMB6-NEXT: lsrs r2, r1 1033; THUMB6-NEXT: ands r2, r0 1034; THUMB6-NEXT: subs r1, r2, #1 1035; THUMB6-NEXT: rsbs r0, r1, #0 1036; THUMB6-NEXT: adcs r0, r1 1037; THUMB6-NEXT: bx lr 1038; 1039; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero: 1040; THUMB78: @ %bb.0: 1041; THUMB78-NEXT: uxtb r1, r1 1042; THUMB78-NEXT: movs r2, #128 1043; THUMB78-NEXT: lsr.w r1, r2, r1 1044; THUMB78-NEXT: ands r0, r1 1045; THUMB78-NEXT: subs r0, #1 1046; THUMB78-NEXT: clz r0, r0 1047; THUMB78-NEXT: lsrs r0, r0, #5 1048; THUMB78-NEXT: bx lr 1049 %t0 = lshr i8 128, %y 1050 %t1 = and i8 %t0, %x 1051 %res = icmp eq i8 %t1, 1 ; should be comparing with 0 1052 ret i1 %res 1053} 1054