1*a7662014SOliver Stannard; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*a7662014SOliver Stannard; RUN: llc -mtriple armv8a-none-none-eabihf -mattr=fullfp16 < %s | FileCheck %s 3*a7662014SOliver Stannard 4*a7662014SOliver Stannarddefine <4 x half> @fptrunc_vector_f32_f16(<4 x float> %a) { 5*a7662014SOliver Stannard; CHECK-LABEL: fptrunc_vector_f32_f16: 6*a7662014SOliver Stannard; CHECK: @ %bb.0: @ %bb 7*a7662014SOliver Stannard; CHECK-NEXT: vcvt.f16.f32 d0, q0 8*a7662014SOliver Stannard; CHECK-NEXT: bx lr 9*a7662014SOliver Stannardbb: 10*a7662014SOliver Stannard %z = fptrunc <4 x float> %a to <4 x half> 11*a7662014SOliver Stannard ret <4 x half> %z 12*a7662014SOliver Stannard} 13*a7662014SOliver Stannard 14*a7662014SOliver Stannarddefine <4 x half> @fptrunc_vector_f64_f16(<4 x double> %a) { 15*a7662014SOliver Stannard; CHECK-LABEL: fptrunc_vector_f64_f16: 16*a7662014SOliver Stannard; CHECK: @ %bb.0: @ %bb 17*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f16.f64 s0, d0 18*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f16.f64 s8, d1 19*a7662014SOliver Stannard; CHECK-NEXT: vmov r1, s0 20*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f16.f64 s2, d2 21*a7662014SOliver Stannard; CHECK-NEXT: vmov r0, s8 22*a7662014SOliver Stannard; CHECK-NEXT: vmov.16 d0[0], r1 23*a7662014SOliver Stannard; CHECK-NEXT: vmov.16 d0[1], r0 24*a7662014SOliver Stannard; CHECK-NEXT: vmov r0, s2 25*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f16.f64 s2, d3 26*a7662014SOliver Stannard; CHECK-NEXT: vmov.16 d0[2], r0 27*a7662014SOliver Stannard; CHECK-NEXT: vmov r0, s2 28*a7662014SOliver Stannard; CHECK-NEXT: vmov.16 d0[3], r0 29*a7662014SOliver Stannard; CHECK-NEXT: bx lr 30*a7662014SOliver Stannardbb: 31*a7662014SOliver Stannard %z = fptrunc <4 x double> %a to <4 x half> 32*a7662014SOliver Stannard ret <4 x half> %z 33*a7662014SOliver Stannard} 34*a7662014SOliver Stannard 35*a7662014SOliver Stannarddefine <4 x float> @fpext_vector_f16_f32(<4 x half> %a) { 36*a7662014SOliver Stannard; CHECK-LABEL: fpext_vector_f16_f32: 37*a7662014SOliver Stannard; CHECK: @ %bb.0: @ %bb 38*a7662014SOliver Stannard; CHECK-NEXT: vcvt.f32.f16 q0, d0 39*a7662014SOliver Stannard; CHECK-NEXT: bx lr 40*a7662014SOliver Stannardbb: 41*a7662014SOliver Stannard %z = fpext <4 x half> %a to <4 x float> 42*a7662014SOliver Stannard ret <4 x float> %z 43*a7662014SOliver Stannard} 44*a7662014SOliver Stannard 45*a7662014SOliver Stannarddefine <4 x double> @fpext_vector_f16_f64(<4 x half> %a) { 46*a7662014SOliver Stannard; CHECK-LABEL: fpext_vector_f16_f64: 47*a7662014SOliver Stannard; CHECK: @ %bb.0: @ %bb 48*a7662014SOliver Stannard; CHECK-NEXT: vmovx.f16 s4, s0 49*a7662014SOliver Stannard; CHECK-NEXT: vmovx.f16 s2, s1 50*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f64.f16 d17, s4 51*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f64.f16 d3, s2 52*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f64.f16 d16, s0 53*a7662014SOliver Stannard; CHECK-NEXT: vcvtb.f64.f16 d2, s1 54*a7662014SOliver Stannard; CHECK-NEXT: vorr q0, q8, q8 55*a7662014SOliver Stannard; CHECK-NEXT: bx lr 56*a7662014SOliver Stannardbb: 57*a7662014SOliver Stannard %z = fpext <4 x half> %a to <4 x double> 58*a7662014SOliver Stannard ret <4 x double> %z 59*a7662014SOliver Stannard} 60