1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD 3; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT 4 5define float @test_vget_lane_f16_1(<4 x half> %a) nounwind { 6; CHECKHARD-LABEL: test_vget_lane_f16_1: 7; CHECKHARD: @ %bb.0: @ %entry 8; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s0 9; CHECKHARD-NEXT: bx lr 10; 11; CHECKSOFT-LABEL: test_vget_lane_f16_1: 12; CHECKSOFT: @ %bb.0: @ %entry 13; CHECKSOFT-NEXT: vmov d0, r0, r1 14; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s0 15; CHECKSOFT-NEXT: vmov r0, s0 16; CHECKSOFT-NEXT: bx lr 17entry: 18 %elt = extractelement <4 x half> %a, i32 1 19 %conv = fpext half %elt to float 20 ret float %conv 21} 22 23define float @test_vget_lane_f16_2(<4 x half> %a) nounwind { 24; CHECKHARD-LABEL: test_vget_lane_f16_2: 25; CHECKHARD: @ %bb.0: @ %entry 26; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s1 27; CHECKHARD-NEXT: bx lr 28; 29; CHECKSOFT-LABEL: test_vget_lane_f16_2: 30; CHECKSOFT: @ %bb.0: @ %entry 31; CHECKSOFT-NEXT: vmov d0, r0, r1 32; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s1 33; CHECKSOFT-NEXT: vmov r0, s0 34; CHECKSOFT-NEXT: bx lr 35entry: 36 %elt = extractelement <4 x half> %a, i32 2 37 %conv = fpext half %elt to float 38 ret float %conv 39} 40 41define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind { 42; CHECKHARD-LABEL: test_vget_laneq_f16_6: 43; CHECKHARD: @ %bb.0: @ %entry 44; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s3 45; CHECKHARD-NEXT: bx lr 46; 47; CHECKSOFT-LABEL: test_vget_laneq_f16_6: 48; CHECKSOFT: @ %bb.0: @ %entry 49; CHECKSOFT-NEXT: vmov d1, r2, r3 50; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s3 51; CHECKSOFT-NEXT: vmov r0, s0 52; CHECKSOFT-NEXT: bx lr 53entry: 54 %elt = extractelement <8 x half> %a, i32 6 55 %conv = fpext half %elt to float 56 ret float %conv 57} 58 59define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind { 60; CHECKHARD-LABEL: test_vget_laneq_f16_7: 61; CHECKHARD: @ %bb.0: @ %entry 62; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s3 63; CHECKHARD-NEXT: bx lr 64; 65; CHECKSOFT-LABEL: test_vget_laneq_f16_7: 66; CHECKSOFT: @ %bb.0: @ %entry 67; CHECKSOFT-NEXT: vmov d1, r2, r3 68; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s3 69; CHECKSOFT-NEXT: vmov r0, s0 70; CHECKSOFT-NEXT: bx lr 71entry: 72 %elt = extractelement <8 x half> %a, i32 7 73 %conv = fpext half %elt to float 74 ret float %conv 75} 76 77define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind { 78; CHECKHARD-LABEL: test_vset_lane_f16: 79; CHECKHARD: @ %bb.0: @ %entry 80; CHECKHARD-NEXT: vcvtb.f16.f32 s2, s2 81; CHECKHARD-NEXT: vmov r0, s2 82; CHECKHARD-NEXT: vmov.16 d0[3], r0 83; CHECKHARD-NEXT: bx lr 84; 85; CHECKSOFT-LABEL: test_vset_lane_f16: 86; CHECKSOFT: @ %bb.0: @ %entry 87; CHECKSOFT-NEXT: vmov s0, r2 88; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 89; CHECKSOFT-NEXT: vmov d16, r0, r1 90; CHECKSOFT-NEXT: vmov r2, s0 91; CHECKSOFT-NEXT: vmov.16 d16[3], r2 92; CHECKSOFT-NEXT: vmov r0, r1, d16 93; CHECKSOFT-NEXT: bx lr 94entry: 95 %b = fptrunc float %fb to half 96 %x = insertelement <4 x half> %a, half %b, i32 3 97 ret <4 x half> %x 98} 99 100define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind { 101; CHECKHARD-LABEL: test_vset_laneq_f16_1: 102; CHECKHARD: @ %bb.0: @ %entry 103; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4 104; CHECKHARD-NEXT: vmov r0, s4 105; CHECKHARD-NEXT: vmov.16 d0[1], r0 106; CHECKHARD-NEXT: bx lr 107; 108; CHECKSOFT-LABEL: test_vset_laneq_f16_1: 109; CHECKSOFT: @ %bb.0: @ %entry 110; CHECKSOFT-NEXT: vldr s0, [sp] 111; CHECKSOFT-NEXT: vmov d17, r2, r3 112; CHECKSOFT-NEXT: vmov d16, r0, r1 113; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 114; CHECKSOFT-NEXT: vmov r12, s0 115; CHECKSOFT-NEXT: vmov.16 d16[1], r12 116; CHECKSOFT-NEXT: vmov r2, r3, d17 117; CHECKSOFT-NEXT: vmov r0, r1, d16 118; CHECKSOFT-NEXT: bx lr 119entry: 120 %b = fptrunc float %fb to half 121 %x = insertelement <8 x half> %a, half %b, i32 1 122 ret <8 x half> %x 123} 124 125define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind { 126; CHECKHARD-LABEL: test_vset_laneq_f16_7: 127; CHECKHARD: @ %bb.0: @ %entry 128; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4 129; CHECKHARD-NEXT: vmov r0, s4 130; CHECKHARD-NEXT: vmov.16 d1[3], r0 131; CHECKHARD-NEXT: bx lr 132; 133; CHECKSOFT-LABEL: test_vset_laneq_f16_7: 134; CHECKSOFT: @ %bb.0: @ %entry 135; CHECKSOFT-NEXT: vldr s0, [sp] 136; CHECKSOFT-NEXT: vmov d17, r2, r3 137; CHECKSOFT-NEXT: vmov d16, r0, r1 138; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 139; CHECKSOFT-NEXT: vmov r12, s0 140; CHECKSOFT-NEXT: vmov.16 d17[3], r12 141; CHECKSOFT-NEXT: vmov r0, r1, d16 142; CHECKSOFT-NEXT: vmov r2, r3, d17 143; CHECKSOFT-NEXT: bx lr 144entry: 145 %b = fptrunc float %fb to half 146 %x = insertelement <8 x half> %a, half %b, i32 7 147 ret <8 x half> %x 148} 149