xref: /llvm-project/llvm/test/CodeGen/ARM/fp16-insert-extract.ll (revision 61ef2d27c4fe3a46d8c4905bd1fb6fd64d15fed2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD
3; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT
4
5define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
6; CHECKHARD-LABEL: test_vget_lane_f16_1:
7; CHECKHARD:       @ %bb.0: @ %entry
8; CHECKHARD-NEXT:    vmovx.f16 s0, s0
9; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s0
10; CHECKHARD-NEXT:    bx lr
11;
12; CHECKSOFT-LABEL: test_vget_lane_f16_1:
13; CHECKSOFT:       @ %bb.0: @ %entry
14; CHECKSOFT-NEXT:    vmov d0, r0, r1
15; CHECKSOFT-NEXT:    vmovx.f16 s0, s0
16; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s0
17; CHECKSOFT-NEXT:    vmov r0, s0
18; CHECKSOFT-NEXT:    bx lr
19entry:
20  %elt = extractelement <4 x half> %a, i32 1
21  %conv = fpext half %elt to float
22  ret float %conv
23}
24
25define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
26; CHECKHARD-LABEL: test_vget_lane_f16_2:
27; CHECKHARD:       @ %bb.0: @ %entry
28; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s1
29; CHECKHARD-NEXT:    bx lr
30;
31; CHECKSOFT-LABEL: test_vget_lane_f16_2:
32; CHECKSOFT:       @ %bb.0: @ %entry
33; CHECKSOFT-NEXT:    vmov d0, r0, r1
34; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s1
35; CHECKSOFT-NEXT:    vmov r0, s0
36; CHECKSOFT-NEXT:    bx lr
37entry:
38  %elt = extractelement <4 x half> %a, i32 2
39  %conv = fpext half %elt to float
40  ret float %conv
41}
42
43define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
44; CHECKHARD-LABEL: test_vget_laneq_f16_6:
45; CHECKHARD:       @ %bb.0: @ %entry
46; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s3
47; CHECKHARD-NEXT:    bx lr
48;
49; CHECKSOFT-LABEL: test_vget_laneq_f16_6:
50; CHECKSOFT:       @ %bb.0: @ %entry
51; CHECKSOFT-NEXT:    vmov d1, r2, r3
52; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s3
53; CHECKSOFT-NEXT:    vmov r0, s0
54; CHECKSOFT-NEXT:    bx lr
55entry:
56  %elt = extractelement <8 x half> %a, i32 6
57  %conv = fpext half %elt to float
58  ret float %conv
59}
60
61define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
62; CHECKHARD-LABEL: test_vget_laneq_f16_7:
63; CHECKHARD:       @ %bb.0: @ %entry
64; CHECKHARD-NEXT:    vmovx.f16 s0, s3
65; CHECKHARD-NEXT:    vcvtb.f32.f16 s0, s0
66; CHECKHARD-NEXT:    bx lr
67;
68; CHECKSOFT-LABEL: test_vget_laneq_f16_7:
69; CHECKSOFT:       @ %bb.0: @ %entry
70; CHECKSOFT-NEXT:    vmov d1, r2, r3
71; CHECKSOFT-NEXT:    vmovx.f16 s0, s3
72; CHECKSOFT-NEXT:    vcvtb.f32.f16 s0, s0
73; CHECKSOFT-NEXT:    vmov r0, s0
74; CHECKSOFT-NEXT:    bx lr
75entry:
76  %elt = extractelement <8 x half> %a, i32 7
77  %conv = fpext half %elt to float
78  ret float %conv
79}
80
81define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
82; CHECKHARD-LABEL: test_vset_lane_f16:
83; CHECKHARD:       @ %bb.0: @ %entry
84; CHECKHARD-NEXT:    vcvtb.f16.f32 s2, s2
85; CHECKHARD-NEXT:    vmov.f16 r0, s2
86; CHECKHARD-NEXT:    vmov.16 d0[3], r0
87; CHECKHARD-NEXT:    bx lr
88;
89; CHECKSOFT-LABEL: test_vset_lane_f16:
90; CHECKSOFT:       @ %bb.0: @ %entry
91; CHECKSOFT-NEXT:    vmov s0, r2
92; CHECKSOFT-NEXT:    vcvtb.f16.f32 s0, s0
93; CHECKSOFT-NEXT:    vmov d16, r0, r1
94; CHECKSOFT-NEXT:    vmov.f16 r2, s0
95; CHECKSOFT-NEXT:    vmov.16 d16[3], r2
96; CHECKSOFT-NEXT:    vmov r0, r1, d16
97; CHECKSOFT-NEXT:    bx lr
98entry:
99  %b = fptrunc float %fb to half
100  %x = insertelement <4 x half> %a, half %b, i32 3
101  ret <4 x half> %x
102}
103
104define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
105; CHECKHARD-LABEL: test_vset_laneq_f16_1:
106; CHECKHARD:       @ %bb.0: @ %entry
107; CHECKHARD-NEXT:    vcvtb.f16.f32 s4, s4
108; CHECKHARD-NEXT:    vmov.f16 r0, s4
109; CHECKHARD-NEXT:    vmov.16 d0[1], r0
110; CHECKHARD-NEXT:    bx lr
111;
112; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
113; CHECKSOFT:       @ %bb.0: @ %entry
114; CHECKSOFT-NEXT:    vldr s0, [sp]
115; CHECKSOFT-NEXT:    vmov d17, r2, r3
116; CHECKSOFT-NEXT:    vmov d16, r0, r1
117; CHECKSOFT-NEXT:    vcvtb.f16.f32 s0, s0
118; CHECKSOFT-NEXT:    vmov.f16 r12, s0
119; CHECKSOFT-NEXT:    vmov.16 d16[1], r12
120; CHECKSOFT-NEXT:    vmov r2, r3, d17
121; CHECKSOFT-NEXT:    vmov r0, r1, d16
122; CHECKSOFT-NEXT:    bx lr
123entry:
124  %b = fptrunc float %fb to half
125  %x = insertelement <8 x half> %a, half %b, i32 1
126  ret <8 x half> %x
127}
128
129define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
130; CHECKHARD-LABEL: test_vset_laneq_f16_7:
131; CHECKHARD:       @ %bb.0: @ %entry
132; CHECKHARD-NEXT:    vcvtb.f16.f32 s4, s4
133; CHECKHARD-NEXT:    vmov.f16 r0, s4
134; CHECKHARD-NEXT:    vmov.16 d1[3], r0
135; CHECKHARD-NEXT:    bx lr
136;
137; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
138; CHECKSOFT:       @ %bb.0: @ %entry
139; CHECKSOFT-NEXT:    vldr s0, [sp]
140; CHECKSOFT-NEXT:    vmov d17, r2, r3
141; CHECKSOFT-NEXT:    vmov d16, r0, r1
142; CHECKSOFT-NEXT:    vcvtb.f16.f32 s0, s0
143; CHECKSOFT-NEXT:    vmov.f16 r12, s0
144; CHECKSOFT-NEXT:    vmov.16 d17[3], r12
145; CHECKSOFT-NEXT:    vmov r0, r1, d16
146; CHECKSOFT-NEXT:    vmov r2, r3, d17
147; CHECKSOFT-NEXT:    bx lr
148entry:
149  %b = fptrunc float %fb to half
150  %x = insertelement <8 x half> %a, half %b, i32 7
151  ret <8 x half> %x
152}
153