1; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM 2; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB 3 4; Test sitofp 5 6define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { 7entry: 8; ARM: sitofp_single_i32 9; ARM: vmov s0, r0 10; ARM: vcvt.f32.s32 s0, s0 11; THUMB: sitofp_single_i32 12; THUMB: vmov s0, r0 13; THUMB: vcvt.f32.s32 s0, s0 14 %b.addr = alloca float, align 4 15 %conv = sitofp i32 %a to float 16 store float %conv, float* %b.addr, align 4 17 ret void 18} 19 20define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { 21entry: 22; ARM: sitofp_single_i16 23; ARM: sxth r0, r0 24; ARM: vmov s0, r0 25; ARM: vcvt.f32.s32 s0, s0 26; THUMB: sitofp_single_i16 27; THUMB: sxth r0, r0 28; THUMB: vmov s0, r0 29; THUMB: vcvt.f32.s32 s0, s0 30 %b.addr = alloca float, align 4 31 %conv = sitofp i16 %a to float 32 store float %conv, float* %b.addr, align 4 33 ret void 34} 35 36define void @sitofp_single_i8(i8 %a) nounwind ssp { 37entry: 38; ARM: sitofp_single_i8 39; ARM: sxtb r0, r0 40; ARM: vmov s0, r0 41; ARM: vcvt.f32.s32 s0, s0 42; THUMB: sitofp_single_i8 43; THUMB: sxtb r0, r0 44; THUMB: vmov s0, r0 45; THUMB: vcvt.f32.s32 s0, s0 46 %b.addr = alloca float, align 4 47 %conv = sitofp i8 %a to float 48 store float %conv, float* %b.addr, align 4 49 ret void 50} 51 52define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { 53entry: 54; ARM: sitofp_double_i32 55; ARM: vmov s0, r0 56; ARM: vcvt.f64.s32 d16, s0 57; THUMB: sitofp_double_i32 58; THUMB: vmov s0, r0 59; THUMB: vcvt.f64.s32 d16, s0 60 %b.addr = alloca double, align 8 61 %conv = sitofp i32 %a to double 62 store double %conv, double* %b.addr, align 8 63 ret void 64} 65 66define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { 67entry: 68; ARM: sitofp_double_i16 69; ARM: sxth r0, r0 70; ARM: vmov s0, r0 71; ARM: vcvt.f64.s32 d16, s0 72; THUMB: sitofp_double_i16 73; THUMB: sxth r0, r0 74; THUMB: vmov s0, r0 75; THUMB: vcvt.f64.s32 d16, s0 76 %b.addr = alloca double, align 8 77 %conv = sitofp i16 %a to double 78 store double %conv, double* %b.addr, align 8 79 ret void 80} 81 82define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { 83entry: 84; ARM: sitofp_double_i8 85; ARM: sxtb r0, r0 86; ARM: vmov s0, r0 87; ARM: vcvt.f64.s32 d16, s0 88; THUMB: sitofp_double_i8 89; THUMB: sxtb r0, r0 90; THUMB: vmov s0, r0 91; THUMB: vcvt.f64.s32 d16, s0 92 %b.addr = alloca double, align 8 93 %conv = sitofp i8 %a to double 94 store double %conv, double* %b.addr, align 8 95 ret void 96} 97